Sony IMX135 Exmor RS 13 Mp Stacked CMOS Image Sensor Circuit Analysis of Row Control, Column Data Readout and Control, and Ramp Generator 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
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Overview Introduction Brief Design Overview Component Descriptions Device Summary Figures To view, please click on the appropriate bookmark in the panel on the left. 0.1.1 Package Photographs Camera Module 0.1.2 Package X-Rays Camera Module 0.1.3 Package Photograph Image Sensor 0.2.1 Die Photograph (ISP Die) Depot 0.2.2 Die Photograph (ISP Die) Polysilicon Layer 0.2.3 Die Architecture (ISP Die) 0.2.4 Die Photograph (CIS Die) Depot 0.2.5 Annotated Die Photograph (CIS Die) Polysilicon Layer 0.3.1 Shared Pixel Schematic 0.3.2 Pixels at Poly Schematics 2.0.0 Row Driver 2.1.0 Row Decoder 2.1.1 Level Shifter 2.1.2 Level Shifter 2.1.3 RS Latch 2.1.4 NAND Gate 2.2.0 Level Shifter 2.3.0 Inverter 2.4.0 Level Shifter 2.5.0 Unused Circuits 1 3.0.0 Column Readouts 3.1.0 Two Column Block 3.1.1 Column Stage 1 3.1.1.1 Column Latch 3.1.2 Column Stage 2 3.1.2.1 Latch 3.1.2.2 XNOR Gate
3.1.2.3 XOR Gate 3.1.3 Column Stage 3 Counter 3.1.3.1 Counter Cell 1 3.1.3.2 Counter Cell 2 3.1.3.3 Counter Cell 3 3.1.3.4 2-to-1 MUX 3.1.4 Inverters 3.2.0 Column Output Latch 3.2.1 Latch and MUX 3.2.1.1 4-to-1 MUX 3.3.0 Column Output Latch 3.3.1 Latch and MUX 3.3.1.1 4-to-1 MUX 3.4.0 Dummy Column Output Latch 3.4.1 Latch and MUX 3.4.1.1 2-to-1 MUX 3.5.0 Buffers 3.5.1 Buffer 3.6.0 Shift Register 3.6.1 Shift Register 1 3.6.2 Shift Register 2 3.6.3 Programmable Delay 3.7.0 Reset Buffers 3.8.0 Column Stage 1 Control 3.8.1 B_TRIGATE 3.9.0 Column Control 2 3.10.0 Column Control 3 3.10.1 Column Control 3A 3.11.0 Column Control 4 3.12.0 Column Control 5 3.13.0 Unused Circuits 2 3.13.1 Unused Circuits 2A 3.13.2 Unused Circuits 2B 3.13.3 Unused Circuits 2C 3.14.0 Column Control (Left Side) 3.14.1 Shift Register (Left Side) 3.14.1.1 Shift Register 1 (Left Side) 3.14.1.2 Shift Register 2 (Left Side) 3.14.1.2.1 Buffer 3.14.1.3 Programmable Delay (Left Side)
3.14.2 Clock Circuit 1 (Left Side) 3.14.2.1 A_INV_DELAY2 3.14.2.2 A_BUFF3 3.14.3 Clock Circuit 2 (Left Side) 3.14.3.1 Counter (Left Side) 3.14.3.1.1 Timing Decoder (Left Side) 3.14.3.1.2 8-to-1 MUX 3.14.4 A_MUX21A 3.14.5 A_MUX21B 3.14.6 Buffers 3.14.6.1 Buffer 3.14.7 A_UNUSED2 3.14.7.1 A_UNUSED1 4.0.0 Analog Block 5.0.0 Control Logic 5.1.0 Level Shifter 1 5.2.0 Level Shifter 2 5.3.0 Level Shifter 3 5.4.0 Level Shifter 4 6.0.0 Ramp Generator 6.1.0 Loading Resistors 6.1.1 Level Shifter 6.2.0 Ramp Current 1 6.2.1 Decoder 6.2.2 Signal Selection 6.2.2.1 Unused 1 6.2.2.2 Unused 2 6.2.3 Current Steering 6.2.3.1 Steering Cell M16X 6.2.3.2 Steering Cell M2X 6.2.3.3 Steering Cell M8X 6.2.3.4 Steering Cell M4X 6.2.3.5 Steering Cell L1X 6.2.3.6 Steering Cell L2X 6.2.3.7 Steering Cell L4X 6.2.3.8 Steering Cell L8X 6.2.3.9 Unused
6.2.4 Bias Generator 6.2.4.1 V to I 6.2.4.1.1 Amplifier 6.2.4.1.2 Unused 6.2.5 S to P 11B 6.3.0 Ramp Current 2 6.3.1 Signal Selection 6.3.1.1 Unused 6.3.2 Current Sink 6.3.2.1 Unused 6.3.2.2 Data Buffer 2 6.3.2.2.1 Level Shifter 6.3.2.3 Bias Voltages 6.3.3 Current Steering 6.3.3.1 Steering Cell 1X 6.3.3.2 Steering Cell 2X 6.3.3.3 Steering Cell 4X 6.3.3.4 Steering Cell M2X 6.3.3.5 Bias Generator 6.3.3.5.1 Unused 6.3.3.6 Steering Cell LSB 6.3.4 Data Buffers 6.3.5 Logic 6.3.5.1 Counter 6.3.5.2 Unused 6.3.5.3 S to P 5B 6.3.6 Instruction 1 6.3.6.1 Unused 6.3.7 Decoder 6.3.8 Instruction 2 6.4.0 AND 6.5.0 Ramp Current 3 6.5.1 Current Cell 2X 6.5.2 Current Cell 2X32 6.5.3 Current Cell 2X16 6.5.4 Current Cell 2X8 6.5.5 Current Cell 2X4 6.5.6 Current Cell 2X2 6.5.7 Control
6.5.8 Bias Current 6.5.8.1 Programmable C1 6.5.8.1.1 Switchable C 6.5.8.2 Current with Ripple 6.5.8.2.1 Mirrored Current 6.5.8.3 Programmable C2 6.5.8.3.1 Switchable C 6.5.9 Unused 6.5.10 Data Buffers 7.0.0 Voltage Generators 1 7.1.0 Reference Current 1 7.1.1 V to I 7.1.1.1 Amplifier 7.2.0 Reference Current 2 7.3.0 Reference Current 3 7.4.0 Data Buffers 7.5.0 Unused 7.6.0 Reference Current 4 7.7.0 Test Output 7.7.1 Decoder 7.7.2 Amplifier 7.7.2.1 Unused 7.8.0 Bandgap Reference 7.8.1 Amplifier 7.8.1.1 NMOS X40 7.8.2 Bias Currents 7.8.3 Unused 7.8.4 Reference Voltages 7.8.4.1 Decoder
8.0.0 Voltage Generators 2 8.1.0 References 8.1.1 Amplifier 8.2.0 Decoder 8.3.0 Data Buffers 8.3.1 Voltage Shifter 1 8.3.2 Voltage Shifter 2 8.3.3 Voltage Shifter 3 8.4.0 Logic 8.5.0 Regulated Charge Pump 1 8.5.1 Control 8.5.2 Reference Voltages 8.5.3 Amplifier 8.6.0 Regulated Charge Pump 2 8.7.0 Amplifier 9.0.0 CIS Column Comparator 9.1.0 Comparator 9.2.0 Column Select 9.3.0 Loading 1 9.4.0 Loading 2 Cell Library 10.0.0 CIS Row Level Shifter About Chipworks
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