High-efficiency of MHz Inverter Constructed from Frequency Multilying Circuit Koji Orikawa, Jun-ichi Itoh Deartment of Electrical Engineering Nagaoka University of Technology Nagaoka, Jaan orikawa@vos.nagaokaut.ac.j Abstract This aer discusses a verification of an inverter oututs MHz frequency which is over the itching frequency. The roosed inverter consists of a multi-hase inverter using silicon itching devices and multi-core transformers. By the frequency multilying, high itching frequency comared with the outut frequency is not required. Moreover, the series resonance using a leakage inductance of the multi-core transformers and a resonant caacitor is alied in order to achieve sinusoidal outut voltage. A rototye circuit is exerimentally verified and theoretically analyzed in terms of zero voltage itching (ZS). As a result, it is confirmed that the rototye circuit can outut sinusoidal outut voltage of.5 MHz with the itching frequency of 5 khz. In addition, a required dead time for zero voltage itching is theoretically analyzed and exerimentally verified using the rototye circuit. I. INTRODUCTI Recently, high-efficiency high-frequency inverters which outut MHz frequency are increasingly received attentions for alications of lasma generators and wireless ower transfer [-3]. For those alications, voltage with MHz band frequency is required. As one of conventional high frequency inverters, ower linear amlifiers using transistors are used. However, the efficiency of the ower linear amlifier is low in rincile. On the other hand, Class E inverters have been studying because they can achieve very high efficiency due to ZS and zeroderivative itching (ZDS) [4, 5]. In addition, wide band ga semiconductors such as silicon carbide (SiC) and gallm nitride (GaN) are used recently. As a result, increasing its efficiency is accelerating even though the outut frequency is several MHz to several tens of MHz because their itching seed is higher than that of conventional Si devices [6]. In addition, in order to obtain higher efficiency by reducing itching losses, ZS or zero current itching (ZCS) is alied. However, the outut frequency is limited by the itching frequency even though the wide band ga semiconductors are used because their erformance is limited. This aer verifies exerimentally the effect of ZS on the roosed circuit based on the frequency multilying method [7] by measuring the inut ower and the outut ower. The roosed circuit oututs a frequency which is over a itching frequency while other circuit cannot achieve high outut frequency which is over the itching frequency. Therefore, not only wide band ga semiconductors are used but also conventional Si devices can be used in the roosed circuit because the itching frequency is lower than the outut frequency. This aer is organized as follows; first, the rincile of the roosed circuit is described. Then, an oeration of the roosed circuit is theoretically analyzed using an equivalent half-bridge circuit in terms of ZS for high efficiency. Finally, a validity of the condition which achieves ZS is exerimentally verified at series resonant condition by measuring the inut ower and the outut ower. II. PROPOSED CIRCUIT BASED FREQUENCY MUTIPYING METHOD Figure shows the circuit configuration of the roosed circuit in a five-hase inverter model. The rimary side of the multi-core transformer [8] is connected in arallel. A common connection oint of the rimary side of the transformer is connected to the neutral oint of DC link caacitors C dc. On the other hand, the secondary side of the multi-core transformer is connected in series. The resonant caacitor which is used for the series resonance with the leakage inductance of the multi-core transformer is connected to the secondary side of the multi-core transformer. Note that the magnetizing inductance is neglected. Figure shows the rincile the roosed frequency multilying method. In the five hase voltage-tye inverter, each of the voltage hases is shifted by 7 degree and oerated with square wave modulation. As a result, the outut frequency f out is exressed as following f N out f
where f is the itching frequency and N is the number of hase in the multi-hase inverter. Therefore, the multi-hase inverter oututs high frequency which is over the itching frequency even though low itching frequency is alied. In addition, cooling is easier because the heat which is generated from the multi-hase inverter can be dissiated for a number of itches. III. C dc C dc o S u S nu u Multi-hase inverter S v S nv PRINCIPE OF ZERO OTAGE SWITCHING This chater describes the rincile of ZS in the roosed circuit for reduction of the itching loss. Fig. 3(a) shows a half bridge equivalent circuit of the roosed circuit. In Fig. 3(a), an uer itch is S. On the other hand, a lower itch is S. A DC link caacitor C dc is assumed to be a voltage source. R is resistance comonents transformed to the rimary side of the multi-core transformer, which includes a wire resistance r and r and a resistance R. is inductance comonents transformed to the rimary side of the multi-core transformer, which includes a leakage inductance l and l. C is an equivalent resonant caacitor. Cr is a resonant caacitor connected to the secondary side of the multi-core transformer. By analyzing the oeration of the roosed circuit, R,, C and C r are exressed by (), (3), (4) and (5) using the turn ratio of the winding in the multi-core transformer n and the resonant frequency f r. R N r () n Rout r N l n (3) l C (4) f r v N C n C N (5) C r S w S nw Fig. 3(b) shows two gate signals of the equivalent circuit with the dead time T d. In this aer, ZS when S is turned on is focused. w S x S nx x S y S ny Outut frequency f out :.5 MHz Switching frequency f : 5 khz Number of hase N: 5 y eakage inductance n=n /N Resonance caacitor l r N N l r C r v uo v vo v wo v xo v yo Figure. Configuration of roosed circuit. Multi-core transformers f out i Nf R v uo v vo v wo v xo v yo / - / / - / / - / / - / / - / / - / 7 deg. T/5 7 deg. 7 deg. 7 deg. Fig. 3(c) and (d) show the gate signals, two corresonding drain-source voltage and the current of a neutral oint of the DC link voltage when hard-itching occurs or ZS is achieved. A. Oeration modes Figure 4 shows oeration modes of the roosed circuit. A condition which achieves ZS is decided by the dead time and circuit arameters. By analyzing Fig. 4, the required dead time T d which achieves ZS is obtained as following. ) Mode I The Mode I is a eriod before the dead time starts. In the Mode I, the itch S is on-state and the itch S is off-state. Note that the current I Sw flows to the S. In this aer, the eriod which the Mode I ends is defined as t=. ) Mode II In the Mode II, the S is turned off and the eriod of the dead time starts. The Mode II is ket until the voltage of arasitic caacitance in S is charged u to the inut voltage or the voltage of the arasitic caacitance in S is discharged to zero. Note that the eriod which the Mode II ends is defined as t=t. Therefore, T d should be longer than T because the arasitic caacitance of drain-source is still charged or discharge until t=t. 3) Mode III First, note that the eriod which the Mode III ends is defined as t=t. The current olarity of the neutral oint of the DC link voltage is changed at t=t. When the dead time T d is shorter than T +T, S is turned on while the drain-source voltage of S is zero. Therefore, ZS is achieved. 4) Mode I If the dead time T d is larger than T +T, the arasitic caacitance of drain-source in S is charged. In this case, S is turned on while the drain-source voltage of S is not zero. Therefore, ZS is not achieved. The required dead time which achieves ZS T d is exressed by (6) using T and T. It is noted that the circuit arameters satisfy (7). T Figure. Princile of frequency multilying.
T Td T (6) T R R (7) T C Sin in C 4 in I I C (8) Hard-itching Zero voltage itching S R C i ds S Dead time T d Dead time T d i o =i -i i S (a) S ds ds Dead time T d ds S i o I T T t T t S Fig. 3(c), (d) Mode I II With resonance caacitor (Without resonance caacitor) T III I T +T I II III T I T +T (b) T <T +T <T d T <T d <T +T (a) Half bridge equivalent circuit. (c) Enlarged waveforms at hard-itching. (b) Gate signals with dead-time. (d) Enlarged waveforms at zero voltage itching. Fig. 3. Princile of zero voltage itching. (c) (d) S i ds S i ds S i ds S i ds S i ds S i ds Hard-itching (Fig. 3(c)) Mode I Mode II,III,I Mode Zero voltage itching (Fig. 3(d)) Mode I Mode II,III Mode I, (a) S :On, S :Off. (b) S :Off, S :Off (During dead time) (c) S :Off, S :On Fig. 4. Oeration modes of the roosed circuit.
T Tan K (9) R () C in c ( T ) R K () I T where T is the eriod which the Mode II ends, T is the eriod of the Mode III. In other words, At T, the current olarity of equivalent is changed. is the natural angular frequency, K is the coefficient, I T is the current of the equivalent at t=t, c(t ) is the voltage of the equivalent resonant caacitor at t=t. I. EXPERIMENTA RESUTS Secifications of a rototye circuit is as following. The number of hase in the multi-hase inverter N is five. In order to obtain the outut frequency f out of.5 MHz, the itching frequency f is 5 khz. The inut voltage is 48. A resistance is 33.3 which is a non-inductive resistance. A. Oeration waveforms Figure 5 shows the exerimental waveforms at ZS condition. The dead time T d = 97. ns which satisfies (6) is used. From Fig. 5(a), it is confirmed that the voltage is almost sinusoidal waveform due to the series resonance. Fig. 5(b) and (c) show two gate signals, the drain-source voltage of S and the rimary current of the multi-core transformer. From the result, there is no rise of v ds during the dead time because the dead time which satisfies (6) is used. Figure 6 shows the exerimental waveforms at hard- v gs (S ) () v gs (S ) v gs (S ) () v gs (S ) (S,S) (S,S) () () v v i (A) (ns) i (A) (ns) i i (a) oad voltage and current. v gs (S ) () v gs (S ) (a) oad voltage and current. v gs (S ) () v gs (S ) (S,S) (S,S) v ds v ds () () vds 5 (A) (ns) vds 5 (A) (ns) (b) drain-source voltage and rimary current of multi-core transformer. (b) drain-source voltage and rimary current of multi-core transformer. (S,S) v gs (S ) v gs (S ) () (S,S) v gs (S ) v gs (S ) () v ds v ds () () vds 5 (A) (ns) vds 5 (A) (ns) (c) Enlarged waveforms of (b) Figure 5. Exerimental waveforms at ZS (T d=97. ns). (c) Enlarged waveforms of (b) Figure 6. Exerimental waveforms at hard-itching (T d=7.6 ns).
itching condition which does not satisfy (6). In Fig. 6, the dead time T d = 7.6 ns. Therefore, hard-itching occurs because v ds is increased during the dead time. From these exeriments, the roosed circuit obtains high efficiency because zero voltage itching is achieved even though the outut frequency is.5 MHz. B. Inut and outut ower measurement Figure 7 shows the measured inut and outut ower of the rototye circuit at low ower when the dead time varies. It is noted that the resistance is constant. The inut and outut ower are the highest at ZS condition because the itching loss is the lowest and dead time is the shortest. On the other hand, at hard-itching condition, the inut ower is decreased with the increasing dead time. In addition, the outut ower is decreased because the itching loss becomes higher. Inut ower Pin (W) Outut ower Pout (W) 5 5 ZS Inut ower P in Fig. 5 Outut ower P out Hard-itching Fig. 6 f : 5 (khz) 5 f out :.5 (MHz) : 48 () 9 3 4 Dead time T d (ns) Figure 7. Inut ower and outut ower.. CCUSI This aer described the high-frequency inverter which oututs MHz frequency based on the multilying frequency method. By the frequency multilying, the roosed circuit oututs high frequency which is over the itching frequency. First, the required dead time which achieves ZS was derived by using the equivalent circuit. Finally, the rototye circuit was exerimentally verified. It was confirmed the rototye circuit can outut.5 MHz with the itching frequency of 5 khz at ZS condition. REFERENCES [] H. Fujita, H. Akagi, S. Shinohara: A -MHz 6-kA oltage-source Inverter Using ow-profile MOSFET Modules for ow-temerature Plasma Generators, Power Electronics, IEEE Transactions on, ol.4, No.6,. 4- (999) [] Y. Sakamoto, K. Wada, T. Shimizu: "A 3.56 MHz Current-oututtye Inverter Utilizing An Immittance Conversion Element", EPE- PEMC 8,. 88-94 (8) [3] S. Suzuki, T. Shimizu: "A Study on Efficiency Imrovement of Highfrequency Current Outut Inverter based on Immittance Conversion Element", IPEC 4,. 66-7 (4) [4] J. A. García, R. Marante, M. de las Nieves Ruiz avín: GaN HEMT Class E Resonant Toologies for UHF DC/DC Power Conversion, Microwave theory and techniques, IEEE Transactions on, ol.6, No.,. 4-49 () [5] J. M. Burkhart, R. Korsunsky, D. J. Perreault: Design Methodology for a ery High Frequency Resonant Boost Converter, Power Electronics, IEEE Transactions on, ol.8, No.4,. 99-937 (3) [6] H. Zhou, W., E. Persson: "Evaluation of GaN, SiC and Suerjunction in MHz C Converter", PCIM5,. 6-65 (5) [7] K. Orikawa, J. Itoh: "Exerimental erification of MHz Inverter Constructed from Frequency Multilying Circuit with Soft-Switching", PCIM5,. 635-64 (5) [8] G. Ortiz, J. Biela, D. Bortis, J. W. Kolar: Megawatt, khz, Isolated, Bidirectional k to.k DC-DC Converter for Renewable Energy Alications, The International Power Electronics Conference,. 3-39 ()