PERFORMANCE COMPARISON OF DIGITAL GATES USING CMOS AND PASS TRANSISTOR LOGIC USING CADENCE VIRTUOSO Paras Gupta 1, Pranjal Ahluwalia 2, Kanishk Sanwal 3, Peyush Pande 4 1,2,3,4 Department of Electronics and Communication Engineering, Graphic Era University, Dehradun, (India) ABSTRACT This paper deals with backend implementation of gates using 0.18µm technology in Cadence Virtuoso 6.14 software and optimization of factors like power dissipation, size and number of transistors involved in digital circuits. So, optimizing these components will ultimately result in optimized utilization of all kinds of resources. This project also throws light on innovative transistor-transistor logic (TTL) structures of various digital components like AND gate, OR gate etc. based on pass transistor logic. These structures utilize fewer transistors and dissipate lesser power in comparison to same devices implemented by conventional CMOS logic. I. INTRODUCTION Pass transistor logic (PTL) have become popular since they offer the possibility to implement high speed and low power circuits in certain applications. A large number of such circuits have been developed with increased performance in terms of speed and power efficiency as well as synthesis methodologies that target pass transistor implementations Generally, the use of pass transistor logic leads to reduced transistor count and smaller node capacitances thus decreasing the required area, rise/fall times and power dissipation. From the implementation point of view, the efficient design of integrated circuits depends strongly on CAD tools that can estimate their performance fast and accurately. Since the transistor count on integrated circuits is increasing, there is an intense need for modeling techniques which can offer sufficient accuracy but are orders of magnitude faster than tools based on numerical methods. II. LOGIC STYLES The logic style used in logic gates basically influences the speed, size, power dissipation, and the wiring complexity of a Circuit. The circuit delay is determined by the number of inversion levels, the number of transistors in series, transistor sizes. Circuit size depends on the number of transistors and their sizes, and also on the wiring complexity. Power dissipation is determined by the switching activity and the node capacitances (made up of gate, diffusion, and wire capacitances), the latter of which in turn is a function of the same parameters that also control circuit size. Finally, the wiring complexity is determined by the number of connections and their lengths. All these characteristic may vary considerably from one logic style to another and thus make the proper choice of logic style crucial for circuit performance. As far as cell-based design techniques (e.g., standard-cells) and logic synthesis are concerned, ease-of-use and generality of logic gates is of importance as well. 38 P a g e
PTL design style has emerged as a promising alternative to conventional CMOS, for low power design. Pass transistor logic device consumes much lesser power in comparison to CMOS logic device implementing same logic. (1)* Here P avg is average power dissipation, α Ti is correspondence node transition node factor, C i is parasitic capacitance associated with each node, V i is node voltage, V DD is power supply voltage and f CLK is clock frequency. From equation, it is clear that the average power dissipation of every device is directly dependent on number of nodes (i.e. transistors) and supply voltage. With reduction in any of them we can achieve reduction in average power dissipation of the devices. Pass transistor logic not only reduces the power dissipation but also reduces overall size of chip, making it more efficient and economical. Here is an example in which AND gate, OR gate etc. are implemented using pass transistor logic and CMOS logic and their results are analyzed. III. EXPERIMENTAL RESULTS In this paper PTL design of AND, OR and NAND is considered. The parameters considered are power dissipation, rise time, fall time and propagation delay. PARAMETER CMOS VALUE PASS VALUE Technology(length) 180nm 180nm Supply Voltage(V DD ) 1.8 Volts 1.8 Volts Width Pmos(4um) Nmos(2um) Pmos(4um) Nmos(2um) Rise time (i/p 10p) 0.8415ns 0.11663ns Fall time (i/p 10p) 0.6080ns 0.0101475ns Propagation delay (i/p 0) 0.61415ns 0.007075ns Power consumption 4.1579513*10^-11 W 9.3531277*10^-16 W No. of transistors 6 2 39 P a g e
Figure.2 OR GATE PARAMETER CMOS VALUE PASS VALUE Technology(length) 180nm 180nm Supply Voltage(V DD ) 1.8 Volts 1.8 Volts Width Pmos(4um) Nmos(2um) Pmos(4um) Nmos(2um) Rise time (i/p 10p) 0.06834ns 0.0116ns Fall time (i/p 10p) 0.082006ns 0.00835ns Propagation delay (i/p 0) 0.0638165ns 0.00971245ns Power consumption 2.7833563*10^-11 W 9.3531277*10^-11 W No. of transistors 6 2 Figure.3 NAND GATE 40 P a g e
PARAMETER CMOS VALUE Technology(length) 180nm PASS VALUE 180nm Supply 1.8 Volts 1.8 Volts Voltage(V DD ) Width Pmos(4um) Nmos(2um) Pmos(4um) Nmos(2um) Rise time (i/p 10p) 0.03475ns 0.006715ns Fall time (i/p 10p) 0.03315ns 0.02809ns Propagation delay 0.02230022ns 0.016052ns (i/p 0) Power consumption 7 1817942*10^- 12 W 2.7257037*10^- 11 W No.of transistors 4 5 The comparative results of various designs are shown in Fig 3, 4 and 5. IV. CONCLUSION Transistors in gates designed by pass transistor logic are less than the number of transistors utilized in CMOS logic design. According to equation (1) with decrease in number of transistors overall power dissipation of the device also decreases. Interconnects are minimized in the circuit, hence minimizing the propagation delay occurring in interconnects. Problem with PTL is the restoration of the output level leading to decrease in noise margin. REFERENCES Journal Papers [1] IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 7, JULY 1997. Books [2] N. Weste, K. Eshranghian, Principles of CMOS VLSI Design: A System Perspective, Reading MA: Addison-Wesley, (1993). [3] Sung-Mo Kang, Y. Leblibici, CMOS Digital Integrated Circuits: Analysis and Design, Addition-Tata McGraw Hill,(2003). [4] Synopsys Inc, Library Compiler User Guide, Volume II, Chapters I III, 1999 41 P a g e
Theses [5] Comparison between nmos Pass Transistor logic style vs. CMOS Complementary Cells, Rakesh Mehrotra, Massoud Pedram Xunwei Wu Dept. of E.E.-Systems Proceedings Papers [6] M. Cheng, M. Irwin, K. Li, and W. Ye, Power Characterization of Functional Units, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, IEEE, Vol.1, pp. 775-779, 1999 [7] M. A. Cirit, Characterizing a VLSI Standard Cell Library, Proceedings of Custom Integrated Circuit Conference, IEEE, pp. 25.7.1-25.7.4, 1991 [8] J.F. Croix and D.F. Wong, A Fast and Accurate Technique to Optimize Characterization Tables for Logic Synthesis, Proceedings of Design Automation Conference, IEEE, pp. 337-340, 1997 [9] Jing-Yang Jou, Jing-Yuan Lin and Wen-Zen Shen, A Power Modeling and Characterization Method for the CMOS Standard Cell Library, Digest of Technical Papers, International Conference on Computer Aided Design, IEEE, pp. 400-404, 1990 [10] Dhimant Patel, CHARMS: Characterization and Modeling System for Accurate Delay Prediction of ASIC Designs, Proceedings of Custom Integrated Circuit Conference, IEEE,pp. 9.5.1-9.5.6, 1990 [11] Arun Pratap Singh Rathod, Brijesh Kumar, S. C. Yadav and Poornima Mittal, Low power VLSI design using pass transistor logic, National Technical Expo. 2014, Jointly by NRDC New Delhi and Graphic Era University Dehradun, at Dehradun, India, April-26-27, 2014. 42 P a g e