Robust n Generic Control of Full-Brige Moulr Multilevel Converter High-Voltge DC Trnsmission Systems Grin Philip Am n Innocent Ewen Dvison Abstrct This pper presents the theoreticl bsis of the control strtegy tht llows the cell cpcitor voltge regultion of the full-brige moulr multilevel converter (FB- MMC) to be controlle inepenent of its c link voltge. The presente control strtegy permits opertion with reuce c link voltge uring permnent pole-to-groun c fult, n controlle ischrge n rechrge of the HVDC links uring shutown n restrt following clernce of temporry pole-topole c fults. Aitionlly, it llows voltge source converter bse HVDC links tht employ FB-MMC to be operte with both positive n negtive c negtive c link voltges. This feture is well suite for hybri HVDC networks, where the voltge source converters re operte longsie the line commutting current source converters, without ny compromise to the power reversl t ny terminls. The usefulness of the presente control strtegy is emonstrte on full-scle moel of HVDC link tht uses FB-MMC with 101 cells per rm, consiering the cses of pole-to-groun n poleto-pole c fults. Inex-Terms DC fult reverse blocking, full n hlf brige moulr multilevel converter, High-voltge c trnsmission systems, n multi-terminl high-voltge c networks. R I. ITRODUCTIO ecently there re severl voltge source converter (VSC) topologies being propose im to improve c fult survivl of point-to-point n multi-terminl HVDC trnsmission systems[1-8]. Hlf-brige moulr multilevel converter (HB-MMC) is wiely opte in recent yers; becuse its istribute cell cpcitors o not contribute ischrge current to c fult when converter switches re blocke [7, 9-18]. As result the mgnitue of trnsient c fult current is gretly reuce compre to tht of conventionl VSC topologies with concentrte input c link cpcitors such s two-level n neutrl-point clmpe converters[3, 4, 6, 9, 19-21]. However, HB-MMC is unble to stop c gri contribution to the c fult current through its freewheeling ioes. This mkes its c fult survivl is incresingly relies on the vilbility of fst cting c circuit brekers s suggeste in [9, 22-25]. Otherwise, HB-MMC freewheeling ioes my fil from excessive current stresses. FB-MMC offers n invluble feture of c fult current limiting, n shres mny other ttributes with HB- MMC; but it hs been wiely ismisse on the groun of high semiconuctor losses [22, 26-31]. G. P. Am is with the Deprtment of Electronic n Electricl Engineering, University of Strthclye, Glsgow, G1 1XW UK (e-mil: grin.m@eee.strth.c.uk). Innocent Ewen Dvison is with Eskom Centre of Excellence in HVDC n Smrt Gri Reserch, within School of Engineering, University of KwZulu-tl, Durbn, South Afric ( Dvison@ukzn.c.z) Mixe cells MMC (50% of the cells re hlf-brige n remining 50% re full-brige) is suggeste s n lterntive to FB-MMC in ttempt to chieve c fult current limiting feture t reuce semiconuctor losses [5, 32]. This pproch is ppere to be ttrctive becuse it combines the ttributes of both HB-MMC n FB-MMC such s moulrity n internl fult mngement. Alterntive rm moulr multilevel converter (AA-MMC) iscusse in [3, 7, 8, 33, 34] offers c fult current limiting feture with similr level of semiconuctor losses s mixe cells MMC, but with smller footprint[5, 35]. However, smooth current commuttion between upper n lower rms of the AA- MMC is seeme to be chllenging, especilly when AA- MMC exchnges lrge rective power with the c gri. Aitionlly, AA-MMC is expecte to hve lrge trnsient c fult current from ischrge of its concentrte input c link cpcitor s c link voltge collpses uring c short circuit fults. References [4, 5] hve shown tht the threelevel n five-level cells MMCs presente in [23, 36-38] offer c fult limiting feture, with similr level of semiconuctor losses n converter footprint s the mixe cells MMC. But they cquire c fult current limiting feture t greter complexity of the control n power circuit compre to mixe cells MMC. This pper explores mnipultion of insertion function c bis to enble reuce c voltge opertion of the HVDC links tht employ FB-MMC uring permnent pole-togroun c fults, n to fcilitte controlle ischrge n rechrge of the c link uring system shutown n restrt following clernce of temporry c fults. Aitionlly, this pper uses generic electromgnetic moel of the FB- MMC to emonstrte the benefits of mnipultion insertion function c bis t system level, consiering the cse of fullscle HVDC link, where ech converter terminl is FB- MMC with 101 cells per rm. It hs been shown tht the justment of the insertion function c bis improves trnsient response of the HVDC link being stuie, incluing its c fult rie through cpbility. II. FULL-BRIDGE MODULAR MULTILEVEL COVERTER (FB- MMC) A) Theoreticl bsis of FB-MMC moultion Figure 1 shows generic three-phse FB-MMC with cells per rm n input c link voltge of V c when it is connecte to c gri through n interfcing trnsformer. Assume the voltge rops in the upper n lower rm rectors re negligible compre to V c, the output phse voltge t output pole reltive to supply mi-point o
cn be expresse s: v () t 1 V v, where v cj 0 2 c cj j1 represents cpcitor voltge of cell j th n is insertion or moultion function. Insertion function for the FB-MMC upper rm is ( t) 1 ( msin( t ), where m is the 2 moultion inex; stns for insertion function c bis; n δ is the phse shift between phse funmentl voltge t converter terminl v o n voltge v t the point of common coupling. Recently, it hs been recognize tht the cell cpcitor voltges of the full-brige MMC cn be regulte inepenent of the c link voltge, shoul bipolr cpbility of ech iniviul FB cell is fully exploite[22]. This llows insertion function of the FB- MMC n its c component to be vrie over extene rnge of -1 1 n -1 1 respectively. When the sum of the cell cpcitor voltges in ech MMC rm is regulte t V cref, the voltge evelope cross upper n lower rms of phse re: v ( ) 1 1 sin( ) 1 t Vc mvcref t Vcref msin( t ) n 1 2 2 2 v 1 1 1 2( t) V sin( ) sin( ) 2 c mv 2 cref t V 2 cref m t, where =V c /V cref. Observe tht when V cref is regulte close or equl to c link voltge (V c ) s it will be uring norml opertion for prcticl resons, 1 s in HB-MMC cse (ll cells re inserte with positive polrity); 0 when V c 0 uring pole-to-pole c short circuit fult (50% of cells re inserte with positive polrity n remining 50% with negtive polrity); n =-1 when polrity of the input c link voltge is reverse (ll cells to be inserte with negtive polrity). When the cell cpcitor voltge regultion is ecouple from the converter input c link voltge s being pursue in this pper, the mximum pek funmentl voltge cn be synthesize uring norml opertion is V 1 1 m1 v0() t V 2 c vcj Vcref V 2 c j1, with =1 or -1 (positive correspons to number of cell cpcitors to be inserte with positive polrity, n the opposite is true). otice tht when the c link voltge collpses to zero uring pole-to-pole c fult, insertion function is limite to - ½ ½; n in this cse, the mximum pek funmentl voltge cn synthesize is ½V cref, which is lmost the sme s in norml opertion shoul V cref is set to be equl to nominl input c operting voltge V c0. This shows when cell cpcitor voltge regultion of the FB-MMC is ecouple from the input c link voltge level, the cell cpcitors of ech rm ct s virtul c link, incluing uring collpse of the ctul c link voltge. This permits c voltge t converter terminl to be synthesize inepenent of input c link voltge. This feture llows FB-MMC to be controllble even when the input c link is lower thn the gri voltge. otice tht the insertion function of ech rm vries within 0 1 n -1 0 uring norml opertion with positive n negtive input c link voltge respectively. The bove iscussions hve shown tht the input c link voltge of the FB-MMC cn be vrie from V c0 to V c0, without loss of converter control, benefiting of the use of the cell cpcitors of ech converter rm s virtul c link. B) Converter control Figure 2 summries control systems of the FB-MMC being use in this pper. Observe tht the loops tht regulte AC power/or c link voltge, rective power/or c voltge n c currents in synchronous reference frme set the insertion function c component, n provie over-current protection uring c network fults. Whilst the loops tht regulte cell cpcitor voltges inepenent of converter c link n common moe currents tht flow in the converter rms set the insertion function c bis, n provie overcurrent protection uring c sie fults. The most inner loop uses mplitue (stircse) moultion to generte the gting signls for switches of the FB-MMC, with Mrqur cpcitor voltge blncing tht rottes the cell cpcitors bse on their voltge mgnitues n polrity of the rm currents. The loops tht regulte cell cpcitor voltges re esigne s follows: A) Common moe current Differentil equtions tht escribe the ynmics of FB- MMC upper n lower rm currents for phse re: i L 1 1 V 2 c v1 R i1 v0 (1) i L 2 1 V 2 c v2 Ri2 v0 (2) Where i 1 n i 2 re phse upper n lower rm currents; v 1 n v 2 re voltges evelope cross converter upper n lower rms cell cpcitors of phse ; n R n L re resistnce n inuctnce of the upper n lower rm rectors. After ing (2) to (1) n recll tht v 1 n v 2 re v 1 Vc m msin( t ) n v 1 Vc m msin( t ), 1 2 2 2 eqution (3) is obtine: i L com 1 1 V 2 c m 2 Vc R icom (3) Where the common moe current i com is: i 1 com 2 ( i1i 2 ) n 1 Vc 2 vcuj vclj j1 j1. To fcilitte control esign, let u com =½V c -½m V c n u com will be obtine from proportionl-integrl (PI) controller s: * * ucom kp( icom icom ) ki ( icom icom ) (4) After replcing the integrl prt of (4) by z com, n further lgebric n Lplce mnipultions, the following trnsfer function is obtine: k p ki icom () s s L L * i () 2 kp R com s ki s s L L. This i n p n trnsfer function llows the initil controller gins to be 2 selecte s k L n k 2 L R for given timeomin specifictions such s settling time or using frequency omin. From the bove efinition of the u com, m is obtine consiering the fee-forwr term of ½V c s: m =2(½V c -u com )/V c.
B) Cell cpcitor voltge The ifferentil equtions tht escribe the cell cpcitor ynmics of the upper n lower rms of phse s n cuj cuj n j1 j1 2 exmple re: 1 Cv i 2 11 v 1 2 Cv 2 clj i2 2 vclj. With proper control, the cell j1 j1 cpcitor voltges of the upper rm vry together with reltively smll errors, n the sme is pplicble to the lower rm. Thus, bove equtions cn be written s: 1 2 v Cv cu 2 cu i 1 1 v cu C i 1 1 (5) 1 2 v Cv cl 2 cl i 2 2 v cl C i 2 2 (6) Recll tht i I 1 i n i I 1 i, i I sin( t ). 1 2 2 2 With insertion functions of the upper n lower rms of phse ( 1 n 2 ) efine s 1 1 2 ( m sin t ) n 1 2 2 ( m sin t ), 1 I mi 4 m cos m ; thus, eqution (7) is obtine by ing (5) n (6): C 1 e Vc1 Vc2 i1 1 i2 2 mi cos(2 ) 4 m t (7) Where V c1 =v cu n V c2 =v cl ; n C e =C/. Observe tht the R.H.S of equtions (5) n (6) o not contin c component, n R.H.S of eqution (7) tht escribes ynmic of the upper n lower rms contins only 2 n hrmonic. These inicte tht the converter cell cpcitor voltge blncing cn be mintine roun the c link voltge, n but the cell cpcitor voltge level is couple to the c link voltge. In orer to ecouple the cell cpcitor voltge level from the c link voltge level, theoreticl eqution (7) is bnone in fvour empiricl eqution in (8): C 1 1 e V 1 2 1 2 2 c Vc i 2 i icom (8) Where C e =C/ is the equivlent cpcitnce per rm, n C is the cpcitnce per cell. Observe tht the R.H.S of eqution (8) is common moe current of the upper n lower rm of phse tht contins c component, which provies the bility to chnge the energy (or voltge) level of the cell cpcitors inepenent of the converter input c link voltge. The reference common moe current * i com is obtine from PI controller tht regultes the cell cpcitor voltges s: * i 1 1 com p Vcref ( V 2 c1 Vc 2) i Vcref ( V 2 c1 Vc 2) (9) The initil gins for the PI controller in (9) re obtine from p 21 n1c e n 2 i n1 C e, with mping n nturl frequency 1 n n1 re ecie bse on time omin specifiction s previously stte. Bse on bove iscussions, the control structure for the cell cpcitor n common moe current regultion epicte in Figure 2 is constructe. The reers re vise to refer to reference [39] for etils of the control esign for the remining controllers epicte in Figure 2. III. PERFORMACE EVALUATIO Figure 3 shows full-scle symmetricl mono-pole HVDC link tht uses FB-MMC, with ech converter terminl VSC 1 n VSC 2 is rte t 1000MVA, ±320kV c link voltge, n connecte to 400kV c network through 1000MVA, 300kV/400kV interfcing trnsformers. Converter terminls VSC 1 n VSC 2 re moelle using FB-MMC electromgnetic trnsient moel escribe in [39], but in this pper, number of FB sub-moules in ech rm is set to 101. Generic control system isplye in Figure 2 is use to control VSC 1 n VSC 2, with no eicte controller for 2 n hrmonic suppression in converter rms is incorporte in ttempt to reuce the overll system complexity. VSC 1 n VSC 2 re configure to regulte ctive power n c voltge level t 640kV (pole-to-pole) respectively, with rective powers t both sttions re set to zero. The prmeters of the HVDC link in Figure 3 re liste in Tble 1. The c fult survivl of the HVDC link in Figure 3 is exmine when the cell cpcitor voltge blncing of the FB-MMCs use in VSC 1 n VSC 2 is ecouple from the c link uring pole-to-groun n pole-to-pole c fults (with n without converter blocking).
PCC 0 Vc c0 vc0 vb0 v0 b0 AC gri Figure 1: Generic three-phse full-brige moulr multilevel converter Figure 2: Generic control systems of the FB-MMC
p +320kV Tble 1: Summry of system prmeters PCC2 1000MVA 400kV/300kV XT=0.2pu VSC2 V c2 p Figure 3: Electromgnetic trnsient bse full-scle moel of FB-MMC HVDC link with 101 cells per rm V c1-320kv VSC1 1000MVA 300kV/400kV XT=0.2pu PCC1 c link voltge (Vc) ±320kV Converter rte c sie voltge 300kV Converter rte power 1052MVA Converter rte ctive power ±1000MW Converter rte rective power ±328MVAr umber of cells per rm 101 Cpcitnce per cell 4mF Arm rectnce 50mH Interfcing trnsformer rte power 1052MVA Interfcing trnsformer voltge rtio 300kV/400kV Interfcing trnsformer per unit 0.2pu lekge rectnce Interfcing trnsformer per unit 0.0002pu resistnce DC cble resistnce 0.01Ω/km DC cble inuctnce 0.8mH/km DC cble cpcitnce 0.25μF/km (A) Pole-to-groun c fult This section exploits some of the silent fetures of the FB- MMC iscusse in section II to enble continue opertion of symmetricl mono-pole HVDC when it is expose to permnent pole-to-groun c fult. For illustrtion, the HVDC link in Figure 3 is initilly set to export 700MW from the point of common coupling (PCC 1 ) to PCC 2. At time t=0.4s, permnent c fult is pplie t the mile of the c cble (positive pole) tht connects VSC 1 to VSC 2, n fterwr VSC 1 is immeitely commne to reuce the trnsmitte power from PCC 2 n PCC 1 to zero, n then restore grully to 400MW fter the trnsients ssocite with the c fults hve ie out. Becuse the surge rresters being use in such HVDC links re not rte for continuous opertion (1.5 to 2 times of the rte voltge for 10ms 20ms in the worse cses), VSC 2 is commne fter 45ms (for illustrtion only) from the fult initition to reuce c link voltge grully to 320kV, with VSC 1 n VSC 2 remin unblocke. Selecte wveforms obtine from this cse re isplye in Figure 4. Figure 4 () n (b), n (c) n () show ctive n rective powers VSC 1 n VSC 2 exchnge with PCC 1 n PCC 2, n their corresponing c sie currents mesure t PCC 1 n PCC 2. Figure 4 (e) n (f) show rm currents of the VSC 1 n VSC 2. Figure 4 (g) n (h) show smples of the c link voltge (pole-to-pole) n current mesure t the terminls of VSC 2. Observe tht successful reuction of the c link voltge is chieve, with the current stresses in VSC 1 n VSC 2 upper n lower rms n in their c sies remin fully controllble. This illustrtive exmple hs emonstrte the possibility of continuous opertion of the FB-MMC HVDC link when one of the its positive or negtive poles is subjecte to permnent pole-to-groun c fult. Figure 4 (i) n (j) show the cell cpcitor voltges of VSC 1 n VSC 2 re ecouple from the c link voltge n well regulte roun (640kV/1016.37kV) s in pre-fult conition. The significnce of this work is tht it resses the min wekness in ll symmetricl mono-pole HVDC links currently in opertion (inbility to operte uring pole-togroun c fult s the surge rresters n c cble insultion of the helthy pole will brekown from excessive voltge stresses, see Figure 4 (k)). () Active n rective power VSC 1 exchnges with PCC 1 (b) Active n rective power VSC 2 exchnges with PCC 2 (c) AC currents VSC 1 injects into PCC 1 () AC currents VSC 2 injects into PCC 2
(e) VSC 1 phse upper n lower rm currents (f) VSC 2 phse upper n lower rm currents (g) VSC 2 c link voltge (h) Smple of the c link current mesure t the terminls of VSC 2(positive pole) (i) VSC 1 phse upper n lower rms cell cpcitor voltges (j) VSC 2 phse upper n lower rms cell cpcitor voltges (k) Positive n negtive pole to groun voltges Figure 4: Wveforms obtine when HVDC link bse on FB-MMC is subjecte to pole-to-groun c fult t the mile of the link (B) Pole-to-pole c fult (i) When VSC 1 n VSC 2 re blocke uring fult This section exploits the c fult reverse blocking n controlle rechrge cpbilities of the FB-MMC to improve c fult survivl of symmetricl mono-pole HVDC link, while keeping the current n voltge stresses on converter sttions switching evices n pssive components within tolerble limits. For illustrtion, the HVDC link in Figure 3 is subjecte to temporry pole-to-pole c fult t the mile of the c line tht connects VSC 1 to VSC 2 t t=0.4s, with 100ms fult urtion. In pre-fult conition, the HVDC link in Figure 3 is set to export 700MW from PCC 1 to PCC 2, n the trnsmitte power is reuce to zero n converter switches re blocke immeitely when the fult is etecte. After fult clernce t t=0.5s, VSC 1 n VSC 2 switches re unlocke, n VSC 2 is commne to perform controlle rechrge of the c link to 640kV before power trnsmission is resume. At t=1.3s, VSC 1 is commne to restore the power exchnge between the two c networks grully to pre-fult vlue. Figure 5 () n (b), (c) n (), n (e) n (f) show ctive n rective powers VSC 1 n VSC 2 exchnge with their corresponing c networks, c current wveforms mesure t PCC 1 n PCC 2, n rm currents of the VSC 1 n VSC 2 respectively. These wveforms hve shown tht the link being stuie is ble to recover from pole-to-pole c fult, with currents t PCC 1 n PCC 2, n switching evices of VSC 1 n VSC 2 re tightly regulte within the levels tht cn be tolerte by the commercilly vilble IGBTs. Figure 5 (g) n (h) show smples of the c link voltge n current mesure t the terminls of VSC 2. Observe tht the HVDC link being stuie briefly lost control ue to the trnsients experience when converter switches re unblocke promptly n the ely time introuce by the response time of iniviul controllers, n shortly fterwr the link is ble to perform controlle rechrge of the link, with the current ssocite with the rechrging of the c line stry cpcitors re tightly controlle, incluing tht in the converter rms. Figure 5 (i) n (j) show the voltge blnce of the cell cpcitors of VSC 1 n VSC 2 re well mintine, incluing uring controlle rechrge of the c link. (ii) When VSC 1 n VSC 2 re not blocke uring c fult This subsection investigtes the possibility of riing temporry pole-to-pole c fult stuie in subsection B-(i) when VSC 1 n VSC 2 re not blocke, n their cell cpcitor voltges re exploite in mnner to be seen by their respective c sies s virtul c links. Exploiting this feture llows the c currents VSC 1 n VSC 2 exchnge with PCC 1 n PCC 2 to be controllble espite the collpse of their physicl c link voltge. Figure 6 isplys selecte wveforms obtine when the simulte cse in B-(i) is repete, with VSC 1 n VSC 2 remin unblocke. Figure 6 () n (b) show with the control system in Figure 2, the HVDC link being stuie is ble to rie-through soli poleto-pole c fult, with c currents ssocite with the ischrge n rechrge of the c line stry cpcitors re
tightly controlle. But the plots for the upper n lower rm currents of VSC 1 n VSC 2 in Figure 6 (c) n () hve shown tht the current stresses in the converter rms, which will be seen by the semiconuctor switches, re ominte by the trnsient ischrge currents of the c line stry cpcitors. Figure 6 (e) n (f) show when VSC 1 n VSC 2 re not blocke, their cell cpcitor voltges exhibit lrge isturbnces s result of lrge unipolr c fult currents tht flow through the sub-moule cpcitors. Although the simulte cse (B)-(ii) hs shown tht the semiconuctor switches re less likely to survive such excessive current stresses when converters re not blocke, riing c fult without converter blocking my be possible in reltively short overhe HVDC links, where the line istribute cpcitnces re negligible. Figure 6 (g) n (h) show smple of the c link current n c link voltge mesure t VSC 2 terminls. () Active n rective power VSC 1 exchnges with PCC 1 (b) Active n rective power VSC 2 exchnges with PCC 2 (c) AC current wveforms VSC 1 exchnges with PCC 1 () AC current wveforms VSC 2 exchnges with PCC 2 (e) VSC 1 phse upper n lower rm currents (f) VSC 2 phse upper n lower rm currents (g) Smple of the c link voltge mesure t the terminls of VSC 2 (h) Smple of the c link current mesure t the terminl of VSC 2 (positive pole) (i) Phse upper n lower rms cell cpcitor voltges of the VSC 1 (j) Phse upper n lower rms cell cpcitor voltges of the VSC 2 Figure 5: Wveforms obtine when HVDC link bse on FB-MMC is subjecte to pole-to-pole c fult t the mile of the link () Current wveforms VSC 1 injects into PCC 1 (b) Current wveforms VSC 2 injects into PCC 2
(c) VSC 1 phse upper n lower rm currents () VSC 2 phse upper n lower rm currents (e) VSC 1 cell cpcitor voltges (phse ) (f) VSC 2 cell cpcitor voltges (phse ) (g) Smple of the c link current mesure t the terminl of VSC 2 (positive pole) (h) Smple of the pole-to-pole c link voltge mesure t the terminls of VSC 2 Figure 6: Wveforms obtine when HVDC link bse on FB-MMC is subjecte to pole-to-pole c fult t the mile of the link, with VSC1 n VSC2 remin unblocke uring fult IV. COCLUSIOS This pper presente comprehensive iscussions of the unerlying theory, which is lter exploite to control FB- MMC when use in symmetricl mono-pole HVDC link in ttempt to improve its c fult survivl. It hs been shown tht when the regultion of the cell cpcitor voltges is ecouple from the converter c link voltge, converter sttions of the HVDC remin controllble even though when its physicl c link voltge is collpse to zero. Moreover, it hs been shown tht the number of sub-moules to be inserte in power pth with positive n negtive polrities is irectly link to the c bis mgnitue of the insertion function of ech phse, n this feture is exploite to enble opertion of FB-MMC HVDC link with vrible c voltge. The theoreticl iscussions presente in section II hve been substntite using simultion of full-scle HVDC link tht uses FB-MMC with 101 sub-moules per rm, consiering the cses of pole-to-groun n pole-topole c fults. The presente results hve shown tht the FB-MMC offers number of invluble fetures tht re well suite for point-to-point n multi-terminl HVDC trnsmission systems. V. REFERECES [1] F. Deng n Z. Chen, "A Control Metho for Voltge Blncing in Moulr Multilevel Converters," Power Electronics, IEEE Trnsctions on, vol. 29, pp. 66-76, 2014. [2] S. Debnth n M. Seeifr, "A ew Hybri Moulr Multilevel Converter for Gri Connection of Lrge Win Turbines," Sustinble Energy, IEEE Trnsctions on, vol. PP, pp. 1-14, 2013. [3] G. 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