LOAD SHARE CONTROLLER

LOAD SHARE CONTROLLER FEATURES 2.7-V to 20-V Operation 8-Pin Package Requires Minimum Number of External Components Compatible with Existing Power Supply Designs Incorporating Remote Output Voltage Sensin Differential Share Bus Precision Current Sense Amplifier (40 Gain) UVLO (Undervoltage Lockout) Circuitry User Programmable Share Loop Compensation APPLICATIONS Paralelled Power Supplies DESCRIPTION The load share controller is an 8-pin device that balances the current drawn from independent, paralleled power supplies. Load sharing is accomplished by adjusting each supplies output current to a level proportional to the voltage on a share bus. The master power supply, which is automatically designated as the supply that regulates to the highest voltage, drives the share bus with a voltage proportional to its output current. The trims the output voltage of the other paralleled supplies so that they each support their share of the load current. Typically, each supply is designed for the same current level although that is not necessary for use with the. By appropriately scaling the current sense resistor, supplies with different output current capability can be paralleled with each supply providing the same percentage of their output current capability for a particular load. GND 1 8 VCC BIAS UVLO 40R SHARE DRIVE AMPLIFIER SENSE 2 R CURRENT SENSE AMPLIFIER SHARE SENSE AMPLIFIER 7 SHARE 6 SHARE ADJ 3 ADJ AMPLIFIER 0.6 V 35 mv ERROR AMPLIFIER 5 COMP 2.3 V ADJR 4 UDG 01141 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002 2008, Texas Instruments Incorporated 1

DESCRIPTION (continued) A differential line is used for the share bus to maximize noise immunity and accommodate different voltage drops in each power converter s ground return line. Trimming of each converter s output voltage is accomplished by injecting a small current into the output voltage sense line, which requires a small resistance (typically 20 Ω to 100 Ω) to be inserted. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UC2902 VCC, ADJ 0.3 to 20 SENSE 5 to 5 Input voltage range, V I ADJR, COMP 0.3 to 4 UNIT V SHARE, SHARE 0.3 to 10 SHARE 100 ma to 10 ma ma Output current, I O ADJ 1 ma to 30 ma ma Operating free-air temperature range, T A 40 to 100 Junction temperature range, T J 55 to 105 Storage temperature, T stg 65 to 150 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltages are with respect to GND. Currents are positive into, and negative out of the specified terminal. C 2

ELECTRICAL CHARACTERISTICS T J = 40 C to 105 C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power SUPPLY SUPPLY CURRENT I CC Supply current SHARE = 1 V, SENSE = 0 V 4 6 V CC = 20 V 6 10 ma UNDERVOLTAGE LOCKOUT V CC Startup voltage SHARE = 0.2 V, SENSE = 0 V, COMP = 1 V 2.3 2.5 2.7 V Hysteresis SHARE = 0.2 V, SENSE = 0 V, COMP = 1 V 60 100 140 mv CURRENT SENSE AMPLIFIER V IO Input offset voltage 0.1 V V (SHARE) 1.1 V 2.5 0.5 1.5 mv SENSE to SHARE gain 0.1 V V (SHARE) 1.1 V 41 40 39 V R IN Input resistance 0.6 1 1.5 V SHARE DRIVE AMPLIFIER V OH High-level output voltage, SHARE V CC = 2.5 V V CC = 12 V V CC = 20 V V CC = 2.5 V V (SENSE) = 50 mv V (SENSE) = 250 mv V (SENSE) = 250 mv V (SENSE) = 10 mv V OL Low-level output voltage, SHARE V CC = 12 V V (SENSE) = 10 mv V O CMRR Output voltage, SHARE Common mode rejection ratio Load regulation V CC = 20 V V (SENSE) = 10 mv V (SENSE) = 0 mv, R (SHARE) = 200 Ω (SHARE to GND) 0 V V (SHARE ) 1 V, SENSE used as input to amplifier Load on SHARE, 1 ma I LOAD 20 ma V (SENSE) = 25 mv 1.2 1.4 9.6 10.0 10.4 V 9.6 10.0 10.4 20 50 20 50 20 50 20 40 mv 50 90 db 0 20 mv I SC Short circuit current V (SHARE) = 0 V, V (SENSE) = 25 mv 85 50 20 ma Slew rate V (SENSE) = 10 mv to 90 mv step R (SHARE) = 200 Ω (SHARE to GND) V (SENSE) = 90 mv to 10 mv step R (SHARE) = 200 Ω (SHARE to GND) 0.12 0.26 0.38 0.12 0.26 0.38 V/μs 3

ELECTRICAL CHARACTERISTICS (continued) T J = 40 C to 105 C, (unless otherwise noted) PARAMETER SHARE SENSE AMPLIFIER R IN Input impedance V (SHARE) = 1 V, V (SENSE) = 10 mv TEST CONDITIONS V (SHARE ) = GND R (SHARE) = 200 Ω (SHARE to GND) V (SHARE ) = 1 V, V (SENSE) = 10 mv MIN TYP 8 15 8 15 V (SHARE) Threshold voltage V (SENSE) = 0 V 41 70 100 mv CMRR Common mode rejection ratio 0 V V (SHARE ) 1 V, V (SENSE) = 2.5 mv 50 60 AVOL DESCRIPTION from SHARE to ADJR Slew rate ERROR AMPLIFIER g M I OH I OL Transconductance, SHARE to COMP High-level output current Low-level output current V (SENSE) = 2.5 mv, 5 nf capacitor from COMP to GND, 1 kω resistor from ADJR to GND V (SENSE) = 2.5 mv, 5 nf capacitor from COMP to GND, 150 Ω resistor from ADJR to GND V (SHARE) = 0 mv to 10 V step through a 200-Ω resistor, R (COMP) = 500 Ω, V (SENSE) = 10 mv, V CC = 10 V 50 68 50 66 MAX UNIT kω db 0.2 0.5 0.8 V/μs 200-Ω resistor SHARE to GND 3.0 4.5 6.0 ms V (COMP) = 1.5 V, SHARE 300 mv V (SENSE) = 10 mv 200-Ω resistor SHARE to GND, V (COMP) = 1.5 V, V (SENSE) = 10 mv 450 325 200 80 150 250 V IO Input offset voltage 15 35 65 mv ΔV IO / ΔV (SENSE) ADJ AMPLIFIER ADJR low voltage 1-kΩ resistor ADJR to GND 2.5 mv V (SENSE) 25 mv 200-Ω resistor SHARE to GND, V (SENSE) = 10 mv μaa 6 0 6 mv/v 1 0 1 mv ADJR high voltage V (SENSE) = 10 mv, V (SHARE) = 1 V 1.4 1.8 2.1 V Current gain ADJR to ADJ I (ADJR) = 0.5 ma, V (ADJ) = 2.5 V, V (SENSE) = 10 mv, V (SHARE) = 1 V I (ADJR) = 0.5 ma, V (ADJ) = 20 V, V (SENSE) = 10 mv, V (SHARE) = 1 V I (ADJR) = 10 ma, V (ADJ) = 2.5 V, V (SENSE) = 10 mv, V (SHARE) = 1 V I (ADJR) = 10 ma, V (ADJ) = 20 V, V (SENSE) = 10 mv, V (SHARE) = 1 V 0.96 0.99 1.02 0.96 0.99 1.02 0.96 0.99 1.02 0.96 0.99 1.02 A/A 4

ORDERING INFORMATION T A PACKAGE (2) PART NUMBER SOIC (D) UC2902D 40 C to 85 C Plastic DIP (N) UC2902N SOIC (D) D 0 C to 70 C Plastic DIP (N) N (2) The D package is also available taped and reeled. Add an R suffix to the device type (i.e., bq24901dr) for quantities of 3,000 devices per reel. D PACKAGE (TOP VIEW) N PACKAGE (TOP VIEW) GND SENSE ADJ ADJR 1 2 3 4 8 7 6 5 VCC SHARE SHARE COMP GND SENSE ADJ ADJR 1 2 3 4 8 7 6 5 VCC SHARE SHARE COMP TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION ADJ 3 I Current output of the adjust amplifier circuit (NPN collector) ADJR 4 O Current adjust amplifier range set (NPN emitter) COMP 5 I/O Output of the error amplifier, input of the adjust amplifier GND 1 Local power supply return and signal ground SENSE 2 I Inverting input of the current sense amplifier SHARE 7 I/O Positive input from share bus or drive-to-share bus SHARE 6 I Reference for SHARE pin VCC 8 I Local power supply (positive) 5

Step 1. Step 2. Step 3. Step 4. APPLICATION INFORMATION The values of five passive components must be determined to configure the load share controller. The output and return lines of each converter are connected together at the load, with current sense resistor R SENSE inserted in each negative return line. Another resistor, R ADJ, is also inserted in each positive remote sense line. The differential share bus terminals (SHARE and SHARE ) of each are connected together respectively, and the SHARE node is also connected to the system ground. A typical application is illustrated in Figure 1. The load share controller design can be executed by following the next few steps: R SENSE V SHARE(max) A CSA I O(max) where A CSA is 40, the gain of the current sense amplifier At full load, the voltage drop across the R SENSE resistor is I O(max) R SENSE. Taking into account the gain of the current sense amplifier, the voltage at full load on the current share bus, V SHARE(max) A CSA I O(max) R SENSE This voltage must stay 1.5-V below V CC or below 10 V whichever is smaller. V SHARE represents an upper limit but the designer should select the full scale share bus voltage keeping in mind that every volt on the load share bus increases the master controller s supply current by approximately 100 μa times the number of slave units connected parallel. R G V ADJ(max) I ADJ(max) Care must be taken to ensure that I ADJ(max) is low enough so that both the drive current and power dissipation are within the device s capability. For most applications, an I ADJ(max) current between 5 ma and 10 ma is acceptable. In a typical application, a 360-Ω R G resistor from the ADJR pin to ground sets I ADJ(max) to approximately 5 ma. V O(max) I O(max) R SENSE R ADJ I ADJ(max) R ADJ must be low enough to not affect the normal operation of the converter s voltage feedback loop. Typical R ADJ values are between 20 Ω to100 Ω depending on V O, ΔV O(max) and the selected I ADJ(max) value. (1) (2) (3) (4) C C g M R ADJ 2 f C R G R SENSE R LOAD A CSA A PWR fc (5) 6

Step 5. The share loop compensation capacitor, C C is calculated to produce the desired share loop unity gain crossover frequency, f C. The share loop error amplifier s transconductance, g M is nominally 4.5 ms. The values of the resistors are already known. Typically, f C is set to at least one order of magnitude below the converter s closed loop bandwidth. The load share circuit is primarily intended to compensate for each converter s initial output voltage tolerance and temperature drift, not for differences in their transient response. The term A PWR(fc) is the gain of the power supply measured at the desired share loop crossover frequency, f C. This gain can be measured by injecting the measurement signal between the positive output and the positive sense terminal of the power supply. R C 1 2 f C C C A resistor in series with C C is required to boost the phase margin of the load share loop. The zero is placed at the load share loop crossover frequency, f C. When the system is powered up, the converter with the highest output voltage tends to source the most current and take control of the share bus. The other converters increase their output voltages until their output currents are proportional to the share bus voltage minus 50 mv. The converter which in functioning as the master may change due to warmup drift and differences in load and line transient response of each converter. ADDITIONAL INFORMATION Please refer to the following topic for additional application information. 1. Application Note U 163, (TI Literature No. SLUA128) The Load Share Controller and Its Performance in Distributed Power Systems by Laszlo Balogh (6) 7

PACKAGE MATERIALS INFORMATION 28-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter Reel Width W1 A0 B0 K0 P1 W Pin1 Quadrant UC2902DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION 28-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length Width Height UC2902DTR SOIC D 8 2500 340.5 338.1 20.6 DTR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2

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