CIRCUIT DIAGRAM Half Wave Rectifier. Half Wave Rectifier with filter 2012/ODD/III/ECE/EC I/LM 1

CIRCUIT DIAGRAM Half Wave Rectifier Half Wave Rectifier with filter 2012/ODD/III/ECE/EC I/LM 1

Ex.No. 1 Date: / /2012 Power supply circuit using Half Wave rectifiers AIM To Build and understand the operation of an AC to DC power supply using half wave rectifier. APPARATUS REQUIRED S.NO Equipment /Component Type/Range Quantity 1 CRO 30 MHz 1 2 Transformer 12-0-12 1 3 Signal Generator (0-30 MHz 1 4 Diode 1N4007 2 5 Resistors Each 1 6 capacitors Each 1 7 Zener diode 1 8 Bread Board - 1 THEORY The objective of the lab is to reacquaint you with the fundamentals of AC (alternating current) and DC (direct current) voltages as well as introduce you to the basics of AC to DC conversion through the use of diode rectifiers. In Figure 1, RL simulates the load placed on the power supply, which can be a battery operated electronic device, a computer (though it would need a DC-DC step down converter),or any other circuit that requires a DC input. The first section of the power supply, after the AC voltage source, is the transformer. It is responsible for converting the AC signal from a standard wall outlet down to a 12 VAC signal. Most DC power supplies maintain a voltage much less than 120 volts, so the transformer stage is necessary to get the AC source amplitude down to a more reasonable level.. Rectifier is capable of converting a sinusoidal input waveform, whose average value is zero into unidirectional waveform, with a nonzero average component. A diode is usually used as the rectifying device. Half wave rectifier is one converts the ac to dc in one half of the cycles only. Although the rectification stage makes the sine wave voltage to be positive, the rectifier s result is not as flat a DC value as we would like to have from a reliable voltage source, as you will measure in lab. The capacitor is included to help smooth out the ripples that result in the output from the rectification stage. 2012/ODD/III/ECE/EC I/LM 2

Half Wave Rectifier output Half Wave Rectifier with filter Power supply circuit using half wave rectifier with filter 2012/ODD/III/ECE/EC I/LM 3

PROCEDURE 1. Simulate the circuit using MultiSIM and Test the circuit functions 2. Connect the half wave rectifier as shown in figure 3. Measure ac and dc voltage and current at the output 4. Calculate ripple factor 5. Form the filter circuit by connecting capacitor in parallel to resistance and measure the same 6. Form the regulator circuit as shown in fig. 7. Measure the output voltage by vary the input voltage and kept he load constant and vice versa 8. Plot line and load regulation graph 9. Measure V FL and V NL and calculate the regulation 10. Observe the circuit output and compare with simulation output REFERENCES 1. Electronic Devices and Circuits Millman, halkias, Satyabratajit, Tata McGraw Hill. ( page nos 177-187 ) 2. Electronic Devices and Circuits David A. Bell, PHI ( page nos 52-64 ) 3. Electronic Devices and Circuit Theory Robert L. Boylested, Loius Nashesky. PHI ( page nos 76-83 ) QUESTIONS FOR DISCUSSION 1. Why are rectifiers used with a filter at their output? 2. Define voltage regulation of a rectifier? 3. What is the ideal value of regulation? 4. What does no-load condition refer to? 5. What are the advantages of a bridge rectifier? 6. what is meant by ripple? 7. What are the applications of rectifiers? 8. What is PIV? State it is value in case of (i) Half wave (ii) Full wave (iii) Bridge rectifier. 2012/ODD/III/ECE/EC I/LM 4

OBSERVATIONS S.No Line Regulation Load Regulation Input Voltage (Vi) Volts Output Voltage (Vo) Volts Input Voltage (Vi) Volts Output Voltage (Vo) Volts Load regulation Line Regulation 2012/ODD/III/ECE/EC I/LM 5

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Work space Ripple factor formulae for Rectifier % r = (Vr (rms)/vdc) * 100 Regulation % Regulation = (V NL - V FL )/ V FL VNL = Voltage across load resistance, When minimum current flows though it VFL = Voltage across load resistance, When maximum current flows through it. 2012/ODD/III/ECE/EC I/LM 7

RESULT Simulation (10) Circuit connection (20) Result (10) Viva Voce (10) Total (50) Staff Signature with Date 2012/ODD/III/ECE/EC I/LM 8

CIRCUIT DIAGRAM Full Wave Rectifier G T A B 169.706 Vpk 60 Hz 0 vi T1 0 1:2 DIODE_VIRTUAL D1 1kΩ R DIODE_VIRTUAL D2 Full Wave Rectifier with filter 2012/ODD/III/ECE/EC I/LM 9

Ex.No.2 Date: / /2012 Power supply circuit using Full Wave rectifier AIM To Build and understand the operation of an AC to DC power supply using half wave rectifier. APPARATUS REQUIRED S.NO Equipment /Component Type/Range Quantity 1 CRO 30 MHz 1 2 Transformer 12-0-12 1 3 Signal Generator (0-30 MHz 1 4 Diode 1N4007 2 5 Resistors Each 1 6 capacitors Each 1 7 Bread Board - 1 8. Zener diode 1 THEORY The objective of the lab is to reacquaint you with the fundamentals of AC (alternating current) and DC (direct current) voltages as well as introduce you to the basics of AC to DC conversion through the use of diode rectifiers. In Figure 1, RL simulates the load placed on the power supply, which can be a battery operated electronic device, a computer (though it would need a DC-DC step down converter), or any other circuit that requires a DC input. The first section of the power supply, after the AC voltage source, is the transformer. It is responsible for converting the AC signal from a standard wall outlet down to a 12 VAC signal. Most DC power supplies maintain a voltage much less than 120 volts, so the transformer stage is necessary to get the AC source amplitude down to a more reasonable level. 2012/ODD/III/ECE/EC I/LM 10

Power supply circuit using Full wave rectifier with filter OBSERVATIONS S.No Line Regulation Load Regulation Input Voltage (Vi) Volts Output Voltage (Vo) Volts Input Voltage (Vi) Volts Output Voltage (Vo) Volts 2012/ODD/III/ECE/EC I/LM 11

The second stage, consisting of the two diodes D1 to D2, is referred to as a full wave rectifier. The diodes only allow current to flow in one direction (the direction of the arrow on their symbol. D1 work to allow only positive AC voltages to pass through the rectifier unaffected. On the other hand, D2 flip the sign of the negative AC voltages to make the whole output of the rectifier to be positive as shown in Figure 1. This converts the AC voltage (a sine wave) to an always-positive DC voltage (a flat signal).although the rectification stage makes the sine wave voltage to be positive, the rectifier s result is not as flat a DC value as we would like to have from a reliable voltage source, as you will measure in lab. The capacitor is included to help smooth out the ripples that result in the output from the rectification stage. Recall that the voltage across a capacitor cannot change instantaneously, but rather it requires a certain amount of time before it is fully charged. Large capacitance values help suppress the quickly changing voltage from the rectifier and result in a flatter DC value being supplied to the load. PROCEDURE 1. Design the circuit by following the design procedure 2. Simulate the circuit using MultiSIM and Test the circuit functions 3. Connect the circuit as per the circuit diagram given 4. Observe the circuit output and compare with simulation output 5. Measure Vr(p-p),Vdc, Vp from output waveform. 6. compare the results with calculated value 7. Plot the load regulation characteristics using zener diode REFERENCES 1. Electronic Devices and Circuits Millman, halkias, Satyabratajit, Tata McGraw Hill. ( page nos 177-187 ) 2. Electronic Devices and Circuits David A. Bell, PHI ( page nos 52-64 ) 3. Electronic Devices and Circuit Theory Robert L. Boylested, Loius Nashesky. PHI ( page nos 76-83 ) 2012/ODD/III/ECE/EC I/LM 12

MODEL GRAPH Full Wave Rectifier output Full Wave Rectifier with filter 2012/ODD/III/ECE/EC I/LM 13

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WORK SPACE Ripple factor formulae for Rectifier % r = (Vr (rms)/vdc) * 100 Regulation % Regulation = (V NL - V FL )/ V FL VNL = Voltage across load resistance, When minimum current flows though it VFL = Voltage across load resistance, When maximum current flows through it. 2012/ODD/III/ECE/EC I/LM 15

Questions 1. What is the PIV for full wave rectifier? 2. What function did the Zener diode perform? 3. What happens to ripple as you increase the value of capacitance from 100μF to 1000μF? 4. How zener diodes act as voltage regulator? RESULT Simulation (10) Circuit connection (20) Result (10) Viva Voce (10) Total (50) Staff Signature with Date 2012/ODD/III/ECE/EC I/LM 16

CIRCUIT DIAGRAM Fixed bias circuit Voltage Divider Bias 22 V 10kΩ 39kΩ + - 0.874m A + - 2N3904 11.949 V 3.9kΩ 1.5kΩ 50uF PIN CONFIGURATION 2012/ODD/III/ECE/EC I/LM 17

Ex.No. 3 Date: / /2012 BJT BIASING AIM To design, simulate and study the BJT voltage divider bias circuit. APPARATUS REQUIRED S.NO Equipment /Component Type/Range Quantity 1 Power Supply (0-30 ) V 1 2 Ammeter (0-1) A 1 3 Voltmeter (0-10 ) V 1 4 Transistor 2N 3904 1 5 Resistor Each 1 6 Capacitor 1 7. Bread Board - 1 THEORY The design of a transistor amplifier requires knowledge of both the dc and the ac response of the system. Biasing means the application of dc voltages to establish a fixed level of current and voltage. For transistor amplifiers the bias voltage and the resulting dc current establish an operating point on the characteristics that define the region that will be employed for amplification of the Input Voltage. Voltage divider bias is the most stable bias circuit. Voltage divider bias circuits are normally designed to have the voltage divider current very much larger than the transistor base current. In this circumstance, base voltage is largely unaffected by base current, so base voltage can be assumed to remain constant. 2012/ODD/III/ECE/EC I/LM 18

DESIGN PROCEDURE Fixed bias circuit Given Data: VCC=12V, hfe=100, IC = 5mA, VCE = 5V 1. IB = IC / hfe = (5x10-3 )/100 = 5x10-5 A = 50uA 2. RB = (VCC-VBE)/IB = (12-0.7) V/50uA R B = 226kΩ 3. RC = (VCC VCE) / IC = (12-5) V / 5mA R C = 1.4kΩ Voltage Divider Bias Circuit 1.R 2.V 3.V 6.V E E C B 2 1 V I V E E IC R E V V E 4.V R V C V R 5.R C C I E IC 7.I2 10 8.R V B I2 9.R V C cc CC 2 V CE BE V I V B C OBSERVATIONS S.No Analysis V CE (V) I C (ma) 1 Circuit Simulation 2 Circuit Implementation 2012/ODD/III/ECE/EC I/LM 19

PROCEDURE 1. Design the circuit as per the design procedure 2. Simulate the circuit using MultiSIM 3. Perform DC analysis 4. Connect the circuit as per the circuit diagram given 5. Observe the circuit output and compare with simulation output 6. Tabulate the output values REFERENCES 1. Electronic Devices and Circuits Millman, halkias, Satyabratajit, Tata McGraw Hill. ( page nos 284-299) 2. Electronic Devices and Circuits David A. Bell, PHI..( page nos 130-136 ) 3. Electronic Circuits Donald l. Schilling Charles Belove Tata McGraw Hill ( page nos185-197 ) 4. Electronic Devices and Circuit Theory Robert L. Boylested, Loius Nashesky. PHI ( page nos 161-235 ) QUESTIONS FOR DISCUSSION 1. How do you test the diode & transistor-using multimeter? 2. What are the techniques used to make the collector current and collector emitter voltage of a transistor to be constant? 3. List out the types of biasing circuits. 2012/ODD/III/ECE/EC I/LM 20

OBSERVATIONS S.No Frequency Input Voltage Output Gain(Av) = Gain (db) = (Vi) Volts Voltage (Vo) (Vo/Vi) 20log(Vo/Vi) Volts MODEL GRAPH 2012/ODD/III/ECE/EC I/LM 21

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WORKSAPCE 2012/ODD/III/ECE/EC I/LM 23

RESULT Simulation (10) Circuit connection (20) Result (10) Viva Voce (10) Total (50) Staff Signature with Date 2012/ODD/III/ECE/EC I/LM 24

CIRCUIT DIAGRAM Common Emitter Amplifier with bypass capacitor Common Emitter Amplifier without bypass capacitor 2012/ODD/III/ECE/EC I/LM 25

Ex.No. 4 Date: / /2012 AIM COMMON EMITTER AMPLFIER To design and construct BJT Common Emitter Amplifier using voltage divider bias (self-bias) with and without bypassed emitter resistor. 1. Measurement of gain. 2. Plot the frequency response & Determination of Gain Bandwidth Product. APPARATUS REQUIRED S.NO Equipment /Component Type/Range Quantity 1 CRO 30 MHz 1 2 Power Supply 10 V 1 3 Signal Generator (0-3) MHz 1 4 Transistor BC107 1 5 Resistor Each 1 6 Capacitor 3 7 Bread Board - 1 THEORY The common emitter configuration is widely used as a basic amplifier as it has both voltage and current amplification. Resistors R1 & R2 form a voltage divider across the base of the transistor. The function of this network is to provide necessary bias condition and, ensure that emitter - base junction is operating in the proper region. In order to operate transistor as an amplifier, the biasing is done in such a way that the operating point should be in the active region. For an amplifier the Q- point is placed so that the load line is bisected. Therefore, in practical design the VCE is always set to VCC/2. This will conform that the Q-point always swings within the active region. This limitation can be explained by maximum signal handling capacity. Output is produced without any clipping or distortion for the maximum input signal. If not so, reduce the input signal magnitude. The Bypass Capacitor The emitter resistor RE is required to obtain the DC quiescent stability. However the inclusion of RE in the circuit causes a decrease in amplification at higher frequencies. In order to avoid such a condition, it is bypassed by capacitor so that it acts as a short circuit for AC and contributes stability for DC quiescent condition. Hence capacitor is connected in parallel with emitter resistance. 2012/ODD/III/ECE/EC I/LM 26

Design Procedure Given Data VCC = 12V, IC = IE = 5mA, hfe = 100, Av = 50, fl = 100Hz, RL = 10kΩ, RS=500Ω 1. VCE = VCC / 2 = 6V 2. VE = VCC / 10 = 1.2V 3. VRC = VCC - VCE - VE = 4.8V 4. RC = VRC / IC = 4.8 / 5mA = 960Ω use 1kΩ 5. RE = VE / IE = 1.2 / 5mA = 240 Ω use 300Ω 6. R2 = 10RE = 3kΩ 7. R1 = (VCC VB) / I2, VB = VE+VBE = 1.9V I2 = IC / 10 = 0.5mA R1 = (12-1.9)/0.5mA = 20.2kΩ 8. fl = 1/ (2π(Rs+Ri) C1), C1 = 1/(2π(Rs+Ri)fL Ri = R1 R2 hie ; hie = βre ; re = 25mV/IE = 5Ω; hie = 500 1/Ri = (1/ R1)+(1/ R2)+(1/ hie) R i = 419Ω use 500 Ω ; C 1 = 1.73uF use 1.5uF 9. fl = 1/ (2π(RL+R0) C2), C2 = 1/(2π(RL+R0)fL ; R0 = RC C 2 = 0.14uF use 0.1Uf 10. fl = 1/2πRCE ; R = RE ((RB+hie)/hfe) ; RB = RS R1 R2 R = 9.67Ω CE = 1/(2π x 9.67 x 100) = 1.64x10-4 C E = 164uF use 100uF 2012/ODD/III/ECE/EC I/LM 27

Procedure to measure Input and output resistance: Input resistance =Input voltage (voltage across R2 resistor)/input current( I i ) Input Current = Voltage across Rs resistor/rs Output resistance To obtain output resistance, measure the voltage across the output terminals without connecting any load. Keep the input voltage constant connect a Decade Resistance Box (DRB) across output terminals. Change the resistance until you get half of the open circuit voltage. The resistance of load will give the output resistance The Coupling Capacitor An amplifier amplifies the given AC signal. In order to have noiseless transmission of signal (without DC), it is necessary to block DC i.e the direct current should not enter the amplifier or load. This is usually accomplished by inserting a coupling capacitor between any two stages. Frequency Response: Emitter bypass capacitors are used to short circuit the emitter resistor and thus increase the gain at high frequency. The coupling and bypass capacitors cause the fall of in the low frequency response of the amplifier because their impedance becomes large at low frequencies. The stray capacitors are effectively open circuits. In the mid frequency range the large capacitors are effective short circuits and the stray capacitors are open circuits, so that no capacitance appears in the mid frequency range. Hence, the mid band gain is maximum. At the high frequencies, the bypass and coupling capacitors are replaced by short circuits and stray capacitors and the transistor determine the response. Characteristics of CE amplifier: 1. Large current gain 2. Large voltage gain 3. Large power gain 4. Current and voltage phase shift of 1800 5 Moderated output Resistance. PROCEDURE 1. Design the circuit as per the design procedure 2. Simulate the circuit using MultiSIM and Test the circuit functions 3. Set Source Voltage Vs = 50mV (say) at 1 KHz frequency, using function generator. 4. keeping the input voltage constant vary the frequency from 50Hz to 1MHz in Regular steps and note down the corresponding output voltage. 5. Plot the Graph: gain (db) Vs frequency. 6. Calculate the bandwidth from Graph. 7. Calculate all the parameters at mid band frequencies (i.e. at 1 KHz). 8. Calculate Voltage Gain and current gain: 9. Calculate input & output Resistances 10. Calculate gain bandwidth 11. Follow the same procedure for common emitter amplifier without bypass capacitor 2012/ODD/III/ECE/EC I/LM 28

OBSERVATIONS S.No Frequency Input Voltage Output Gain(Av) = Gain (db) = (Hz) (Vi) Volts Voltage (Vo) (Vo/Vi) 20log(Vo/Vi) Volts MODEL GRAPH 2012/ODD/III/ECE/EC I/LM 29

REFERENCES 1 Electronic Devices and Circuits David A. Bell, PHI. ( page nos 105,107,228,232,187 ) 2. Electronic Circuits Donald l. Schilling Charles Belove Tata McGraw Hill ( page nos271-281,453-466 ) 3. Electronic Devices and Circuit Theory Robert L. Boylested, Loius Nashesky. PHI( page nos 530-583 QUESTIONS FOR DISCUSSION 1. For amplification, CE configuration is preferred, why? 2. To operate a transistor as amplifier, the emitter junction is forward biased and the collector junction is reversed biased, why? 3. Most of the transistor are npn type and not pnp, why? 4. How do we test the transistor for active region condition? 5. What are the factors, which influence the higher cut-off frequency? 6. What are the components, which influence the lower cut-off frequency? 7. Mention the applications of CE amplifier. Justify? 8. Compare the characteristics of CE amplifier, CB amplifier & CC amplifier. 9. What must be the voltage across the transistor, when it is operated as a switch? 10. How do we test the transistor for switching condition? 11. What is the specific feature of CE configuration relating to voltage and current gain compared to the other configurations CB &CC? 2012/ODD/III/ECE/EC I/LM 30

OBSERVATIONS Common Emittter amplifier without bypass capacitor S.No Frequency Input Voltage Output Gain(Av) = Gain (db) = (Hz) (Vi) Volts Voltage (Vo) (Vo/Vi) 20log(Vo/Vi) Volts 2012/ODD/III/ECE/EC I/LM 31

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WORK SPACE 2012/ODD/III/ECE/EC I/LM 33

RESULT Simulation (10) Circuit connection (20) Result (10) Viva Voce (10) Total (50) Staff Signature with Date 2012/ODD/III/ECE/EC I/LM 34

CIRCUIT DIAGRAM Common collector amplifier MODEL GRAPH 2012/ODD/III/ECE/EC I/LM 35

Ex.No. 5 Date: / /2012 AIM COMMON COLLECTOR AMPLFIER To design and construct BJT Common Collector Amplifier using voltage divider bias (self-bias). 1. Measurement of gain. 2. Plot the frequency response & Determination of Gain Bandwidth Product. APPARATUS REQUIRED S.NO Equipment /Component Type/Range Quantity 1 CRO 30 MHz 1 2 Power Supply 2V, 20 V Each 1 3 Signal Generator (0-3) MHz 1 4 Transistor BC107 1 5 Resistor As per Design Each 1 6 Capacitor 2 7 Bread Board - 1 THEORY In common collector amplifier as the collector resistance is made to zero, the collector is at ac ground that is why the circuit is also called as grounded - collector amplifier or this configuration is having voltage gain close to unity and hence a change in base voltage appears as an equal change across the load at the emitter, hence the name emitter follower. In other words the emitter follows the input signal. This circuit performs the function of impedance transformation over a wide range of frequencies with voltage gain close to unity. In addition to that, the emitter follower increases the output level of the signal. Since the output voltage across the emitter load can never exceed the input voltage to base, as the emitter-base junction would become back biased. Common collector state has a low output resistance, the circuit suitable to serve as buffer or isolating amplifier or couple to a load with large current demands. Characteristics of CC amplifier: 1. Higher current gain 2. Voltage gain of approximately unity 3. Power gain approximately equal to current gain 4. No current or voltage phase shift 5. High input resistance and Low output resistance 2012/ODD/III/ECE/EC I/LM 36

Design Procedure Given Data: VCC = 12V, IE = 5mA, hfe = 100, Av =1, RS = 500Ω, fl = 100Hz, RL = 10kΩ 1. V E = V CC/2 = 6V 2. V E = V B-V BE ; V B = 6.7V 3. R E = V E/I E = 6V/5mA = 1.2kΩ 4. Rinbase = βre = 120kΩ ; Rthbase<< Rinbase ; Rthbase = 12kΩ R thbase = R 1 R 2 ;If R 1 = R 2, R thbase = R 1/2 R 1 = R 2 = 24kΩ 5. C1 = 1/(2πR fl) ; R = Rthbase Rinbase = 10.9kΩ C 1= 1.46x10-7 = 0.14uF use 0.1uF 6. CE = 1/(2π(R E+R L)f L) = 1.42x10-7 = 0.14uF use 0.1uF 2012/ODD/III/ECE/EC I/LM 37

PROCEDURE 1. Design the circuit as per the design procedure 2. Simulate the circuit using MultiSIM and Test the circuit functions 3. Set Source Voltage Vs = 50mV (say) at 1 KHz frequency, using function generator. 4. keeping the input voltage constant vary the frequency from 50Hz to 1MHz in regular steps and note down the corresponding output voltage. 5. Plot the Graph: gain (db) Vs frequency. 6. Calculate the bandwidth from Graph. 7. Calculate all the parameters at mid band frequencies (i.e. at 1 KHz). 8. Calculate Voltage Gain and current gain: 9. Calculate input & output Resistances 10. Calculate gain bandwidth REFERENCES 1. Electronic Devices and Circuits Millman, halkias, Satyabratajit, Tata McGraw Hill. ( page no 414 ) 2. Electronic Devices and Circuits David A. Bell, PHI. ( page nos 339,314,345 ) 3. Electronic Circuits Donald l. Schilling Charles Belove Tata McGraw Hill ( page nos 304-306,468-470) 4. Electronic Devices and Circuit Theory Robert L. Boylested, Loius Nashesky. PHI ( page nos 530-583 ) QUESTIONS FOR DISCUSSION 1. Why CC amplifier is known as emitter follower? 2. Mention the applications of CC amplifier. Justify? 3. What is the phase difference between input and output signals in the case of CC amplifier? 4. Mention the characteristics of CC amplifier? 5. What is gain bandwidth product?2. What is the voltage gain of this circuit? 6. It is act as a buffer, why? 2012/ODD/III/ECE/EC I/LM 38

OBSERVATIONS S.No Frequency Input Voltage Output Gain(Av) = Gain (db) = (Hz) (Vi) Volts Voltage (Vo) (Vo/Vi) 20log(Vo/Vi) Volts 2012/ODD/III/ECE/EC I/LM 39

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WORK SPACE 2012/ODD/III/ECE/EC I/LM 41

RESULT Simulation (10) Circuit connection (20) Result (10) Viva Voce (10) Total (50) Staff Signature with Date 2012/ODD/III/ECE/EC I/LM 42

CIRCUIT DIAGRAM Source Follower with Bootstrapped Gate Resistance Source Follower without Bootstrapped Gate Resistance 2012/ODD/III/ECE/EC I/LM 43

Ex.No.6 Date: / /2012 SOURCE FOLLOWER (COMMON DRAIN AMPLIFIER) WITH BOOTSTRAPPED GATE RESISTANCE AIM To construct and simulate the Source follower or Common drain amplifier with and without bootstrapped gate resistance and find the gain bandwidth, frequency response, input impedance and output impedance. APPARATUS REQUIRED S.NO Equipment /Component Type/Range Quantity 1 CRO 30 MHz 1 2 Power Supply 20 V 1 3 Signal Generator (0-3) MHz 1 4 FET 2N3337 2 5 Resistors 15k,4.7k,2.2k, 1k, 10 k Each 1 6 Capacitors 10 µf, 20µf Each 2 7 Bread Board - 1 THEORY A voltage amplifier should exhibit a very high input resistance in order to avoid signal attenuation between the circuit input resistance and the source resistance of the input generator. A major problem when designing a circuit for high input resistance is the shunting effect of the base bias resistors, RB (=R1 R2 for a potentiometer biased circuit). If this effect is isolated, a truly high circuit input resistance would result. The technique used is called bootstrapping and involves adding an extra resistor to the bias circuit and magnifying its effective ac value by a capacitive coupling which aims to produce identical signal voltages at both ends of the resistor. Then, ideally, no signal current is taken by the bias circuit and the input resistance is defined by the input resistance to the transistor. 2012/ODD/III/ECE/EC I/LM 44

OBSERVATIONS S.No Frequency Input Voltage Output Gain(Av) = Gain (db) = (Hz) (Vi) Volts Voltage (Vo) (Vo/Vi) 20log(Vo/Vi) Volts MODEL GRAPH 2012/ODD/III/ECE/EC I/LM 45

PROCEDURE 1. Construct the circuit as per the circuit diagram 2. Simulate the circuit using MultiSIM and Test the circuit functions 3. Set Source Voltage Vs = 50mV (say) at 1 KHz frequency, using function generator. 4. keeping the input voltage constant vary the frequency from 50Hz to 1MHz in Regular steps and note down the corresponding output voltage. 5. Plot the Graph: gain (db) Vs frequency. 6. Calculate the bandwidth from Graph. 7. Calculate all the parameters at mid band frequencies (i.e. at 1 KHz). 8. Calculate Voltage Gain and current gain 9. Calculate input & output Resistances 10. Calculate gain bandwidth REFERENCES 1. Transistor circuit techniques G.J.Ritchie. ( page no 82 ) 2. Electronic Devices and Circuit Theory Robert L. Boylested, Loius Nashesky. PHI ( page nos 297-299,537-540 ) QUESTIONS FOR DISCUSSION 1. Why common drain amplifier is called source follower? 2. How FET will differ from BJT? 3. What is the advantage of bootstrapped gate resistace?explain in brief. 4. Write down the application of FET 5. What is meant by MOSFET? 6. Why thermal runaway does not occur in FET? 7. State whether FET is voltage controlled or current controlled device,explain why? 8. Why current gain is the important parameter in BJT? 9. Why do we plot input and output characteristics? What information can we Obtain? 10. Source follower is used as a buffer amplifier, why? 11. How are the capacitance values assumed at low frequency analysis? 12. What is the other name of input resistance of FET? 2012/ODD/III/ECE/EC I/LM 46

Work space 2012/ODD/III/ECE/EC I/LM 47

RESULT Simulation (10) Circuit connection (20) Result (10) Viva Voce (10) Total (50) Staff Signature with Date 2012/ODD/III/ECE/EC I/LM 48

CIRCUIT DIAGRAM Darlington Amplifier MODEL GRAPH 2012/ODD/III/ECE/EC I/LM 49

Ex.No.7 Date: / /2012 AIM DARLINGTON AMPLIFIER USING BJT To construct and simulate Darlington Amplifier. 1. Measurement of gain and input resistance. 2. Comparison with calculated values. 3. Plot the frequency response & Determination of Gain Bandwidth APPARATUS REQUIRED S.NO Equipment /Component Type/Range Quantity 1 CRO 30 MHz 1 2 Power Supply 18 V 1 3 Signal Generator (0-3) MHz 1 4 Transistors 2N3904 2 5 Resistors Each 1 6 capacitors Each 1 7 Bread Board - 1 THEORY In some applications, the need arises for an amplifier with high input impedance. The Darlington pair achieves larger input impedances. Two transistors form a composite pair, the input impedance of the second transistor constituting the emitter load for the first. The circuit consists of two cascaded emitter followers with infinite emitter resistance in the first stage. PROCEDURE 1. Construct the circuit as per the circuit diagram 2. Simulate the circuit using MultiSIM and Test the circuit functions 3. Set Source Voltage Vs = 50mV (say) at 1 KHz frequency, using function generator. 4. keeping the input voltage constant vary the frequency from 50Hz to 1MHz in Regular steps and note down the corresponding output voltage. 5. Plot the Graph: gain (db) Vs frequency. 6. Calculate the bandwidth from Graph. 7. Calculate all the parameters at mid band frequencies (i.e. at 1 KHz). 8. Calculate Voltage Gain, current gain, input and output resistances 2012/ODD/III/ECE/EC I/LM 50

OBSERVATIONS S.No Frequency Input Voltage Output Gain(Av) = Gain (db) = (Hz) (Vi) Volts Voltage (Vo) (Vo/Vi) 20log(Vo/Vi) Volts 2012/ODD/III/ECE/EC I/LM 51

REFERENCES 1. Electronic Devices and Circuits Millman, halkias, Satyabratajit, Tata McGraw Hill. ( page no 365 ) 2. Electronic Devices and Circuits David A. Bell, PHI. ( page nos 570,626 ) 3. Electronic Circuits Donald l. Schilling Charles Belove Tata McGraw Hill ( page no 352-358 ) 4. Electronic Devices and Circuit Theory Robert L. Boylested, Loius Nashesky. PHI ( page no 299-304,341 ) QUESTIONS FOR DISCUSSION 1. What do you mean by Darlington pair? 2. Give the main feature of the Darlington pair. 2012/ODD/III/ECE/EC I/LM 52

WORK SPACE 2012/ODD/III/ECE/EC I/LM 53

RESULT Simulation (10) Circuit connection (20) Result (10) Viva Voce (10) Total (50) Staff Signature with Date 2012/ODD/III/ECE/EC I/LM 54

CIRCUIT DIAGRAM Class A Power Amplifier OBSERVATIONS S.No Input Supply Output Input dc Output Efficiency voltage current voltage power(p dc ) ac power In % (I dc ) (V o ) (P ac ) 2012/ODD/III/ECE/EC I/LM 55

Ex.No. 8 Date: / /2012 AIM CLASS A POWER AMPLIFIER To construct and simulate the Class A power amplifier and find the frequency response. APPARATUS REQUIRED S.NO Equipment /Component Type/Range Quantity 1 CRO 30 MHz 1 2 Power Supply 24 V 1 3 Signal Generator (0-3) MHz 1 4 Transistors 2N3904 1 5 Resistors 100, 300,1k, 5k Each 1 6 Capacitors 10 uf, 100 uf Each 1 7 Bread Board - 1 THEORY Power amplifiers provide sufficient power to an output load to drive power devices, typically a few watts to tens off watts. The main feature of power amplifier is the circuit s efficiency, the maximum amount of power that the circuit is capable of handling, the impedance matching to the output device. In a Class A power amplifier, the output signal varies for a full 360 0 of the cycle. This circuit requires the Q point to be biased at a level such that at least half the signal swing of the output may vary up and down, the extreme values not being limited by the supply voltage levels, high as well as low. PROCEDURE 1. Simulate the circuit using MultiSIM and Test the circuit functions 2. Construct the Class A power amplifier shown in Figure 1. Vcc = 10V,R1 = 2.2KΩ, C1 = 1µF,and R L = 100Ω. Use 10KΩ potentiometer for R 2. 3. Apply a sinusoidal wave with frequency 1KHz and 2V peak to peak to the use channel 1 of the oscilloscope to display input signal and channel 2 to display the output. 4. Adjust the input signal to a value so that the output voltage has maximum symmetrical swing without clipping. 5. Observe the circuit output and compare with simulation output 6. Determine the maximum power and efficiency 2012/ODD/III/ECE/EC I/LM 56

WORK SPACE Formulae DC input power P i (dc) = V cc * I cq = V cc 2 /2R L =AC output power in rms P o (ac) = I C (rms)* V CE (rms) = V 2 CE (rms)/r C = I 2 C (rms)* R C AC output power in Peak value P o (ac) = {I C (p)* V CE (p)}/2 AC output power in peak to peak value P o (ac) = {I C (p-p)* V CE (p-p)}/8 Efficiency: %efficiency = P o (ac)/ P i (dc) 2012/ODD/III/ECE/EC I/LM 57

REFERENCES 1. Electronic Devices and Circuits Millman, halkias, Satyabratajit, Tata McGraw Hill. ( page nos 462,563 ) 2. Electronic Devices and Circuits David A. Bell, PHI. ( page nos606 ) 3. Electronic Devices and Circuit Theory Robert L. Boylested, Loius Nashesky. PHI ( page nos 667 ) QUESTIONS FOR DISCUSSION 1. Give the classification of amplifiers. 2. What is distortion 3. Why is the frequency response very important for amplifiers? 4. What is mean by faithful amplification? 5. Define Efficiency of an amplifier 2012/ODD/III/ECE/EC I/LM 58

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RESULT Simulation (10) Circuit connection (20) Result (10) Viva Voce (10) Total (50) Staff Signature with Date 2012/ODD/III/ECE/EC I/LM 60

Circuit Diagram Complementary- symmetry power amplifier G T A B Q0 BJT_NPN_VIRTUAL V0 15 V V2 1.9997 Vpk 1kHz 0 Q1 R0 10Ω Rl BJT_PNP_VIRTUAL V1 15 V Modification Of Complementary- Symmetry Power Amplifier 2012/ODD/III/ECE/EC I/LM 61

Ex.No. 9 Date: / /2012 CLASS B COMPLEMENTARY SYMMETRY POWER AMPLIFIER AIM To design and simulate the Complementary Class B power amplifier and find the frequency response. APPARATUS REQUIRED S.NO Equipment /Component Type/Range Quantity 1 CRO 30 MHz 1 2 Power Supply 15 V 2 3 Signal Generator (0-3) MHz 1 4 Transistors SL100, SK100 Each 1 5 Resistors 10 1 6 Diode 2 6 Bread Board - 1 THEORY Power amplifiers provide sufficient power to an output load to drive power devices, typically a few watts to tens off watts. The main feature of power amplifier is the circuit s efficiency, the maximum amount of power that the circuit is capable of handling and the impedance matching to the output device. Class B circuit provides an output signal varying over one half the input signal cycle, or for 180 0 of signal. The dc bias point for class B is therefore at 0 V, with the output varying from this bias point for a half cycle. The output is not a faithful reproduction of the input if only one half-cycle is present. Using complementary transistors (NPN and PNP), it is possible to obtain a full cycle output across a load using half-cycles of operation from each transistor. A single input signal is applied to the base of both transistors; the transistors, being of opposite type, will conduct complementary half cycles of the input. The NPN transistor will be biased into conduction by the positive half cycle of signal, with a resulting half cycle of output across the load. 2012/ODD/III/ECE/EC I/LM 62

OBSERVATIONS S.No Input Supply Output Input dc Output Efficiency voltage current voltage power(p dc ) ac power In % (I dc ) (V o ) (P ac ) MODEL GRAPH 2012/ODD/III/ECE/EC I/LM 63

During the negative half cycle of signal, the pnp transistor is biased into conduction by the input, resulting in the other half cycle of output. PROCEDURE 1. Design the circuit by following the design procedure. 2. Simulate the circuit using MultiSIM and Test the circuit functions 3. Connect the circuit as per the circuit diagram given. 4. Observe the circuit output with cross over distortion. 5. Modify the circuit to avoid cross over distortion. 6. Determine the maximum power and efficiency and compare with simulated output. REFERENCES 1. Electronic Devices and Circuits David A. Bell, PHI. ( page nos 620 ) 2. Electronic Devices and Circuit Theory Robert L. Boylested, Loius Nashesky. PHI ( page nos 679 ) QUESTIONS FOR DISCUSSION 1. What do you mean by complementary Symmetry stages? 2. Give the advantage of complementary symmetry class B amplifier. 3. Define cross over distortion. 4. How cross over distortion can be eliminated. 2012/ODD/III/ECE/EC I/LM 64

Formulae DC input power WORK SPACE P i (dc) = V cc * I cq = V cc [(2/ )(Ic(p))] = V cc [(2/ )(Vcc/2R L )] AC output power in rms P o (ac) = I C (rms)* V CE (rms) = V 2 CE (rms)/r C = I 2 C (rms)* R C AC output power in Peak value P o (ac) = {I C (p)* V CE (p)}/2 AC output power in peak to peak value P o (ac) = {I C (p-p)* V CE (p-p)}/8 2012/ODD/III/ECE/EC I/LM 65

RESULT Simulation (10) Circuit connection (20) Result (10) Viva Voce (10) Total (50) Staff Signature with Date 2012/ODD/III/ECE/EC I/LM 66

Circuit Diagram: R E = 10M, R1 = R2 = 5,1k, Vcc = -Vee =9V 2012/ODD/III/ECE/EC I/LM 67

Ex.No.10 Date: / /2012 DIFFERENTIAL AMPLIFIER AIM: To construct and study the performance of Differential Amplifier using BJT and calculate the Common mode gain, differential gain and CMRR and also plot the frequency response and characteristic curve. APPARATUS REQUIRED: S.NO Equipment /Component Type/Range Quantity 1 CRO 30 MHz 1 2 Power Supply 2V, 20 V Each 1 3 Signal Generator (0-3) MHz 1 4 Transistor BC107 1 5 Resistor 5.1KΩ, 10MΩ Each 2 6 Bread Board 1 THEORY: The operational amplifier has had a dramatic impact on electronic circuit design, both analog and digital, over the last 25 years. While the complexity, speed and capability of the Op-Amp have changed dramatically over this time, the basic operation still depends heavily on the input differential amplifier stage. It is this differential amplifier stage that will be examined in this project. The differential amplifier is designed to effectively shift a constant current between two branches as a function of the difference between the two input signals. Ideally, as a result of the changing current, the amplifier output reflects only the difference between the inputs. The quality for the amplifier design is determined, in part, by examining the output of the differential amplifier under two specific input conditions. The ratio of the differential mode voltage gain [ADM] (inputs are equal in magnitude and opposite in sign) to the common mode voltage gain [ACM] (both inputs are equal) is used to determine the Common Mode Rejection Ratio (CMRR). 2012/ODD/III/ECE/EC I/LM 68

OBSERVATIONS 1. Differential mode gain S.No Frequency in Input Voltage Hz (Vi) Volts Output Voltage (Vo) Volts Gain (db) = 20log(Vo/Vi) 2. Common mode gain S.No Frequency in Input Voltage Output Voltage Gain (db) = Hz (Vi) Volts (Vo) Volts 20log(Vo/Vi) 2012/ODD/III/ECE/EC I/LM 69

DIFFERENTIAL GAIN (A D ): The A D is the gain with which differential amplifier amplifies the difference between two input signals. Hence it is called differential gain of the differential amplifier. A D = V o /Vin Diff COMMON MODE GAIN (A C ): Apply the two input voltages which are equal in all the respects to the inputs differential amplifier i.e V 1 = V 2 then ideally the output voltage V O = (V1 V 2 ) A d, must be zero but practically it will not be zero due to mismatches present in the amplifier. A C = V o /Vin common COMMON MODE REJECTION RATIO (CMRR): When the same voltage is applied to both the inputs, the differential amplifier is said to be operated in a common mode configuration. Many disturbance signals, noise signals appear as a common input signal to both the input terminals of the differential amplifier. Such common mode signal should be rejected by the differential amplifier. The ability of a differential amplifier to reject a common mode signal is expressed by a ratio called Common Mode Rejection Ratio denoted as CMRR. CMRR = A D /A C 2012/ODD/III/ECE/EC I/LM 70

WORK SPACE 2012/ODD/III/ECE/EC I/LM 71

Procedure: 1. Simulate the circuit using MultiSIM and Test the circuit functions 2. Connect the circuit as per the circuit diagram given. 3. Apply a 30 mv amplitude, 1 khz sine wave to vin1 and ground vin2. Use the oscilloscope to 4. Display the input waveform at vin1 and the output waveform at vout1 and sketch the result. 5. Use the oscilloscope to measure the peak-to-peak voltages of vin1 and vout1. 6. Use the oscilloscope to display vout1 and vout2. 7. Use the oscilloscope to display vout1 vout2 Measure the peak-to-peak voltage of the signal and calculate the differential gain of the circuit 8. Apply a 30 mv amplitude, 1 khz sine wave to both vin+ and vin. Use the oscilloscope to display the output waveform at vout+ and vout. 9. Apply a differential voltage signal (VX) to each input. The individual input voltages should be equal in magnitude but opposite in polarity. Measure the output voltage and determine the differential mode voltage gain (ADM). Measure the input current for terminal and determine the effective input impedance as seen by the total differential input voltage (2VX). 10. Apply a common mode signal (equal magnitude and same polarity) to the two inputs. Measure the output voltage and determine the common mode voltage gain (ACM). Determine the input impedance for this input condition.compare with the calculated value. 11. Determine the CMRR (A D /A C ) for the amplifier. References 1. Electronic Devices and Circuits David A. Bell, PHI 2. Electronic Devices and Circuit Theory Robert L. Boylested, Loius Nashesky. PHI QUESTIONS 1. What is meant by differential amplifier? 2. What is it advantage over single ended CE amplifier? 3. Define CMRR. What is the significance of it? 4. Give any one application of differential amplifier. 2012/ODD/III/ECE/EC I/LM 72

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RESULT Simulation (10) Circuit connection (20) Result (10) Viva Voce (10) Total (50) Staff Signature with Date 2012/ODD/III/ECE/EC I/LM 74