Logic and Computer Design Fundamentals Chapter 3 Combinational Logic Design Part 2 Combinational Logic
Overview Part -Implementation Technology and Logic Design Design Concepts Fundamental concepts of design Design Procedure The major design steps: specification, formulation, optimization, technology mapping, and verification Technology Mapping From AND, OR, and NOT to other gate types Verification Does the designed circuit meet the specifications? Chapter 3-p2 IT32 2
Overview Part 2 Combinational Logic Functions and functional blocks Rudimentary logic functions Decoding Encoding Selecting Chapter 3-p2 IT32 3
Functions and Functional Blocks The functions considered are those found to be very useful in design. Corresponding to each of the functions is a combinational circuit implementation called a functional block. In the past, many functional blocks were implemented as SSI, MSI, and LSI circuits. Today, they are often simply parts within a VLSI circuits. Chapter 3-p2 IT32 4
Rudimentary Logic Functions Value fixing, transferring, inverting and enabling are the most elementary of combinational logic functions. Can be used on the inputs to functional blocks to implement other than the block s intended function Chapter 3-p2 IT32 5
Value fixing, transferring, and inverting functions Functions of a single variable X X F = F = X F = X F = V CC V DD F = F = X (c) F = X F = F = X F = X (a) (b) (d) Chapter 3-p2 IT32 6
Enabling Function Enabling permits an input signal to pass through to an output Disabling blocks an input signal from passing through to an output, replacing it with a fixed value The value on the output when it is disable can be, or Hi-Z (as for three-state buffers). a) When disabled, output b) When disabled, output X EN (a) F EN X F Chapter 3-p2 IT32 7 (b)
Decoders Convert binary information from n input lines to (max. of) 2 n output lines. Known as n-to-m-line decoder, or simply n:m or nxm decoder (m <= 2 n ). A n-to- 2 n decoder uses its n-bit input to determine which of 2 n outputs will be uniquely activated. Generate 2 n (or fewer) minterms of n input variables. Chapter 3-p2 IT32 8
Decoders Example: if codes,,, are used to identify four light bulbs, we may use a 2-bit decoder: 2-bit code X Y 2x4 Dec F F F 2 F 3 Bulb Bulb Bulb 2 Bulb 3 This is a 2x4 decoder which selects an output line based on the 2-bit code supplied. Truth table: X Y F F F 2 F 3 Chapter 3-p2 IT32 9
Decoders From truth table, circuit for 2x4 decoder is: X Y F F F 2 F 3 Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY) F = X'Y' F = X'Y F 2 = XY' F 3 = XY X Y Chapter 3-p2 IT32
Decoder Examples -to-2-line Decoder Chapter 3-p2 IT32
Decoder Examples 2-to-4-Line Decoder Note that the 2-4-line made up of 2 -to-2- line decoders and 4 AND gates. Chapter 3-p2 IT32 2
Decoders Design a 3x8 decoder. x y z F F F 2 F 3 F 4 F 5 F 6 F 7 F = x'y'z' F = x'y'z F 2 = x'yz' F 3 = x'yz F 4 = xy'z' F 5 = xy'z F 6 = xyz' F 7 = xyz x y z Chapter 3-p2 IT32 3
Decoders In general, for an n-bit code, a decoder could select up to 2 n lines: n-bit code n to 2 n : decoder : up to 2 n output lines Chapter 3-p2 IT32 4
Decoder with Enable In general, attach m-enabling circuits to the outputs See truth table below for function Note use of X s to denote both and Combination containing two X s represent four binary combinations Alternatively, can be viewed as distributing value of signal EN to EN of 4 outputs In this case, called a demultiplexer A A D EN A A D D D 2 D 3 D X X D 2 D 3 (a) (b) Chapter 3-p2 IT32 5
Decoder with Enable Design a 3x8 decoder. E x y z F F F 2 F 3 F 4 F 5 F 6 F 7 x x x F = x'y'z' F = x'y'z F 2 = x'yz' F 3 = x'yz F 4 = xy'z' F 5 = xy'z Enabel (E) F 6 = xyz' F 7 = xyz x y z Chapter 3-p2 IT32 6
Decoder Expansion Another way to design a decoder is to break it into smaller pieces. Notice some patterns in the table below: When S2 =, outputs Q-Q3are generated as in a 2-to-4 decoder. When S2 =, outputs Q4-Q7are generated as in a 2-to-4 decoder. Chapter 3-p2 IT32 7
Decoder Expansion Here s a 3-to-8 decoder built from two smaller 2-to-4 decoders. When S2=, the bottom 2-to-4 decoder is enabled and generates a for one of outputs Q, Q, Q2or Q3. When S2=, the top 2-to-4 decoder is enabled instead, and a will be output for either Q4, Q5, Q6or Q7. Chapter 3-p2 IT32 8
Decoder Expansion Activity Chapter 3-p2 IT32 9
Encoding Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with n m 2 n such that each valid code word produces a unique output code Circuits that perform encoding are called encoders An encoder has 2 n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values Typically, an encoder converts a code containing exactly one bit that is to a binary code corresponding to the position in which the appears. Chapter 3-p2 IT32 2
Octal-to-Binary Encoder A = D + D3 + D5 + D7 A= D2 + D3 + D6 + D7 A2= D4 + D5 + D6 + D7 Chapter 3-p2 IT32 2
Octal-to-Binary Encoder Chapter 3-p2 IT32 22
Selecting Selecting of data or information is a critical function in digital systems and computers Circuits that perform selecting have: A set of information inputs from which the selection is made A single output A set of control lines for making the selection Logic circuits that perform selecting are called multiplexers Selecting can also be done by three-state logic Chapter 3-p2 IT32 23
Multiplexers A multiplexer selects information from an input line and directs the information to an output line A typical multiplexer has n control inputs (S n -, S ) called selection inputs, 2 n information inputs (I 2 n -, I ), and one output Y A multiplexer can be designed to have m information inputs with m < 2 n as well as n selection inputs Chapter 3-p2 IT32 24
2-to--Line Multiplexer Since 2 = 2, n = The single selection variable S has two values: S = selects input I S = selects input I Truth Table The equation: Y = S I + SI Chapter 3-p2 IT32 25
2-to--Line Multiplexer The equation: Y = SI + SI The circuit: Decoder Enabling Circuits Note the regions of the multiplexer circuit shown: S -to-2-line Decoder 2 Enabling circuits 2-input OR gate I I Y Chapter 3-p2 IT32 26
2-to--Line Multiplexer (continued) To obtain a basis for multiplexer expansion, we combine the Enabling circuits and OR gate into a 2 2 AND- OR circuit: -to-2-line decoder 2 2 AND-OR In general, for an 2 n -to--line multiplexer: n-to-2 n -line decoder 2 n 2 AND-OR Chapter 3-p2 IT32 27
Example: 4-to--line Multiplexer 2-to-2 2 -line decoder 2 2 2 AND-OR Condensed Truth Table Chapter 3-p2 IT32 28
Multiplexer Width Expansion Some IC packages have a few multiplexers in each package. The selection and enable inputs are common to all multiplexers within the package. Select vectors of bits instead of bits Chapter 3-p2 IT32 29
Multiplexer Width Expansion A A A2 A3 Y Y Y2 Y3 S (select) E (enable) B B B2 B3 E S Output Y X all s select A select B Quadruple 2: multiplexer Chapter 3-p2 IT32 3
Three-State Implementation Chapter 3-p2 IT32 3
Larger Multiplexers Larger multiplexers can be constructed from smaller ones. An 8-to- multiplexer can be constructed from smaller multiplexers like this (note placement of selector lines): I I I2 I3 I4 I5 I6 I7 4: MUX S S 4: MUX 2: MUX S2 Y S 2 S S Y I I I 2 I 3 I 4 I 5 I 6 I 7 S S Chapter 3-p2 IT32 32
Summary Decoder: For each possible input condition, one and only one output signal will be at logic n-to-2 n decoder is simply a minterm generator, with output corresponding to exactly one minterm. Encoders: Assign a unique output code (a binary number) for each input signal applied to the device Opposite of the decoder Chapter 3-p2 IT32 33
Summary Demultiplexer: Connects a single input line to one of n output lines, the specific output being determined by a selection code Multiplexers: Connects a single output line to one of n input lines, the specific input being determined by a selection code. Chapter 3-p2 IT32 34