INTEGRATED CIRCUITS. 74ALS573B/74ALS574A Latch flip flop. Product specification IC05 Data Handbook Feb 08

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INTGRAT CIRCUITS Latch flip flop IC05 ata Handbook Feb 08

74ALS573B 74ALS574A Octal traparent latch (3-State) Octal flip-flop (3-State) FATURS 74ALS573B is broadside pinout version of 74ALS373 74ALS574A is broadside pinout version of 74ALS374 Inputs and outputs on opposite side of package allow easy interface to microprocessors Useful as an input or output port for microprocessors 3-State outputs for bus interfacing Common output enable 74ALS563A and 74ALS564A are inverting version of 74ALS573B and 74ALS574A respectively SCRIPTION The 74ALS573B is an octal traparent latch coupled to eight 3-State output devices. The two sectio of the device are controlled independently by enable () and output enable (O) control gates. The 74ALS573B is functionally identical to the 74ALS373 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the inputs is traferred to the latch outputs when the enable () input is High. The latch remai traparent to the data input while is High, and stores the data that is present one setup time before the High-to-Low enable traition. The 74ALS574A is functionally identical to the 74ALS374 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. It is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sectio of the device are controlled independently by clock (CP) and output enable (O) control gates. The register is fully edge triggered. The state of the input, one setup time before the Low-to-High clock traition is traferred to the corresponding flip-flop s output. The active-low output enable (O) controls all eight 3-State buffers independent of the latch operation. When O is Low, latched or traparent data appears at the output. When O is High, the outputs are in high impedance off state, which mea they will neither drive nor load the bus. TYP TYPICAL PROPAGATION LAY TYPICAL SUPPLY CURRNT (TOTAL) 74ALS573B 5.0 ma 74ALS574A 6.0 5mA ORRING INFORMATION SCRIPTION ORR CO COMMRCIAL RANG V CC = 5V ±0%, T amb = 0 C to +70 C RAWING NUMBR 0-pin plastic IP 74ALS573BN, 74ALS574AN SOT46-0-pin plastic SOL 74ALS573B, 74ALS574A SOT3-0-pin plastic SSOP Type II 74ALS573BB, 74ALS574AB SOT33- INPUT AN OUTPUT LOAING AN FAN-OUT TABL NOT: PINS SCRIPTION 74ALS (U.L.) HIGH/LOW LOA VALU HIGH/LOW 0 7 ata inputs.0/.0 0µA/0.mA (74ALS573B) Latch enable input.0/.0 0µA/0.mA O Output nable input (active-low).0/.0 0µA/0.mA CP (74ALS574A) Clock pulse input (active rising edge).0/.0 0µA/0.mA 0 7 ata outputs 30/40.6mA/4mA One (.0) ALS unit load is defined as: 0µA in the High state and 0.mA in the Low state. Feb 08 853 307 070

PIN CONFIGURATION 74ALS573B PIN CONFIGURATION 74ALS574A O 0 V CC O 0 V CC 0 0 0 0 3 8 3 8 4 7 4 7 3 5 3 3 5 3 4 6 5 4 4 6 5 4 5 7 4 5 5 7 4 5 6 8 3 6 6 8 3 6 7 7 7 7 GN 0 GN 0 CP SF0073 SF0074 LOGIC SYMBOL 74ALS573B LOGIC SYMBOL 74ALS574A 3 4 5 6 7 8 3 4 5 6 7 8 0 3 4 5 6 7 CP 0 3 4 5 6 7 O 0 3 4 5 6 7 O 0 3 4 5 6 7 8 7 5 4 3 8 7 5 4 3 V CC =Pin 0 GN=Pin 0 SF0075 V CC =Pin 0 GN=Pin 0 SF0076 IC/I SYMBOL 74ALS573B IC/I SYMBOL 74ALS574A N N N C 3 8 3 8 4 5 7 4 5 7 6 7 5 4 6 7 5 4 8 3 8 3 SF0077 SF0078 Feb 08 3

LOGIC IAGRAM 74ALS573B 0 3 4 3 5 4 6 5 7 6 8 7 O 8 7 5 4 3 V CC = Pin 0 GN = Pin 0 0 3 4 5 6 7 SC000 FUNCTION TABL 74ALS573B INPUTS OUTPUTS INTRNAL O n RGISTR 0 7 L H L L L L H H H H L l L L L h H H L L X NC NC Hold H L X NC Z H H n n Z H = High-voltage level h = High state must be present one setup time before the High-to-Low enable traition L = Low-voltage level l = Low state must be present one setup time before the High-to-Low enable traition NC= No change X = on t care Z = High impedance off state = High-to-Low enable traition LOGIC IAGRAM 74ALS574A OPRATING MO nable and read register Latch and read register isable outputs 0 3 4 3 5 4 6 5 7 6 8 7 CP V CC = Pin 0 GN = Pin 0 O 0 8 7 3 4 5 5 4 6 3 7 SC000 Feb 08 4

FUNCTION TABL 74ALS574A INPUTS OUTPUTS INTRNAL O CP n RGISTR 0 7 L l L L L h H H L X NC NC Hold H X NC Z H n n Z H = High-voltage level h = High state must be present one setup time before the Low-to-High clock traition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock traition NC= No change X = on t care Z = High impedance off state = Low-to-High clock traition = Not Low-to-High clock traition OPRATING MO Latch and read register isable outputs ABSOLUT MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMTR RATING UNIT V CC Supply voltage 0.5 to +7.0 V V IN Input voltage 0.5 to +7.0 V I IN Input current 30 to +5 ma V OUT Voltage applied to output in High output state 0.5 to V CC V I OUT Current applied to output in Low output state 48 ma T amb Operating free-air temperature range 0 to +70 C T stg Storage temperature range 65 to +50 C RCOMMN OPRATING CONITIONS SYMBOL PARAMTR LIMITS MIN NOM MAX V CC Supply voltage 4.5 5.0 5.5 V V IH High-level input voltage.0 V V IL Low-level input voltage 0.8 V I IK Input clamp current 8 ma I OH High-level output current.6 ma I OL Low-level output current 4 ma T amb Operating free-air temperature range 0 +70 C UNIT Feb 08 5

C LCTRICAL CHARACTRISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMTR TST CONITIONS MIN TYP MAX LIMITS UNIT V = ±0%, V = MAX, I OH = 0.4mA V CC V V OH High-level output voltage CC, IL V IH = MIN I OH = MAX.4 3. V V = MIN, V = MAX, I OL = ma 0.5 0.40 V V OL Low-level output voltage CC IL V IH = MIN I OL = 4mA 0.35 0.50 V V IK Input clamp voltage V CC = MIN, I I = I IK 0.73. V I I Input current at minimum input voltage V CC = MAX, V I = 7.0V 0. ma I IH High-level input current V CC = MAX, V I =.7V 0 µa I IL I OZH I OZL Low-level input current Off-state output current, High-level voltage applied Off-state output current, Low-level voltage applied 74ALS573B V CC = MAX, V I = 0.4V 0. ma 74ALS574A V CC = MAX, V I = 0.4V 0. ma V CC = MAX, V I =.7V 0 µa V CC = MAX, V I = 0.4V 0 µa I O Output current 3 V CC = MAX, V O =.5V 30 ma I CC Supply current (total) I CCH 7 ma 74ALS573B I CCL V CC = MAX 3 ma I CCZ 5 4 ma I CCH 0 ma 74ALS574A I CCL V CC = MAX 7 7 ma I CCZ 8 8 ma NOTS:. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type.. All typical values are at V CC = 5V, T amb = 5 C. 3. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I OS. Feb 08 6

AC LCTRICAL CHARACTRISTICS SYMBOL PARAMTR TST CONITION t PLH t PHL t PLH t PHL t PZH t PZL t PHZ t PLZ Propagation delay n to n Propagation delay to n Output enable time to High or Low level Output disable time from High or Low level 74ALS573B Waveform 3 Waveform Waveform 6 Waveform 7 Waveform 6 Waveform 7 LIMITS T amb = 0 C to +70 C V CC = +5.0V ± 0% C L = 50pF, R L = 500Ω f MAX Maximum clock frequency Waveform 45 MHz t PLH t PHL t PZH t PZL t PHZ t PLZ Propagation delay CP to n Output enable time to High or Low level Output disable time from High or Low level AC STUP CHARACTRISTICS Waveform 74ALS574A Waveform 6 Waveform 7 Waveform 6 Waveform 7 SYMBOL PARAMTR TST CONITION t su (H) t su (L) t h (H) t h (L) Setup time, High or Low n to Hold time, High or Low n to 74ALS573B Waveform 4 Waveform 4 MIN.0.0 4.0 4.0.0 4.0.0.0 3.0 4.0.0 4.0.0.0 LIMITS MAX 0.0 0.0.0.0.0.0.0.0.0.0.0.0.0.0 T amb = 0 C to +70 C V CC = +5.0V ± 0% C L = 50pF, R L = 500Ω t w (H) Pulse width, High Waveform 0.0 t su (H) t su (L) t h (H) t h (L) t w (H) t w (L) Setup time, High or Low n to CP Hold time, High or Low n to CP CP Pulse width, High or Low Waveform 5 74ALS574A Waveform 5 Waveform 5 MIN 6.0 6.0 6.0 6.0 6.0 6.0.0.0 8.0.0 MAX UNIT UNIT Feb 08 7

AC WAVFORMS For all waveforms, =.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. /f max CP t w (H) t w (H) t PLH t w (L) t PHL t PHL t PLH n n SF0058 Waveform. Propagation elay for Clock Input to Output, Clock Pulse Widths, and Maximum Clock Frequency Waveform. SF005 Propagation elay for nable to Output and nable Pulse Width n t PLH t PHL n SF0060 Waveform 3. Propagation elay for ata to Output n n t su (H) t h (H) t su (L) t h (L) t su (H) t h (H) t su (L) t h (L) CP SF006 SF006 Waveform 4. ata Setup Time and Hold Times Waveform 5. ata Setup Time and Hold Times O O t t V PZH PHZ OH -0.3V n 0V SC000 Waveform 6. 3-State Output nable Time to High Level and Output isable Time from High Level t PZL t PLZ 3.5V n V OL +0.3V SC0000 Waveform 7. 3-State Output nable Time to Low Level and Output isable Time from Low Level Feb 08 8

TST CIRCUIT AN WAVFORMS PULS GNRATOR V IN V CC.U.T. V OUT R L 7.0V NGATIV PULS 0% 0% t THL ( t ff) t w t TLH ( t r ) 0% 0% AMP (V) 0.3V R T C L Test Circuit for 3-State Outputs SWITCH POSITION TST SWITCH t PLZ, t PZL closed All other open FINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to Z OUT of pulse generators. R L POSITIV PULS 0% Family 74ALS 0% t TLH ( t r ) Amplitude 3.5V.3V t w t THL ( t f ) Input Pulse efinition 0% 0% INPUT PULS RUIRMNTS 0.3V Rep.Rate t w t TLH t THL MHz 500.0.0 AMP (V) SC0007 Feb 08

Latch/flip flop IP0: plastic dual in-line package; 0 leads (300 mil) SOT46- Feb 08 0

Latch/flip flop SO0: plastic small outline package; 0 leads; body width 7.5 mm SOT3- Feb 08

Latch/flip flop SSOP0: plastic shrink small outline package; 0 leads; body width 5.3 mm SOT33- Feb 08

Latch/flip flop FINITIONS ata Sheet Identification Product Status efinition Objective Specification Preliminary Specification Product Specification Formative or in esign Preproduction Product Full Production This data sheet contai the design target or goal specificatio for product development. Specificatio may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contai Final Specificatio. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips lectronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. LIF SUPPORT APPLICATIONS Philips Semiconductors and Philips lectronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips lectronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips lectronics North America Corporation customers using or selling Philips Semiconductors and Philips lectronics North America Corporation Products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips lectronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 8 ast Arques Avenue P.O. Box 340 Sunnyvale, California 4088 340 Telephone 800-34-738 Copyright Philips lectronics North America Corporation 7 All rights reserved. Printed in U.S.A. Feb 08 3