IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 4, JULY

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 4, JULY 2008 1649 Open-Loop Control Methods for Interleaved DCM/CCM Boundary Boost PFC Converters Laszlo Huber, Member, IEEE, Brian T. Irving, and Milan M. Jovanović, Fellow, IEEE Abstract Open-loop interleaving methods for PFC boost converters operating at the boundary of discontinuous-conduction mode and continuous-conduction mode with a master-slave relationship are analyzed. It is shown that the only method that results in stable operation is the synchronization of the slave converter to the turn-on instant of the master converter, where each converter operates with current-mode control. Effects of mismatched inductances, phase-shift error, switching-frequency limit, and valley switching on the quality of the input current are discussed in detail. Index Terms Interleaved boost, open-loop control, power factor correction (PFC), variable frequency, zero-voltage switching (ZVS). I. INTRODUCTION I N off-line power supplies that require active power factor correction (PFC), a boost converter operating at the boundary of discontinuous conduction mode (DCM) and continuous conduction mode (CCM) is a widely employed topology at low-power levels (up to 200 300 W) because it is more efficient and more cost effective than the CCM boost PFC converter [1] [4]. These benefits are brought about by the elimination of the reverse-recovery losses of the boost diode and by turning on the boost switch with zero-voltage switching (ZVS) or near ZVS (also called valley switching). Neither the CCM nor the DCM boost PFC converter, which operate with a constant switching frequency, can achieve ZVS without an additional active snubber circuit. Other benefits of the DCM/CCM boundary boost PFC converter compared to the constant-switching-frequency DCM boost PFC converter are a lower total-harmonic distortion (THD) of the line current, and a smaller peak inductor current resulting in lower turn-off switching losses and lower conduction losses [5]. Although the DCM/CCM boundary boost PFC converter exhibits a smaller peak inductor current than the DCM boost PFC converter, its peak inductor current is still twice its average current, which often necessitates a large differential mode (DM) electromagnetic interference (EMI) filter [11]. Another drawback is that its switching frequency, which changes with the instantaneous line voltage and the output power, varies over a wide range. In order to prevent excessive switching losses, a maximum switching-frequency limit is often implemented. Manuscript received March 14, 2007; revised July 26, 2007. Published June 20, 2008. Recommended for publication by Associate Editor B. Fahimi. The authors are with Delta Products Corporation, Power Electronics Laboratory, Research Triangle Park, NC 27709 USA (e-mail: lhuber@deltartp.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2008.924611 Fig. 1. Basic topology of two interleaved PFC boost converters. Generally, the input current ripple and, consequently, the input DM-EMI filter can be significantly reduced by interleaving two or more boost PFC converters as shown in Fig. 1 [6] [19]. In addition, the output current ripple can be also significantly reduced, resulting in a reduced equivalent-series-resistance (esr) loss of the output capacitor, and possibly a reduction in capacitor volume. Another benefit of interleaving is that the efficiency at lighter loads can be increased by employing phase shedding, i.e., by progressively turning off converters as the load is decreased. By interleaving two or more DCM/CCM boundary boost converters, the benefits of DCM/CCM boundary boost PFC converters mentioned above can be extended to higher power levels. However, since the switching frequency is variable, the synchronization of interleaved DCM/CCM boundary boost PFC converters presents a challenging task. Very few implementations of the interleaved DCM/CCM boundary boost PFC converters have been published in the literature [11] [19]. All previously published implementations are based on a master-slave relationship, where the master converter operates as a stand-alone converter, whereas, the slave converter(s) is partially controlled by the master in order to achieve proper interleaving, i.e., a proper phase shift with respect to the master. It has been shown that the slave converter can be synchronized to the master converter with an open-loop method [11] [16], i.e., by generating a time delay equal to half the switching period of the master determined from its previous switching cycle, or with a closed-loop method [17] [19], i.e., by measuring the phase difference between the converters and adjusting the phase of the slave based on the phase error. The slave converter with open-loop synchronization can be synchronized to the turn-on instant of the master converter [12] [15] or to the turn-off instant of the master converter [11], [16]. The slave converter with closed-loop synchronization has been synchronized to the master converter by using a phase-locked-loop (PLL) approach and adjusting the turn-off instant of the slave converter [17] [19]. 0885-8993/$25.00 2008 IEEE

1650 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 4, JULY 2008 Fig. 2. (a) Basic control circuit and (b) key waveforms of two interleaved DCM/CCM boundary boost PFC converters with current-mode control, with matched inductances, when the slave is synchronized to the turn-on instant of the master. However, none of these papers [11] [19] offers a complete analysis of the behavior of the interleaved converters. Specifically, no analysis of the effect of components mismatching on steady-state and transient performance is given. In addition, for the open-loop synchronization methods, the response of the interleaved converters to phase-shift disturbances has not been addressed at all. As a result, practical limitations of some of the proposed implementations have not been properly recognized. This paper is focused on the analysis of the open-loop synchronization methods of the slave converter to the master converter. In Section II, synchronization of the slave converter to the turn-on instant and to the turn-off instant of the master converter for both current-mode and voltage-mode control is analyzed with respect to inductor tolerances and interleaving stability. It is shown that among the open-loop synchronization methods, the only method that results in stable operation is the synchronization of the slave converter to the turn-on instant of the master converter, where each converter operates with current-mode control. In Section III, the open-loop method where the slave is synchronized to the turn-on instant of the master is further analyzed with respect to the input current ripple. The effects of limiting the switching frequency and maintaining valley switching on both the input-current ripple and input-current distortion are also discussed. II. ANALYSIS OF OPERATION WITH OPEN-LOOP SYNCHRONIZATION METHODS As mentioned in Section I, with open-loop synchronization, the slave converter can be synchronized to the turn-on instant or to the turn-off instant of the master converter. In both cases, the converters can operate either with current-mode control or with voltage-mode control. A. Synchronization of Slave to Turn-On Instant of Master The basic control circuit and key waveforms when the slave converter is synchronized to the turn-on instant of the master converter are shown in Figs. 2 and 3 for current-mode and voltage-mode control, respectively. It is assumed in Figs. 2 and 3 that the inductances of the master and slave converters are matched, i.e.,. It is also assumed that the resonant Fig. 3. (a) Basic control circuit and (b) key waveforms of two interleaved DCM/CCM boundary boost PFC converters with voltage-mode control, with matched inductances, when the slave is synchronized to the turn-on instant of the master. interval, during which the voltage of a boost switch resonates down to its valley is negligible compared to the switching period. In both Figs. 2 and 3, the master is turned on by zero-current-detection pulse ZCD-M, and the slave is turned on after delay with respect to the turn-on instant of the master. Delay is equal to half the switching period of the master determined from the master s previous switching cycle. ZCD-M signal goes high once master inductor current decreases to zero. Both the master and slave are turned off by their own PWM, which compares a ramp signal to a feedback signal. In the case of current-mode control, shown in Fig. 2, the ramp signal is inductor current and the feedback signal is the sinusoidal reference current, which is proportional to the output of the voltage-loop error amplifier. In the case of voltage-mode control, shown in Fig. 3, the ramp signal is ramp voltage, which has a constant slope and which is synchronized to the individual boost turn-on instant. The feedback signal is the output voltage of the voltage-loop error amplifier,. The key difference between current-mode and voltage-mode control circuits shown in Figs. 2 and 3 is that the slope of the ramp in current-mode control, i.e.,, changes proportionally with the voltage across inductor, and inversely with the inductance of inductor, whereas, the slope of the ramp in voltagemode control is always constant. This difference results in very different operation when the inductances are mismatched, or when delay time is perturbed. If the inductances of the master and slave with current-mode control are mismatched, the boost switch of the slave will lose ZVS turn-on. In fact, if, the slave will operate in DCM, as shown in Fig. 4(a) and, if, the boost switch of the slave will alternately turn on with hard switching and in DCM, i.e., the slave will operate with a subharmonic oscillation, as shown in Fig. 4(b). With voltage-mode control, if the inductances of the master and slave are mismatched, the ZVS turn-on of the slave switch will not be disturbed, as shown in Fig. 5. It can be seen in Fig. 5 that although the slope of the slave s inductor current changes, the on-time of the slave does not change because it is determined by the slave s voltage ramp which has

HUBER et al.: OPEN-LOOP CONTROL METHODS FOR INTERLEAVED DCM/CCM BOUNDARY BOOST PFC CONVERTERS 1651 Fig. 4. Inductor current waveforms of the master and slave operating with current-mode control, with mismatched inductances, when the slave is synchronized to the turn-on instant of the master: (a) L <L and (b) L >L. Fig. 6. Inductor current waveforms of the master and slave operating with current-mode control and with the slave synchronized to the turn-on instant of the master, when the slave s reference current is reduced with respect to the master s reference current. Fig. 5. Inductor current waveforms of the master and slave operating with voltage-mode control, with mismatched inductances, when the slave is synchronized to the turn-on instant of the master. a constant slope. The current sharing error in Fig. 5 can be determined as (1) where is the ratio of the boost inductances; whereas, and are respectively the master and slave inductor currents averaged over a switching cycle. Typically, the tolerance of the boost inductances is 5%, which results in a current sharing error of 10%. However, if the mismatch of the boost inductances is 10%, the current sharing error is 20%. To prevent the turn-on of the boost switch of the slave with hard switching in current-mode control and, consequently, an increased switching loss, the slave s reference current can be reduced with respect to the master s reference current, as shown in Fig. 6(a) [14]. Unfortunately, by reducing the slave s reference current, the current sharing between the master and slave becomes significantly worse. As shown in Fig. 6, the currentsharing error is the worst when the slave current reference is optimally lowered to ensure that the slave s boost switch never turns on with hard switching. The worst-case current sharing error is determined as (2) For 5% and 10% mismatch of the boost inductances, the current sharing error is 29.8% and 58.5%, respectively. A better approach to prevent the turn-on of the boost switch of the slave with hard switching in current-mode control is to identify the master and the slave during the initialization phase, i.e., to ensure that the inductance of the slave is always smaller than the inductance of the master. In that case, the inductor currents of the master and slave with mismatched inductances follow the waveforms shown in Fig. 4(a) and the current sharing error is determined with the same expression as (1). For 5% and 10% mismatch of the boost inductances, the current sharing error is 10% and 20%, respectively. Effects of the delay-time perturbation on the operation of the slave with current-mode control and with voltage-mode control are shown in Figs. 7 and 8, respectively. As shown in Fig. 7, the slave with current-mode control always returns to normal operation after one or two switching cycles. In fact, the slave with current-mode control returns to normal operation after one switching cycle when the perturbed delay time is smaller than, as shown in Fig. 7(a) and 7(c), and after two switching cycles when the perturbed delay time is greater than, as shown in Fig. 7(b) and 7(d). However, the slave with voltage-mode control cannot always returns to normal operation, as shown in Fig. 8. When the perturbed delay time is smaller than, the slave with voltage-mode control returns to normal operation by the next switching cycle, as shown in Fig. 8(a) and 8(c). When the perturbed delay time is greater than, the slave with voltage-mode control cannot return to normal operation, as shown in Fig. 8(b) and 8(d). B. Synchronization of Slave to Turn-Off Instant of Master The basic control circuit and key waveforms when the slave is synchronized to the turn-off instant of the master are shown in Figs. 9 and 10, respectively, for current-mode and voltage-mode control. It is assumed in Figs. 9 and 10 that the inductances of the master and slave are matched, i.e.,. It follows from Figs. 9(a) and 10(a) that the current-mode or voltage-mode control is only relevant for the operation of the master, whereas, the operation of the slave is identical in both control modes. Unlike in Figs. 2 and 3, the slave is turned on by zero-currentdetection pulse ZCD-S, which goes high once slave inductor current decreases to zero. The slave is turned off with a

1652 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 4, JULY 2008 Fig. 7. Effect of delay-time perturbation on the operation of the slave with current-mode control, when the slave is synchronized to the turn-on instant of the master: (a) D>0:5, T <T =2, (b) D>0:5, T >T =2, (c) D<0:5, T <T =2, and (d) D<0:5, T >T =2. delay with respect to the turn-off instant of the master. Delay is equal to half the switching period of the master determined from the master s previous switching cycle. The operation of the master is identical to that when the slave is synchronized to the turn-on instant of the master described in the previous subsection. Both the master and slave turn on with ZVS. If the inductances of the master and slave with either current-mode or voltage-mode control are mismatched, the ZVS turn-on of the slave switch will not be disturbed, as shown in Fig. 11. The current sharing error, defined in (1), for 5% and 10% mismatch of the boost inductances is 10% and 20%, respectively. Effects of the delay-time perturbation on the operation of the slave are shown in Fig. 12. Since the operation of the slave is identical in both current-mode and voltage-mode control, the effects of the delay time perturbation on the operation of the slave shown in Fig. 12 include both control modes. As shown in Fig. 12(a) and (b), if the duty cycle is greater than 0.5, the slave returns to normal operation after a few switching cycles. It can be seen in Fig. 12(a) and (b) that the error between the disturbed and nondisturbed inductor currents of the slave continuously decreases with each switching cycle. However, if the duty cycle is smaller than 0.5, the slave cannot return to normal operation and, in fact, oscillates, as shown in Fig. 12(c) and (d). It can be seen in Fig. 12(c) and (d) that the error between the disturbed and nondisturbed inductor currents of the slave continuously increases with each switching cycle. A summary of open-loop synchronization methods is presented in Table I. The only open-loop method that results in stable operation at any duty cycle is the synchronization of the Fig. 8. Effect of delay-time perturbation on the operation of the slave with voltage-mode control, when the slave is synchronized to the turn-on instant of the master: (a) D > 0:5, T < T =2, (b) D > 0:5, T > T =2, (c) D<0:5, T <T =2, and (d) D<0:5, T >T =2. Fig. 9. (a) Basic control circuit and (b) key waveforms of two interleaved DCM/CCM boundary boost PFC converters with current-mode control, with matched inductances, when the slave is synchronized to the turn-off instant of the master.

HUBER et al.: OPEN-LOOP CONTROL METHODS FOR INTERLEAVED DCM/CCM BOUNDARY BOOST PFC CONVERTERS 1653 III. ANALYSIS OF INPUT CURRENT WAVEFORM In this section, the open-loop method where the slave is synchronized to the turn-on instant of the master and where each operates with current-mode control, is further analyzed with respect to the input-current ripple and the input-current distortion. To limit the current sharing error below a reasonable 20%, it is assumed that the master and the slave are identified during the initialization phase. As a result, the reference current of the slave is identical to the reference current of the master. For an additional safety margin, the reference current of the slave can be slightly reduced (0.5% 1%) compared to the reference current of the master. Fig. 10. (a) Basic control circuit and (b) key waveforms of two interleaved DCM/CCM boundary boost PFC converters with voltage-mode control, with matched inductances, when the slave is synchronized to the turn-off instant of the master. Fig. 11. Inductor current waveforms of the master and slave operating with either current-mode control or voltage-mode control, with mismatched inductances, when the slave is synchronized to the turn-off instant of the master. A. Input-Current Ripple The inductor currents of the master and slave for the ideal case when the inductances of the master and slave are matched and the slave is 180 phase shifted with respect to the master are shown in Fig. 13. Fig. 13 also shows the sum of the inductor currents,, i.e., the unfiltered input current, which has a frequency equal to twice the switching frequency and has a peak-to-peak current ripple significantly smaller than the ripple of the individual inductor currents. Generally, input-current ripple is minimal when the phase shift is 180 and maximal (twice ) when the phase shift is 0. The input-current ripple is dependent on the duty cycle, converter tolerances, e.g., tolerance of the boost inductances, as well as an improper phase shift between the converters. The input-current ripple normalized to the peak inductor current is determined as for for (3) Fig. 12. Effect of delay-time perturbation on the operation of the slave with current-mode control or voltage-mode control, when the slave is synchronized to the turn-off instant of the master: (a) D>0:5, T <T =2, (b) D>0:5, T >T =2, (c) D<0:5, T <T =2, and (d) D<0:5, T >T =2. slave converter to the turn-on instant of the master converter, where each converter operates with current-mode control. The normalized input current ripple as a function of duty cycle is shown in Fig. 14(a). The filtered input current,, is obtained by averaging the unfiltered input current over a switching period, i.e.,. It can be easily shown that the filtered input current is equal to the peak inductor current, i.e.,. The filtered input current and the unfiltered input current over a half line cycle for the ideal case of matched inductances and 180 phase shift of the slave versus master are presented in Fig. 14(b). The unfiltered input current is presented with its upper and lower envelope. Both the filtered and unfiltered input current in Fig. 14(b) are normalized to the peak value of the filtered input current,. The input-current ripple in Fig. 14(b) is obtained from (3) by substituting the variation of the duty cycle during a half line cycle, i.e., in (3). It follows from Fig. 14(b) that the input-current ripple is maximal at, where. Component tolerances, particularly the tolerance of boost inductance, lead to a mismatch between the boost stages and, therefore, increase input-current ripple, as shown in Fig. 15. The normalized input-current ripple as a function of duty cycle for three different tolerances of the boost inductances is shown in Fig. 15(a). Unfortunately, the relationship cannot be expressed in a closed form. It should be noted in Fig. 15(a) that the perfect ripple cancellation at is lost for any inductance mismatch. The unfiltered

1654 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 4, JULY 2008 TABLE I SUMMARY OF OPEN-LOOP SYNCHRONIZATION METHODS Master and Slave are identified during the initialization phase (always L <L ) Master and Slave are NOT identified during the initialization phase (L L or L L ) Fig. 13. Boost inductor currents for matched inductances with 180 phase shift and duty cycle greater than 0.5. Fig. 15. Input-current ripple of mismatched boost inductances: (a) normalized input-current ripple as a function of duty cycle and (b) upper and lower inputcurrent envelopes for V = 230V, V = 385 V, P = 250 W, and L = 230 H. Fig. 14. Input-current ripple for the ideal case of matched boost inductances with 180 phase shift: (a) normalized input-current ripple as a function of duty cycle and (b) upper and lower input-current envelopes for V =230V and V =385V. If the slave has a turn-on delay of, i.e., if the phase shift is greater than 180, the normalized input-current ripple can be derived in a closed form, i.e., for for (4) input current, corresponding to Fig. 15(a), is presented in Fig. 15(b). For the worst case in Fig. 15, when, the maximal input-current ripple is, which is a 29% increase compared to the ideal case. In (4), is the switching period determined as (5)

HUBER et al.: OPEN-LOOP CONTROL METHODS FOR INTERLEAVED DCM/CCM BOUNDARY BOOST PFC CONVERTERS 1655 Fig. 17. Key switching waveforms of both master and slave boost converter operating with switching-frequency limit and valley switching. Fig. 16. Input-current ripple of matched boost inductances with slave turn-on time delay for V = 230V, V =385V, P = 250 W, and L = 230 H: (a) normalized input-current ripple as a function of duty cycle and (b) upper and lower input-current envelopes. where and represent the output power of a single boost converter and the total output power of both boost converters, respectively, and is the boost inductance of a single converter. The normalized input-current ripple (4) versus duty cycle and the corresponding filtered and unfiltered input currents over a half line cycle are presented in Fig. 16 for three different turn-on delays at,, and. For the worst case in Fig. 16, when (i.e., 195 phase shift), the maximal input-current ripple is, which is a 10% increase compared to the ideal case. Again, it should be noted in Fig. 16(a) that the perfect ripple cancellation at is lost for any turn-on delay of the slave. B. Effect of Frequency Limit and Valley Switching on Input-Current Ripple The switching frequency of the DCM/CCM boundary boost PFC converters, which is a function of both line voltage and load current, can vary over a very wide range. To prevent excessive switching losses (e.g., gate-drive loss and turn-off loss of the main switch), it is beneficial to limit the switching frequency. The switching losses can be further minimized by ensuring valley switching, i.e., turning on the boost switch when its voltage is minimum, under all conditions. The consequence of the switching-frequency limit and the valley switching is that the turn-on moment of each boost switch is dependent on, first, reaching the minimum switching period and, then, if not coincidental with the valley, waiting an additional resonant period before turning on the switch. Fig. 17 shows key switching waveforms obtained through SIMPLIS simulation for both the master and slave converters operating with switching-frequency limit and valley switching. It should be noted that the boost converters are identical (i.e., equal inductances, resistances, etc.), with the exception that the slave reference current level is set 0.5% lower than the master reference current level. This gives an additional safety margin to ensure that the slave converter operates with a slightly higher switching frequency when operating without synchronization. Generally, the master switch is turned on with a preset delay to achieve valley switching once the master-valley-ok and minimum-period-ok signals are both high. Once the master switch is turned on, the period ramp is reset and then linearly increases until the master switch is turned on again at the start of the next switching cycle. Since the slope of the period ramp is constant, the peak of the period ramp is proportional to the master switching period. The peak of the period ramp from the previous switching cycle is sampled, divided by two, held for one switching cycle, and compared with the period ramp in the current switching cycle to determine the proper interleaving phase shift of the slave converter. As shown in Fig. 17, as the switching period of each converter approaches the minimum switching-period limit, valley skipping begins to occur. Since the interleaving phase shift is determined by sampling the previous switching period of the master, and since the master is jittering between its first and second valley, an improper phase shift and, therefore, an increased current ripple occurs, as shown in Fig. 18(b). During time interval in Fig. 17, the master converter turns on at its second valley, which increases its switching period and, therefore, increases the peak of the period ramp. The increased peak of the period ramp is sampled, divided by two, and applied in the next switching cycle. However, during time interval, the master once again turns on at its first valley and, as a result, an improper phase shift occurs. Although the

1656 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 4, JULY 2008 Fig. 18. Effect of frequency limit and valley switching on input-current ripple. Fig. 19. Input current and voltage with and without frequency limit. interleaving phase shift is initially poor at the onset of the frequency limit, the tendency of the circuit is to correct itself, as shown in Fig. 18(a). It should be noted that since the slave naturally operates with a higher switching frequency when operating without synchronization, it reaches the minimum-period limit before the master, as shown in Fig. 17. In this example, the master converter begins to switch on at its second valley immediately after the slave. However, as the mismatch between the converters increases, it may happen that the master reaches the minimum period limit well after the slave converter. C. Effect of Frequency Limit on Input-Current Distortion It is well known that in a boost converter operating at the DCM/CCM boundary, PFC is achieved by keeping switch on-time constant during a half line cycle, which forces the inductor current averaged over a switching cycle,, to be proportional to instantaneous input voltage, i.e.,, where the resonant period is considered much shorter than switching period. Since the two converters are interleaved, the input current averaged over a switching cycle is simply twice the average individual inductor current. By limiting the maximum switching frequency, the boost converters effectively operate in DCM for a portion of the instantaneous input voltage. The average current is therefore no longer proportional to instantaneous input voltage, i.e., When the resonant period is taken into consideration, an abrupt change in the average input current can occur when the switch turn-on moment skips from one valley to the next. As a result, current distortion is introduced as shown in Fig. 19, which leads to a further degradation in power factor. Fig. 19 is obtained through SIMPLIS simulation using a 250-kHz frequency limit. However, it should be noted that although power factor PF is less than 0.99, total harmonic distortion THD indicates that the current harmonics are well below the EN61000-3-2 limit. It should (6) be also noted that the waveform of the input current with frequency limit at in Fig. 19 is similar to the line current waveform of a DCM boost PFC converter operating with a constant switching frequency presented in [5]. IV. SUMMARY In this paper, four open-loop interleaving methods for DCM/CCM boundary boost PFC converters with a master-slave relationship are thoroughly analyzed. With open-loop synchronization, the slave converter can be synchronized to the turn-on or to the turn-off instant of the master converter. In both cases, the converters can operate either with current-mode or voltage-mode control. It is shown that the only open-loop method that results in stable operation is the synchronization of the slave converter to the turn-on instant of the master converter, where each converter operates with current-mode control. To limit the current-sharing error below a reasonable 20%, which corresponds to 10% tolerance of the boost inductances, the master and the slave should be identified during the initialization phase. Otherwise, the current sharing error can be as high as 60%, which is practically unacceptable. Effects of mismatched inductances, phase-shift error, switching-frequency limit, and valley switching on the input current ripple and input current distortion are discussed in detail. REFERENCES [1] J. S. Lai and D. Chen, Design consideration for power factor correction boost converter operating at the boundary of continuous conduction mode and discontinuous conduction mode, in Proc. IEEE Applied Power Electronics Conf. (APEC), Mar. 1993, pp. 267 273. [2] J. W. Kim, S. M. Choi, and K. T. Kim, Variable on-time control of the critical conduction mode boost power factor correction converter to improve zero-crossing distortion, in Proc. IEEE Power Electronics and Drive Systems Conf. (PEDS), Nov. 2005, pp. 1542 1546. [3] Y.-K. Lo, J.-Y. Lin, and S.-Y. Ou, Switching-frequency control for regulated discontinuous-conduction-mode boost rectifiers, IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 760 768, Apr. 2007.

HUBER et al.: OPEN-LOOP CONTROL METHODS FOR INTERLEAVED DCM/CCM BOUNDARY BOOST PFC CONVERTERS 1657 [4] M. M. Jovanović and Y. Jang, State-of-the-art, single-phase, active power-factor-correction techniques for high-power applications An overview, IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 701 708, Jun. 2005. [5] K. H. Liu and Y. L. Lin, Current waveform distortion in power factor correction circuits employing discontinuous-mode boost converters, in Proc. IEEE Power Electronics Specialists Conf.(PESC)., Jun. 1989, pp. 825 829. [6] B. A. Miwa, D. M. Otten, and M. F. Schlecht, High efficiency power factor correction using interleaving techniques, in Proc. IEEE Applied Power Electronics Conf. (APEC), Feb. 1992, pp. 557 568. [7] L. Balogh and R. Redl, Power factor correction with interleaved boost converters in continuous-inductor-current mode, in Proc. IEEE Applied Power Electronics Conf. (APEC), Mar. 1993, pp. 168 174. [8] C. H. Chan and M. H. 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[13] T. Ishii and Y. Mizutani, Variable Frequency Switching of Synchronized Interleaved Switching Converters, U.S. Patent 5 905 369, May 18, 1999. [14] B. T. Irving, Y. Jang, and M. M. Jovanović, A comparative study of soft-switched CCM boost rectifiers and interleaved variable-frequency DCM boost rectifier, in Proc. IEEE Applied Power Electronics Conf. (APEC), Feb. 2000, pp. 171 177. [15] C. M. de Oliveira Stein, J. R. Pinheiro, and H. L. Hey, A ZCT auxiliary commutation circuit for interleaved boost converters operating in critical conduction mode, IEEE Trans. Power Electron., vol. 17, no. 6, pp. 954 962, Nov. 2002. [16] T. F. Wu, J. R. Tsai, Y. M. Chen, and Z. H. Tsai, Integrated circuits of a PFC controller for interleaved critical-mode boost converters, in Proc. IEEE Applied Power Electronics Conf. (APEC), Feb. 2007, pp. 1347 1350. [17] M. S. Elmore, Input current ripple cancellation in synchronized, parallel connected critically continuous boost converters, in Proc. IEEE Applied Power Electronics Conf. (APEC), Mar. 1996, pp. 152 158. [18] M. S. Elmore and K. A. Wallace, Zero Voltage Switching Supplies Connected in Parallel, U.S. Patent 5 793 191, Aug. 11, 1998. [19] A. Jansen, Master-Slave Critical Conduction Mode Power Converter, U.S. Patent Application 2006/0077604, Apr. 13, 2006. Laszlo Huber (M 86) was born in Novi Sad, Yugoslavia, in 1953. He received the Dipl. Eng. degree from the University of Novi Sad in 1977, the M.S. degree from the University of Niš, Niš, Yugoslavia, in 1983, and the Ph.D. degree from the University of Novi Sad in 1992, all in electrical engineering. From 1977 to 1992, he was an Instructor at the Institute for Power and Electronics, University of Novi Sad. In 1992, he joined the Virginia Power Electronics Center at Virginia Tech, Blacksburg, as a Visiting Professor. From 1993 to 1994, he was a Research Scientist at the Virginia Power Electronics Center. Since 1994, he has been a Senior Member of the R&D Staff at the Power Electronics Laboratory, Delta Products Corporation, Research Triangle Park, NC, the Advanced R&D unit of Delta Electronics, Inc., Taiwan, one of the world s largest manufacturers of power supplies. His 30-year experience includes the analysis, simulation, and design of high-frequency, high-power-density, single-phase and three-phase power processors; modeling, simulation, evaluation, and application of high-power semiconductor devices; and modeling, simulation, analysis, and design of analog and digital electronics circuits. He has published over 80 technical papers and holds four U.S. patents. Brian T. Irving was born in Ossining, NY, in 1973. He received the B.S. degree in electrical engineering from the University of Binghamton, Binghamton, NY, in 1998. From 1996 to 1998, he was an Engineer at Celestica Inc., Endicott, NY, where he designed PFC boost circuits for server power supplies. Since 1998, he has been a Member of R&D Staff at the Power Electronics Laboratory, Delta Products Corporation, located in Research Triangle Park, NC. His research interests include high-density, single-phase PFC circuits, control techniques, current sharing, modeling, and simulation. Milan M. Jovanović (F 01) received the Dipl. Ing. degree in electrical engineering from the University of Belgrade, Belgrade, Serbia. Presently, he is the Chief Technology Officer of the Power Systems Business Group of Delta Electronics, Inc., Taipei, Taiwan, R.O.C.