Comparison of Multi Carrier PWM Techniques applied to Five Level CHB Inverter

Similar documents
A Comparative Study of SPWM on A 5-Level H-NPC Inverter

Performance Improvement of Multilevel Inverter through Trapezoidal Triangular Carrier based PWM

Simulation of Five-Level Inverter with Sinusoidal PWM Carrier Technique Using MATLAB/Simulink

Performance Evaluation of Single Phase H-Bridge Type Diode Clamped Five Level Inverter

Keywords Asymmetric MLI, Fixed frequency phase shift PWM (FFPSPWM), variable frequency phase shift PWM (VFPSPWM), Total Harmonic Distortion (THD).

Speed Control of Induction Motor using Multilevel Inverter

Simulation of Multilevel Inverter Using PSIM

COMPARATIVE STUDY OF DIFFERENT TOPOLOGIES OF FIVE LEVEL INVERTER FOR HARMONICS REDUCTION

Level Shifted Pulse Width Modulation in Three Phase Multilevel Inverter for Power Quality Improvement

CARRIER BASED PWM TECHNIQUE FOR HARMONIC REDUCTION IN CASCADED MULTILEVEL INVERTERS

Analysis of Asymmetrical Cascaded 7 Level and 9 Level Multilevel Inverter Design for Asynchronous Motor

A Comparative Analysis of Multi Carrier SPWM Control Strategies using Fifteen Level Cascaded H bridge Multilevel Inverter

Series Parallel Switched Multilevel DC Link Inverter Fed Induction Motor

Literature Survey: Multilevel Voltage Source Inverter With Optimized Convention Of Bidirectional Switches

A Carrier Overlapping PWM Technique for Seven Level Asymmetrical Multilevel Inverter with various References

Analysis of Cascaded Multilevel Inverters with Series Connection of H- Bridge in PV Grid

Performance Evaluation of Multi Carrier Based PWM Techniques for Single Phase Five Level H-Bridge Type FCMLI

ISSN: International Journal of Science, Engineering and Technology Research (IJSETR) Volume 1, Issue 5, November 2012

MULTICARRIER TRAPEZOIDAL PWM STRATEGIES FOR A SINGLE PHASE FIVE LEVEL CASCADED INVERTER

NEW VARIABLE AMPLITUDE CARRIER OVERLAPPING PWM METHODS FOR THREE PHASE FIVE LEVEL CASCADED INVERTER

International Journal of Advance Engineering and Research Development

A comparative study of Total Harmonic Distortion in Multi level inverter topologies

IMPLEMENTATION OF MODIFIED REDUCED SWITCH MULTILEVEL INVERTER USING MCPWM AND MSPWM TECHNIQUES

New Multi Level Inverter with LSPWM Technique G. Sai Baba 1 G. Durga Prasad 2. P. Ram Prasad 3

Harmonic Evaluation of Multicarrier Pwm Techniques for Cascaded Multilevel Inverter

A Comparative Analysis of Modified Cascaded Multilevel Inverter Having Reduced Number of Switches and DC Sources

CASCADED H-BRIDGE MULTILEVEL INVERTER FOR INDUCTION MOTOR DRIVES

COMPARATIVE STUDY OF PWM TECHNIQUES FOR DIODE- CLAMPED MULTILEVEL-INVERTER

Hybrid 5-level inverter fed induction motor drive

Simulation and Analysis of ASCAD Multilevel Inverter with SPWM for Photovoltaic System

A Novel Multilevel Inverter Employing Additive and Subtractive Topology

Performance Metric of Z Source CHB Multilevel Inverter FED IM for Selective Harmonic Elimination and THD Reduction

Hardware Implementation of SPWM Based Diode Clamped Multilevel Invertr

Keywords: Multilevel inverter, Cascaded H- Bridge multilevel inverter, Multicarrier pulse width modulation, Total harmonic distortion.

An Implementation of 9-Level MLI using IPD-Topology for Harmonic Reduction

Comparison of carrier based PWM methods for Cascaded H-Bridge Multilevel Inverter

Study of five level inverter for harmonic elimination

Harmonic Analysis & Filter Design for a Novel Multilevel Inverter

HARMONIC ORIENTATION OF PULSE WIDTH MODULATION TECHNIQUE IN MULTILEVEL INVERTERS

Power Quality Analysis for Modular Structured Multilevel Inverter with Bipolar Variable Amplitude Multicarrier Pulse Width Modulation Techniques

PERFORMANCE ANALYSIS OF MULTI CARRIER BASED PULSE WIDTH MODULATED THREE PHASE CASCADED H-BRIDGE MULTILEVEL INVERTER

A Series-Connected Multilevel Inverter Topology for Squirrel-Cage Induction Motor Drive

Study of Unsymmetrical Cascade H-bridge Multilevel Inverter Design for Induction Motor

A Single-Phase Carrier Phase-shifted PWM Multilevel Inverter for 9-level with Reduced Switching Devices

Hardware Implementation of Cascaded Hybrid MLI with Reduced Switch Count

Design of Multi-Level Inverter and Its Application As Statcom to Compensate Voltage Sags Due to Faults

Multilevel Inverters: A Comparative Study of Pulse Width Modulation Techniques

Symmetrical Multilevel Inverter with Reduced Number of switches With Level Doubling Network

ISSN Vol.05,Issue.05, May-2017, Pages:

International Journal of Advance Engineering and Research Development

Simulation of Three Phase Cascaded H Bridge Inverter for Power Conditioning Using Solar Photovoltaic System

Analysis of New 7- Level an Asymmetrical Multilevel Inverter Topology with Reduced Switching Devices

COMPARATIVE STUDY ON CARRIER OVERLAPPING PWM STRATEGIES FOR THREE PHASE FIVE LEVEL DIODE CLAMPED AND CASCADED INVERTERS

Modified Multilevel Inverter Topology for Driving a Single Phase Induction Motor

A Novel Cascaded Multilevel Inverter Using A Single DC Source

EVALUATION OF VARIOUS UNIPOLAR MULTICARRIER PWM STRATEGIES FOR FIVE LEVEL FLYING CAPACITOR INVERTER

Nine-Level Cascaded H-Bridge Multilevel Inverter Divya Subramanian, Rebiya Rasheed

Multi Carrier PWM based Multi Level Inverter for High Power Application

INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET)

A Hybrid Cascaded Multilevel Inverter for Interfacing with Renewable Energy Resources

Multilevel Inverter with Coupled Inductors with Sine PWM Techniques

II. WORKING PRINCIPLE The block diagram depicting the working principle of the proposed topology is as given below in Fig.2.

A SOLUTION TO BALANCE THE VOLTAGE OF DC-LINK CAPACITOR USING BOOST CONVERTER IN DIODE CLAMPED MULTILEVEL INVERTER

Modified Transistor Clamped H-bridge-based Cascaded Multilevel inverter with high reliability.

International Journal Of Engineering And Computer Science ISSN: Volume 2 Issue 12 December, 2013 Page No Abstract

MODELING AND ANALYSIS OF THREE PHASE MULTIPLE OUTPUT INVERTER

Cascaded H-Bridge Multilevel Inverter

A New Transistor Clamped 5-Level H-Bridge Multilevel Inverter with voltage Boosting Capacity

Reduction in Total Harmonic Distortion Using Multilevel Inverters

Performance Analysis of Three Phase Cascaded H-Bridge Multi Level Inverter for Voltage Sag and Voltage Swell Conditions

Analysis and Simulation of a Cascaded H-Bridge Structure Electrical Converter With Separate DC Supply

Performance Study of Multiphase Multilevel Inverter Rajshree Bansod*, Prof. S. C. Rangari**

Enhanced Performance of Multilevel Inverter Fed Induction Motor Drive

Multilevel Inverter Based Statcom For Power System Load Balancing System

Power Quality Enhancement of Diode Clamped Multilevel Inverter Using Different Modulation Schemes

IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 04, 2016 ISSN (online):

A New Approach for Transistor-Clamped H-Bridge Multilevel Inverter with voltage Boosting Capacity Suparna Buchke, Prof. Kaushal Pratap Sengar

ANALYSIS AND IMPLEMENTATION OF FPGA CONTROL OF ASYMMETRIC MULTILEVEL INVERTER FOR FUEL CELL APPLICATIONS

Diode Clamped Multilevel Inverter Using PWM Technology

Analysis And Comparison Of Flying Capacitor And Modular Multilevel Converters Using SPWM

Original Article Development of multi carrier PWM technique for five level voltage source inverter

A New Cascaded Multilevel Inverter Fed Permanent Magnet Synchronous Motor By Using Sinusoidal Pulse Width Modulation

Simulation & Implementation Of Three Phase Induction Motor On Single Phase By Using PWM Techniques

AN IMPROVED MODULATION STRATEGY FOR A HYBRID MULTILEVEL INVERTER

Design and Implementation of 3-Phase 3-Level T-type Inverter with Different PWM Techniques

ADVANCED PWM SCHEMES FOR 3-PHASE CASCADED H-BRIDGE 5- LEVEL INVERTERS

HARMONIC REDUCTION COMPARISON IN MULTILEVEL INVERTERS FOR INDUSTRIAL APPLICATION

CHAPTER 3. NOVEL MODULATION TECHNIQUES for MULTILEVEL INVERTER and HYBRID MULTILEVEL INVERTER

[Gong* et al., 5.(6): June, 2016] ISSN: IC Value: 3.00 Impact Factor: 4.116

SIMULATION OF THREE PHASE MULTI- LEVEL INVERTER WITH LESS NUMBER OF POWER SWITCHES USING PWM METHODS

Performance Evaluation of a Cascaded Multilevel Inverter with a Single DC Source using ISCPWM

Simulation of Cascade H-Bridge Multilevel Inverter With Equal DC Voltage Source

Comparison between Conventional and Modified Cascaded H-Bridge Multilevel Inverter-Fed Drive

COMPARATIVE STUDY ON MCPWM STRATEGIES FOR 15 LEVEL ASYMMETRIC INVERTER

Sampled Reference Frame Algorithm Based on Space Vector Pulse Width Modulation for Five Level Cascaded H-Bridge Inverter

Multilevel DC-link Inverter Topology with Less Number of Switches

Elimination of Harmonics using Modified Space Vector Pulse Width Modulation Algorithm in an Eleven-level Cascaded H- bridge Inverter

Analysis of IM Fed by Multi-Carrier SPWM and Low Switching Frequency Mixed CMLI

Simulation and Comparison of Twenty Five Level Diode Clamped & Cascaded H-Bridge Multilevel Inverter

SEVEN LEVEL HYBRID ACTIVE NEUTRAL POINT CLAMPED FLYING CAPACITOR INVERTER

Transcription:

Volume 114 No. 7 2017, 77-87 ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu ijpam.eu Comparison of Multi Carrier PWM Techniques applied to Five Level CHB Inverter P S V Kishore 1, P Suresh Kumar 2, K Ramesh 3 1,2,3Vignan s IIT, AP, India pulavarthi.kishore@gmail.com suresh0260@gmail.com rameshkoyyana@gmail.com April 14-15, 2017 Abstract The use of Multi-level inverters has been increased due to their high power applications and the ability for getting nearly a sinusoidal output voltage compared to normal two level inverters. The various multilevel inverters in existence are Diode Clamped, Capacitor Clamped, and Cascaded H-bridge inverters. In order to get fewer harmonic various techniques are adopted to control the switches in a multilevel inverter. In this paper, multi carrier PWM techniques are used to generate the pulses to the switches in the 5-Level Cascaded H-bridge (CHB) inverter. MATLAB/Simulation is used to simulate the circuit and the results are tabulated. Keywords: Multi carrier PWM, CHB Inverter, Multi-level inverter, MATLAB/Simulation, five-level 1 Introduction Due to the advantage of high voltage operation, multilevel inverters have look forward for a wide range of research work. A part from 77

high voltage operation they provide fewer harmonics which lead to obtain a desired sine wave [1]. Due to this reason they were used in power converter topology for high power & voltage applications [2][3]. There are mainly three types of multilevel inverters. 1. Diode Clamped Multi-level Inverter (DCMI) 2. Capacitor Clamped Multi-level Inverter (CCMI) and 3. Cascaded H-Bridge Inverter (CHBI) The advantages of CHB inverters over other multi-level inverters are 1. It doesn t require diodes or capacitors for clamping. 2. It doesn t need any filter since the output waveform is nearly a sine wave. There are so many techniques available namely Sine PWM (SPWM), Space Vector PWM (SVPWM) [4] to generate pulses to the switches in these multilevel inverters so that the output voltage is nearly sinusoidal and contains less number of harmonics. The SPWM technique can be extended to multilevel inverters by using multiple carrier signals so it is called as Multi Carrier PWM technique. Different types of multicarrier PWM techniques have been applied to Z-source inverter [5-8] and in [9], multi carrier techniques are applied to diode clamped multi-level inverter. In this paper, three types of multicarrier techniques have been applied to five-level CHB inverter. 2 CHB Inverter Fig1: Five-level CHB inverter Fig2: Output of five-level CHB inverter 78

The major differences of DCMLI (Diode Clamped Multi-level inverter), CCMLI (Capacitor Clamped Multi-level Inverter) from CHBI is the methodology of obtaining the output voltage waveforms. A separate DC source is being used along with each CHB Inverter to create a stepped waveform. A simple single phase leg of a 5-level CHB inverter is shown in figure 1. The single H-bridge itself acts as a 3-level inverter. Here two H-bridge modules are used for getting 5 different voltage levels as shown in figure 2. Table 1 shows the switching pattern and the different output voltage levels for the fivelevel CHB inverter. Table 1: Switching pattern and output voltage levels of fivelevel CHB Switches in H-bridge 1 Switches in H-bridge 2 Voltage S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 level 1 1 0 0 1 1 0 0 2V 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 1 1 1 0 0 V 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 -V 1 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1-2V 3 Multi Carrier PWM techniques In a Sinusoidal PWM technique, a single sine wave is compared with a triangular (carrier) wave in order to generate pulses for the switching operations of an inverter. A sine PWM technique has been extended to multi-level inverter modules by taking more number of carriers. Hence it is simply called as multi carrier pulse width modulation technique. It requires (n-1) carrier waves for n level inverter. It is again simplified as Level Shifted PWM (carrier signals are arranged vertically) and Phase Shifted PWM (carrier signals are 79

arranged horizontally). LSPWM is again divided into three types. They are 1. Phase Disposition-PWM (PD-PWM), 2. Phase Opposition Disposition-PWM (POD-PWM) 3. Alternate Phase Opposition Disposition-PWM(APOD-PWM) [5]. In PD-PWM, all the carrier waves are in phase (fig 3), in POD- PWM, All the carrier waves above zero are in phase among them and all the carrier waves below the zero are in phase among them but in opposition to the earlier carrier waves (fig 4) and in APOD- PWM, all the carrier waves are in opposition alternatively from top to bottom. (fig 5) Here the peak to peak voltage of 3V is taken for each carrier wave and the sine reference wave is shown in figures 3-5 for the modulation index of 0.8 (that is, peak value of sine wave=6*0.8=4.8v). Here the figures 3-5 are shown for one cycle of sine reference wave. Fig3: PD-PWM Fig4: POD-PWM 80

Fig5: APOD-PWM 4 Simulation Results All the three multi carrier techniques are applied to five-level CHB inverter. Simulation is carried out in MATLAB/Simulink by taking the parameters as follows. 1. DC bus voltage=100v, 2. Modulation index (ratio of peak value of the reference wave to the peak value of the upper carrier wave), m=0.8, 1 and 3. Carrier frequency, fc =2500Hz, therefore frequency modulation ratio (ratio of carrier frequency to reference frequency), mf = 50 If p is the number of voltage levels in phase voltage of a multilevel inverter then the number of levels that the line voltage contain is (2p-1). Therefore for 5-level inverter, the number of levels in the line voltage is nine. When the reference waveform is more than the carrier wave, a pulse is produced. The pulses produced by the comparison of reference sine wave with upper and lower carriers, are given to the H-bridge 1 and the pulses produced by comparison of reference sine wave with the middle two carrier waves, are given to H-bridge 2. One phase of the simulation circuit is shown in fig 6 and the circuit for the three-phase is constructed by taking the reference sine wave with a phase shift of 120 and 240 degrees for the other two phases. 81

Fig 6: Simulation diagram for one leg for PD-PWM technique. The output voltages (both phase and line) and corresponding harmonic patterns are taken. Figure 7 and 8 shows the phase voltage, line voltage respectively and the corresponding harmonic pattern also shown when the PDPWM applied to 5-level CHB when the modulation index is one. Similarly the waveforms obtained when the POD PWM and APOD PWM applied to 5 level CHB when m=1, are shown in the figures 9-12. In all the figures, the harmonics in the line voltage decreases significantly since it contains more levels than the phase voltage. All these output voltages and harmonic content values are sown in table 2 for the modulation indexes of 0.8 and 1. When the modulation index increases from 0.8 to 1, the voltage peak voltage has increased and the harmonics decreased. Fig7: Phase voltage and harmonics for PD-PWM technique applied to 5-level CHB when m=1 82

Fig8: Line voltage and harmonics for PD-PWM technique applied to 5-level CHB when m=1 Fig9: Phase voltage and harmonics for POD-PWM technique applied to 5-level CHB when m=1 Fig10: Line voltage and harmonics for POD-PWM technique applied to 5-level CHB when m=1 83

Fig 11: Phase voltage and harmonics for APOD_PWM technique applied to 5-level CHB,m=1 Fig12: Phase voltage and harmonics for APOD-PWM technique applied to 5-level CHB, m=1 PWM techni que Table 2: Output voltages and percentage of harmonics for different modulation indexes. Peak of the Fundam ental (Vph)(V) Harmo nics (%) m=0.8 m=1 Peak of the fundam ental (Vline)(V) Harmo nics (%) Peak of the fundam ental (Vph)(V) Harmo nics (%) Peak of the fundam ental (Vline)(V) Harmo nics (%) PD 157.1 38.24 271.9 21.34 196.2 26.68 339.8 16.89 POD 157 37.52 272 35.35 196.1 26.59 339.9 21.34 APOD 157 37.62 271.9 29.50 196.2 26.63 339.8 25.34 84

5 Conclusion The three types of multicarrier PWM techniques (PD-PWM, POD-PWM and APOD-PWM) have been applied to the five-level CHB inverter for different modulation indexes. The phase and line voltage waveforms and the corresponding harmonic content is shown for the modulation index of unity and the results are tabulated for both modulation indexes. All the three techniques gave nearly the same fundamental voltage but Phase Disposition Pulse Width Modulation (PD-PWM) technique gives the less harmonic content. References [1]. L. Yiqiao, and C.O. Nwankpa, A new type of STATCOM based on cascading voltage source inverters with phase-shifted unipolar SPWM, IEEE Trans. on Industry Applications, Vol.35, No.5, 1999, pp1118-1123. [2]. L. Li, C. Dariusz, and Y. Liu, Multilevel space vector PWM technique based on phase-shift harmonic suppression, Applied Power Electronics Conference and Exposition (APEC), Vol.1, 2000, pp535-541. [3]. M.L. Tolbert, and F.Z. Peng, Multilevel Converters for Large Electric Drives, IEEE Trans. on Industry Applications, Vol.35, No.1, 1999, pp36-44. [4]. Satya Venkata Kishore, Dhana Prasad Duggapu Hardware Implementation of 3-Phase Three Level Diode Clamped MLI Using SVPWM Technique, International Journal of Emerging Trends in Electrical and Electronics, ISSN: 2320-9569, Vol. 12, Issue. 9, september-2016. [5]. Aparna Prayag and Sanjay Bodkhe, A Comparative Analysis of Classical Three Phase Multilevel (Five Level) Inverter Topologies 1st IEEE International Conference on Power Electronics,Intelligent Control and Energy Systems, 978-1-4673-8587-9/16 [6]. José Rodríguez, Senior Member, IEEE, Jih-Sheng Lai, Senior Member, IEEE, and Fang Zheng Peng, Senior Member, IEEE Multilevel Inverters: A Survey of Topologies, Controls, and Applications IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002 85

[7]. Giuseppe Carrara, Simone Gardella, Mario Marchesoni, Member, IEEE, Raffaele Salutari, and Giuseppe Sciutto A New Multilevel PWM Method: A Theoretical Analysis IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 7, NO. 3, JULY 1992. [8]. T.Sengolrajan, B.Shanthi, S.P.Natarajan, Comparative Study of Multicarrier PWM Techniques for Seven Level Cascaded Z-Source Inverter, International Journal of Computer Applications (0975 8887) Volume 65 No.6, March 2013. [9]. Ms.T.Prathiba, Dr.P.Renuga, Multi Carrier PWM based Multi Level Inverter for High Power Application, International Journal of Computer Applications (0975 8887) Volume 1 No. 9, 2010. 86

87

88