AN7 Application note IEEE80.af class PoE converter reference design high efficiency flyback converter based on the PM8800A Introduction By Antonio Rotta The PM8800A is a highly integrated device embedding an IEEE80.af compliant powered device (PD) interface together with a PWM controller and support for auxiliary sources. This document focuses on a reference design for a high efficiency, class PD (up to W input) power converter based on a flyback topology with pulse transformer driven synchronous rectification using the PM8800A as the main controller. Schematics of the PoE converter are given in Section, while the related bill of material is detailed in Section. In Section efficiency measurements together with main waveforms of the PoE interface and power converter are shown. October 0 Doc ID 07 Rev /6 www.st.com
Contents AN7 Contents Electrical specifications...................................... Schematics................................................ Bill of material.............................................. 6 Test results................................................ 8. Efficiency measurements...................................... 8. Waveforms................................................. 9.. Startup sequence.......................................... 9.. Primary side MOSFET...................................... 0.. Secondary side MOSFET..................................... Load transient..............................................5 Output ripple............................................. 5 Revision history........................................... 5 /6 Doc ID 07 Rev
AN7 Electrical specifications Electrical specifications Table. Specifications for. V output Parameter Description Min. Typ. Max. Unit Input voltage range Applied at RJ5 connector 0 57 V Operative input voltage 57 V UVLO Vin rising edge 6 V Vin falling edge 0 V Auxiliary input voltage range 8 56 V Output voltage (Vout) Vin = V to 57 V, Iout 0 to Imax.5.5.5 V Output current (Iout) Vin = V to 57 V 0.5 A Peak-to-peak output ripple 8 Vin, Iout = Imax 0 50 mvpp Efficiency DC-DC only Vin = 8 V, Iout = Imax 90 % Overall efficiency Vin = 8 V, Iout = Imax 88 % Switching frequency 50 khz Doc ID 07 Rev /6
Schematics AN7 Schematics Figure. High efficiency PoE converter schematic: detail of the input section including data transformers and terminations A B C D C C8 8 KV Chassis Termination Data Transformer Use std IEEE 80.af data transformer Typical value for resistor 75 ohm Typical value for capacitor 0nF R0 Chassis Chassis OUTPUT J RJ5 Data Jack Chassis 0 56 7 8 9 6 7 5 R 6 R R R5 C C5 R6 5 R7 6 7 0 8 9 T H09/TLA-6T7LF C6 8 KV 5 0 Chassis 56 7 8 8 9 T H09/TLA-6T7LF C R 6 5 Chassis INPUT 0 9 RJ5 Data and Power Jack AM950v /6 Doc ID 07 Rev
AN7 Schematics Figure. High efficiency PoE converter: flyback topology with pulse transformer driven synchronous rectification C5 uf 06 C GND C 0.uF AGND C8 0u 6V 06 R9 00k nf AGND R C R8 680 50 C5 uf 6V C 7nF D9 SOD GND AGND C59 uf 6V GND T 0 9 R R R6 56 06 8 7 D SOD SOD D C6 COILCRAFT POEP-L 68pF C9 0u 6V 06 R R0 06 MMBT906 Q7 SOT R8 00k C5 DO8H-ML L 0.uH C9.n 8 KV R5 7 R.5V.5A C 0u 6V 06 C 0u 6.V 8x0.5 C9 0.uF R6 0 C9 0nF R9 680 C0 uf 6V R k % R 5K % D0 C5 00pF R SOD U TS SOT-5.K % R7 % R.k % 0.uF C 6 D8 T7 SOD COILCRAFT DA9-AL GND C D9 MMBT906 Q6 SOT SOD 5 Sharp PCH7 0.uF C Q Si88 SO8 5 C6 0.uF D0 SOD 7 R8 C0 6V 06 C 6V 06 C7 5 Q STSNLLH5 SO8 7nF 8 7 6 5 GND R9 0. ohm 06 U 5 C 0.uF L 0uH MSS7-0ML C uf 06 6 C u 8x0. R 0k C8 0.uF R 70k % 7 AGND AGND 6 RT VFB 5 SS COMP COMP AUXII CS 8 CS VIN npgd npgd RCLASS VCC VCC GD AUXI_IRL C 70p GD 0 GND C6 0.u D STPSH00A Ex Pad GND 9 D STPSH00A DCCL VSS D0 STPSH00A D5 STPSH00A U PM8800A HTSSOP6 7 D STPSH00A D STPSH00A R8 5 D J58A STS0PF0L D STTHR0A Q SO8 R0 C R R D6 SOD D7 STTHR0A R 0R RT D5 SOD SS AUXII RCLASS AUXI_IRL DCCL VSS R7 % R5 R6 0k 5R % D8 STPSH00A D9 STPSH00A D5 BZX8C5 SOT C7 C R R5 R7 A B C D AUXII DC Power Jack C0 J AUXI DC Power Jack J C AM95v Doc ID 07 Rev 5/6
Bill of material AN7 Bill of material Table. Bill of material Qty. Reference Description Value Tol. Voltage Body Vendor C Ceramic capacitor 00 nf 00 V 60 TDK C, C, C, C5 Ceramic capacitor TBD 0% 00 V 60 TDK C6, C8 Ceramic capacitor TBD KV 8 TDK C Ceramic capacitor nf 0% 00 V 805 TDK C Aluminium capacitor µf 0% 00 V 80x0. Std low ESR C, C5 Ceramic capacitor µf 0% 00 V 06 TDK C6 Ceramic capacitor 68 pf 00 V 805 TDK C8, C9, C Ceramic capacitor 0 µf 6. V 805 TDK C Aluminium capacitor 0 µf 6. V 8x0. C5,C0, C59 Ceramic capacitor µf 0% 6 V 60 Std 6 C6, C8, C, C9, C, C5 Std low ESR Ceramic capacitor 00 nf 0% 50 V 60 Std C9 Ceramic capacitor. nf KV 8 TDK C, C7 Ceramic capacitor 7 nf 50 V 60 Std C Ceramic capacitor 70 pf 50 V 60 Std C9 Ceramic capacitor 0 nf 0% 50 V 60 Std D TVS diode J58A ST 9 8 D, D5, D8, D9, D0, D, D9, D0 D, D7, D8, D9, D, D, D, D7 Schottky diode 00 V SOD ST Schottky diode STPSH00A 00 V ST L SMT inductor 0 µh MSS7-0ML Coilcraft L SMT inductor 0. µh DO8H- ML Coilcraft Q MOSFET, N ch. Si 88 50 V SO8 Vishay Q MOSFET, N ch. STSNLLH5 0 V SO8 ST Q6, Q7 Transistor, PNP MMBT906LT 0 V SOT Std 8 R, R, R, R, R5, R6, R7, R0 Chip resistor TBD 60 Std 6/6 Doc ID 07 Rev
AN7 Bill of material Table. Bill of material (continued) Qty. Reference Description Value Tol. Voltage Body Vendor R Chip resistor R0 06 Std R6 Chip resistor 56 06 Std R8, R5 Chip resistor 7 60 Std R9 Chip resistor 00 K 805 Std R Chip resistor 70 K % 60 Std R, R6 Chip resistor 0 K 60 Std R Chip resistor 0 R 60 Std R6 Chip resistor 0 R 60 Std R8, R9 Chip resistor 680 60 Std R Chip resistor 60 Std R Chip resistor K % 60 Std R Chip resistor 50 60 Std R Chip resistor 5 K % 60 Std R5 Chip resistor 5R % 60 Std R8 Chip resistor 00 K 60 Std R9 Chip resistor 0. R 60 Std R Chip resistor. K % 60 Std R Chip resistor. K % 60 Std T, T POE+ magnetics H09 Pulse T Power transformer POEP-L Coilcraft T7 Gate driver transformer DA9-AL Coilcraft U POE controller PM8800A HTSSOP6 ST U SMT optocoupler PCH7 PDIP Sharp U Shunt regulator TSAILT SOT-5 ST Doc ID 07 Rev 7/6
Test results AN7 Test results. Efficiency measurements Figure. Efficiency measurements at 8 V input Isolated synchronous flyback converter with PM8800A Efficiency 00% 98% 96% 9% 9% 90% 88% 86% 8% 8% 80% 78% 76% 7% 7% 70% 68% 66% 6% 6% 60% 58% 56% overall dcdc + Hs input stage 5% 5% 50% 0.00 0.50.00.50.00.50.00 Iout (A) AM95v The difference between DC-DC and overall measurements is about % from A to full load. In Figure it is possible to see the contribution to the total losses of the PD interface section of the converter; the major contribution comes from the rectification bridge. 8/6 Doc ID 07 Rev
AN7 Test results. Waveforms.. Startup sequence Figure. Startup from the Cisco Catalyst 750E switch with A load Figure 5. Startup from the PowerDsine 900GR.at injector with A load Doc ID 07 Rev 9/6
Test results AN7 Figure 6. Startup from the Phihong PSA6U-80.af injector with A load.. Primary side MOSFET Figure 7. Primary side Power MOSFET waveforms at 0 A load 0/6 Doc ID 07 Rev
AN7 Test results Figure 8. Primary side Power MOSFET waveforms at A load.. Secondary side MOSFET Figure 9. Secondary side Power MOSFET waveforms at 0 A load Doc ID 07 Rev /6
Test results AN7 Figure 0. Secondary side Power MOSFET waveforms at A load.. Load transient Figure. Response of the converter to a.5 A - A load transient /6 Doc ID 07 Rev
AN7 Test results..5 Output ripple Figure. Output ripple measurement at A Figure. Output ripple measurement at A with infinite persistence Doc ID 07 Rev /6
Test results AN7 Figure. Output ripple measurement at 0 A /6 Doc ID 07 Rev
AN7 Revision history 5 Revision history Table. Document revision history Date Revision Changes 0-Oct-0 Initial release. Doc ID 07 Rev 5/6
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