TC74VHCT540AF, TC74VHCT540AFT, TC74VHCT540AFK TC74VHCT541AF, TC74VHCT541AFT, TC74VHCT541AFK

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TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT540AF, TC74VHCT540AFT, TC74VHCT540AFK TC74VHCT541AF, TC74VHCT541AFT, TC74VHCT541AFK Octal Bus Buffer TC74VHCT540AF/AFT/AFK Inverted, 3-State Outputs TC74VHCT541AF/AFT/AFK Non-Inverted, 3-State Outputs TC74VHCT540AF, TC74VHCT541AF The TC74VHCT540A and 541A are advanced high speed CMOS OCTAL BUS BUFFERs fabricated with silicon gate C 2 MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The TC74VHCT540A is an inverting type and, the TC74VHCT541A is a non-inverting type. When either G 1 or G 2 are high, the terminal outputs are in the high-impedance state. The input are compatible with TTL output. These devices may be used as a level converter for interfacing 3.3 V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply. These structure prevents device destruction due to mismatched supply and input/output s such as battery back up, hot board insertion, etc. TC74VHCT540AFT, TC74VHCT541AFT TC74VHCT540AFK, TC74VHCT541AFK Note: Output in off-state Features High speed: t pd = 5.4 ns (typ.) at V CC = 5 V Low power dissipation: I CC = 4 μa (max) at Ta = 25 C Compatible with TTL inputs: V IL = 0.8 V (max) V IH = 2.0 V (min) Power down protection is provided on all inputs and outputs Balanced propagation delays: t plh t phl Low noise: V OLP = 1.5 V (max) Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc.) 540/541 type. Weight SOP20-P-300-1.27A: 0.22 g (typ.) TSSOP20-P-0044-0.65A: 0.08 g (typ.) VSSOP20-P-0030-0.50: 0.03 g (typ.) Start of commercial production 1995-09 1

Pin Assignment TC74VHCT540A TC74VHCT541A G 1 1 20 V CC G1 1 20 V CC A1 2 19 G2 A1 2 19 G2 A2 3 18 Y1 A2 3 18 Y1 A3 4 17 Y2 A3 4 17 Y2 A4 5 16 Y3 A4 5 16 Y3 A5 6 15 Y4 A5 6 15 Y4 A6 7 14 Y5 A6 7 14 Y5 A7 8 13 Y6 A7 8 13 Y6 A8 9 12 Y7 A8 9 12 Y7 GND 10 11 Y8 GND 10 11 Y8 (top view) (top view) IEC Logic Symbol G1 G2 (1) (19) TC74VHCT540A & EN G1 G2 (1) (19) TC74VHCT541A & EN A1 A2 A3 A4 A5 A6 A7 A8 (2) (3) (4) (5) (6) (7) (8) (9) (18) (17) (16) (15) (14) (13) (12) (11) Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A1 A2 A3 A4 A5 A6 A7 A8 (2) (3) (4) (5) (6) (7) (8) (9) (18) (17) (16) (15) (14) (13) (12) (11) Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Truth Table Inputs Outputs G 1 G 2 A n Y n Y n H X X Z Z X H X Z Z L L H H L L L L L H X: Don t care Z: High impedance Y n : VHCT541A Y n : VHCT540A 2

Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply range V CC 0.5 to 7.0 V DC input V IN 0.5 to 7.0 V DC output V OUT 0.5 to 7.0 (Note 2) 0.5 to V CC + 0.5 (Note 3) Input diode current I IK 20 ma Output diode current I OK ±20 (Note 4) ma DC output current I OUT ±25 ma DC V CC /ground current I CC ±75 ma Power dissipation P D 180 mw Storage temperature T stg 65 to 150 C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/ and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ( Handling Precautions / Derating Concept and Methods ) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: Output in off-state Note 3: High or low state. I OUT absolute maximum rating must be observed. Note 4: V OUT < GND, V OUT > V CC V Operating Ranges (Note 1) Characteristics Symbol Rating Unit Supply V CC 4.5 to 5.5 V Input V IN 0 to 5.5 V Output V OUT 0 to 5.5 (Note 2) 0 to V CC (Note 3) V Operating temperature T opr 40 to 85 C Input rise and fall time dt/dv 0 to 20 ns/v Note 1: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either V CC or GND. Note 2: Output in off-state Note 3: High or low state 3

Electrical Characteristics DC Characteristics Characteristics Symbol Test Condition Ta = 25 C Ta = 40 to 85 C V CC (V) Min Typ. Max Min Max Unit High-level input Low-level input V IH 4.5 to 5.5 2.0 2.0 V V IL 4.5 to 5.5 0.8 0.8 V High-level output V OH V IN I OH = 50 μa 4.5 4.40 4.50 4.40 = V IH or V IL I OH = 8 ma 4.5 3.94 3.80 V Low-level output V OL V IN I OL = 50 μa 4.5 0.0 0.10 0.10 = V IH or V IL I OL = 8 ma 4.5 0.36 0.44 V 3-state output off-state current I OZ V IN = V IH or V IL V OUT = V CC or GND 5.5 ±0.25 ±2.50 μa Input leakage current I IN V IN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 μa Quiescent supply current Output leakage current I CC V IN = V CC or GND 5.5 4.0 40.0 μa I CCT Per input: V IN = 3.4 V Other input: V CC or GND 5.5 1.35 1.50 ma I OPD V OUT = 5.5 V 0 +0.5 +5.0 μa AC Characteristics (input: t r = t f = 3 ns) Characteristics Symbol Ta = Test Condition Ta = 25 C 40 to 85 C V CC (V) C L (pf) Min Typ. Max Min Max Unit Propagation delay time (TC74VHCT540A) t plh t phl 5.0 ± 0.5 15 5.4 7.4 1.0 8.5 50 5.9 8.4 1.0 9.5 ns Propagation delay time (TC74VHCT541A) t plh t phl 5.0 ± 0.5 15 5.0 6.9 1.0 8.0 50 5.5 7.9 1.0 9.0 ns 3-state output enable time t pzl t pzh R L = 1 kω 5.0 ± 0.5 15 8.3 11.3 1.0 13.0 50 8.8 12.3 1.0 14.0 ns 3-state output disable time Output to output skew t plz t phz R L = 1 kω 5.0 ± 0.5 50 9.4 11.9 1.0 13.5 ns t oslh t oshl (Note 1) 5.0 ± 0.5 50 1.0 1.0 ns Input capacitance C IN 4 10 10 pf Output capacitance C OUT 9 pf Power dissipation capacitance C PD (Note 2) 19 pf Note 1: Parameter guaranteed by design. t oslh = t plhm t plhn, t oshl = t phlm t phln Note 2: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC (opr) = C PD V CC f IN + I CC / 8 (per bit) 4

Noise Characteristics (input: t r = t f = 3 ns) Characteristics Symbol Test Condition Ta = 25 C V CC (V) Typ. Limit Unit Quiet output maximum dynamic V OL V OLP C L = 50 pf 5.0 1.1 1.5 V Quiet output minimum dynamic V OL V OLV C L = 50 pf 5.0 1.1 1.5 V Minimum high level dynamic input Maximum low level dynamic input V IHD C L = 50 pf 5.0 2.0 V V ILD C L = 50 pf 5.0 0.8 V 5

Package Dimensions Weight: 0.22 g (typ.) 6

Package Dimensions Weight: 0.08 g (typ.) 7

Package Dimensions Weight: 0.03 g (typ.) 8

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