Redundant Bus Protection Using High-Impedance Relays Josh LaBlanc, Schweitzer Engineering Laboratories, Inc. (formerly of Minnesota Power) Michael Thompson, Schweitzer Engineering Laboratories, Inc. 2018 Minnesota Power and SEL onfiguration of the bus under study Redundancy options Introduction Methods of applying redundancy to a high-impedance bus-protection circuit Advantages and disadvantages 1
Z TX Bus 2 Single-Line Diagram Z Bus 1 TX Z Relay Failure learing Zone Relay Fails Z TX * * * All line ends open Transformer breakers open on overcurrent protection Bus 2 O Widespread outage is likely to cause other line overloads Z Bus 1 O Line Opens * TX Z * * * * * 2
Protection Redundancy haracteristics omplete redundancy includes Relaying schemes ontrol circuits T circuits Is complete redundancy feasible? T ircuits All breakers have an unused T Y circuit, though three different full-tap T ratios exist None of these Ts are wired into the control house T W T X Bus Line Protection #1 Line Protection #2 T Y Spare T T Z Bus Protection #1 Line 3
Other Redundancy Schemes High-impedance primary, percentage restrained differential secondary relaying High-impedance primary, high-impedance secondary relaying Percentage restrained differential (line T circuit) Zone interlock directional blocking High-Impedance Bus Application Z, B 86B 3 B T1 T2 T3 T 50 Operate Path
Primary Amperes Secondary Amperes Modes of Operation for Internal Fault 1. Upon fault inception, high voltage raises nearly instantaneously 2. Metal-oxide varistor clamps voltage to safe level 3. T saturates and shunts differential current through saturated T. At next zero crossing of waveform, process repeats itself urrent Waveform During Internal Faults Total Fault urrent in Primary ircuit Relay urrent A B A B A B A B 5
T Saturation for External Fault External Fault Z, B T1 T2 T3 T Saturated T Path Relay Voltage During Saturation R T123 I T123 I T + + + + R LEAD123 R LEAD R T T123 V T123 V JT V T T V+ Set point above V JT with margin 0 V T123 V JT V T V Improved security margin if V T is 50% expected instead of the 0% assumption 6
High-Impedance Relaying Redundancy onfigurations Series Parallel ly connected overcurrent backup Series onfiguration Z, B1 Z, B2 T1 T2 T3 T 50 50 7
Series onfiguration Details Relay sensitivity considerations Voltage pulse width is a function of T accuracy rating lamping voltage doubles causing earlier T saturation Voltage pulse width reduces by about half T insulation impact higher voltage impresses greater stress on circuit insulation Series ircuit lamping Voltage Z, B2 1,500 V T1 T2 T3 T Z, B2 1,500 V 8
Parallel onfiguration Z, B1 Z, B2 T1 T2 T3 T 50 50 Parallel onfiguration Details Relay sensitivity considerations clamping voltage Sensitivity Relay heating T insulation impact same as single relay application 3 / B switch requires make-before-break contacts 9
Parallel ircuit lamping Voltage Z, B1 Z, B2 T1 T2 T3 T 1,500 V ly onnected Overcurrent Z, B1 T1 T2 T3 T 50 50 / 51, B2 50 / 51 10
ly Overcurrent onfiguration Details T performance when Z element is shorted System acts as unrestrained differential overcurrent scheme T performance needs to be evaluated 3 / B switch status is used to disable sensitive functions Attenuation With In-Service The three stages of high-impedance relay performance attenuate the current signal Degree of attenuation is dependent on Maximum and minimum internal fault current levels Fault X/R ratio Fault point-on-wave or dc offset 11
Attenuation Example onclusion Z modes of operation Voltage / current attenuation Insulation impacts lamping voltage Settings considerations 12