Departmet of Electrical ad omputer Egieerig, orell Uiersity EE 350: Microelectroics Sprig 08 Homework 0 Due o April 6, 08 at 7:00 PM Suggested Readigs: a) Lecture otes Importat Notes: ) MAKE SURE THAT YOU INDIATE THE UNITS ASSOIATED WITH YOUR NUMERIAL ANSWERS. OTHERWISE NO POINTS WILL BE AWARDED. ) Uless oted otherwise, always assume room temperature. 3) THIS HOMEWORK SET REQUIRES MATLAB OMPUTATION/PLOTTING. START EARLY. Problem 0.: (Frequecy performace of a cascode amplifier s a commo source amplifier) osider the followig cascode amplifier: W 0 m L 0.5 m DD TN ox 00 A 0.0 3.0 0.5 I r BIAS gd gs oc 4 ma 0 ff oxwl 30 ff 3 r r o o
Assume that BIAS ad BIAS hae bee adjusted such that the drai curret of the both the FETs is 4 ma. Suppose R s kω. Syopsis: A good oltage amplifiers eeds to hae a large iput resistace, a small output resistace, a large gai, ad a large gai badwidth (i.e. the badwidth oer which the gai is flat ad at the D alue is large). A commo source amplifier has a large gai ad a large iput resistace, but suffers from the Miller effect which compromises the gai badwidth. A commo gate amplifier has a large gai, ad a large gai badwidth (because it does ot suffer from the Miller effect), but it has a small iput resistace. A casacade of the aboe two, i.e. a cascode, has a large iput resistace, a large gai, ad a large gai badwidth. The large gai badwidth of the cascode results from the fact that the first commo source stage i a cascode does t really produce too much gai (because it gets loaded with the small iput resistace of the secod commo gate stage) ad most of the gai comes from the secod commo gate stage. osequetly, the Miller effect preset i the first commo source stage is ot too damagig. These characteristics make the cascode a attractie stage for circuit desigers. I this problem you will explore this i detail. a) Draw a high-frequecy small sigal model of the cascode show aboe. b) At the bias poit, fid the (umerical) alues of g m ad g o for both the FETs (these should be idetical for the two FETs sice they are both biased with the same D curret). How big is g m compared to g o? c) Usig KL at the drai ed of M i the small sigal model, show that: out gm r o a jgd ro The aboe expressio is the ope circuit oltage gai of the secod commo gate stage. At low frequecies (~D), the aboe expressio gies the familiar ear-d ope circuit oltage gai of a commo gate amplifier: g m r oc r o. d) Plot 0 log out 0 (i.e. i db uits) o a log-frequecy scale from e6 Hz to e Hz. Note the 3dB a corer frequecy i Hz (ot rad/s). The matlab fuctio logspace will be useful whe makig the frequecy array for plottig. e) Usig KL at the drai ed of M i the small sigal model, show that: a gm jgd g m r g o o go gm j gd gs go jgd ro If the iput impedace lookig ito M from the source ed were assumed to be ifiite, the aboe expressio would reduce to,
a gm jgd go j gd which is the just the ope circuit oltage gai of a commo source amplifier with a low frequecy alue equal to g m ro. Howeer, the iput impedace of the commo gate amplifier is ot ifiite ad is i fact ery small. After makig suitable approximatios, the aboe expressio simplifies to, a gm jgd g m r g o m j gd gs go jgd ro The ear-d alue of the aboe expressio is, a gm r oc R A i g m r o Rout Ri r A oc gm ro Rout ro Ri gm ro a i at ear-d is of the order of uity. What the aboe aalysis shows is that the first stage, the commo source stage, does ot really proide much gai at all. All the gai comes from the secod stage, the commo gate stage. The first stage does ot proide much gai because it is loaded with the small iput resistace of the secod stage. Ad so the loaded oltage gai of the first stage (ot the ope circuit oltage gai) is pretty small, ear uity! Now here comes the puch lie: sice the first commo source stage does ot really proide much gai, the Miller effect does ot make the gate-to-drai capacitace of the first stage look terribly big ad therefore the Miller effect does ot destroy the high frequecy performace of the first commo source stage! f) Plot 0 log a 0 (i.e. i db uits) o a log-frequecy scale from e6 Hz to e Hz. Note the 3dB corer frequecy. g) Do a KL at the gate of M, used preiously obtaied results, ad show that, s j gs gd Rs jgdr s g m j gm jgd gs o jgd ro g m r g o gd h) Plot 0 log i 0 s corer frequecy. (i.e. i db uits) o a log-frequecy scale from e6 Hz to e Hz. Note the 3dB i) Based o the results i part (d) ad (f) ad (h), which stage, first or secod or the iput part, limits the oerall frequecy badwidth of the amplifier? 3
j) Now usig your results from parts (c), (e), amd (g), Plot 0 log out 0 (i.e. i db uits) o a logfrequecy scale from e6 Hz to e Hz. Note the 3dB corer s frequecy. k) If you ow just cosider a simple commo source amplifier (assume that the FET M is replaced by a wire) the from the lecture otes (without makig approximatios): a gm jgd go goc j gd s gm jgd j gs gdr s jgdr s go goc j gd Plot 0 log a 0 (i.e. i db uits) o a log-frequecy scale from e6 Hz to e Hz. Note the 3dB s corer frequecy. ompare the plot to your aswer i part (j) for the cascode amplifier. You should see that the cascode does better i terms of the frequecy badwidth while proidig at the same time few db larger ear-d gai. l) There is still a problem with usig the cascode as a oltage amplifier; it has a large output resistace. This ca be fixed by usig a commo drai stage as the fial output stage. Do you thik that addig a commo drai stage would sigificatly spoil the frequecy performace of the oerall amplifier? Why or why ot? Does a commo drai stage suffer from the Miller effect? Problem 0.: (RF Amplifier/Filter i oe) May MOS RF receig modules i wireless systems use a RF bad-pass filter ad a amplifier combiatio before demodulatig or mixig dow the RF sigal. Ofte the filtratio ad amplificatio pesses ca be combied i a sigle stage. Oe such MOS stage is show i the figure below ad has bee implemeted i the 00 m MOS techology. The 00 m refers to the FET chael legth. I its simplest form, the S stage is loaded with a L circuit. Placig a iductor i a MOS chip is ot a easy task but ca be doe. The figure below also shows the micrograph of a MOS GSM receier chip with two itegrated spiral iductors. You will eed to figure out the frequecy respose of the circuit. The operatio of the circuit is as follows: We kow that the resistace of the load sittig o top of the FET determies the gai of a S stage. If a simple resistor is replaced by a L circuit the the impedace of the L circuit will be frequecy depedet ad therefore the S stage gai ca also be made frequecy depedet. At low frequecies we expect the iductor to act like a short ad therefore the amplifier gai will be ery small. At high frequecies we expect the capacitor to act like a short ad therefore the gai will agai be ery small. At some itermediate frequecy the gai will be maximum ad this maximum gai will occur i a ery arrow bad of frequecies. Oe ca choose alues for L ad so that the maximum gai occurs at aroud ~ GHz (which is close to the carrier frequecy used by mobile systems, e.g. GSM). 4
Suppose: W DD L 8 ox.04 00 A 3.5 gs 0.5 ff L 5 H BIAS R.5 S 0 k? pf TN gd 0.fF 0.5 a) What ought to be the alue of the capacitor so that the maximum gai occurs at ~ GHz? b) What is the impedace Z() of the load sittig o top of the FET? c) Draw a small sigal model of the circuit. Use the high frequecy small sigal model for the FET. Represet the L load by its impedace Z(). d) Fid the small sigal oltage gai of the amplifier: A out s The best way to do it is to first fid: out i ad the fid: i s ad the multiply the two. e) Plot the gai (i db uits: i.e. 0 log0 A ) as a fuctio of frequecy from 0 MHz to 00 GHz. Use matlab or your faorite plottig program. f) What is the maximum gai (i db uits) you see i your plot i part (e)? g) What is the full width half max (FWHM) gai badwidth you see i your plot i part (e)? FWHM gai badwidth is the rage of frequecies (i Hz) oer which the gai (i db) is larger tha the peak gai alue (i db) mius 3 db. I other words, FWHM gai badwidth is the rage of frequecies oer which the square magitude of the gai is more tha oe-half of the peak gai alue. 5
h) Derie a aalytic expressio for the FWHM gai badwidth ad show that it matches what you see i your plot. Hit: usig ope circuit time costat techique determie the effectie resistace associated with the L circuit. i) A simple iductor loaded S stage ca also perform well at high frequecies compared to a resistiely loaded S stage i terms of gai ad output oltage swig. Suppose i the problem, the L circuit is replaced by just a iductor of iductace 5 H. Fid the small sigal oltage gai of the amplifier: A out s Plot the gai (i db uits: i.e. 0 log0 A ) as a fuctio of frequecy from 0 MHz to 00 GHz. Use matlab or your faorite plottig program. You will ote that there is o badpass filterig but the gai still peaks aroud 5-6 GHz ad is pretty large. You could ot hae easily obtaied such a large gai at such high frequecies usig a stadard resistie load. Problem 0.3: (Folded ascode Differetial Amplifier) osider the followig folded cascode differetial amplifier. Use the low-frequecy circuit models for this problem. The FETs M ad M, M3 ad M4, ad M5 ad M6 are matched pairs. The output resistaces of sources I BIAS are assumed to be ifiity (for coeiece). Assume appropriate D biasig such that the currets i the two legs of the first stage are idetical, ad the currets i the two legs of the secod stage are also idetical. a) Fid the differetial mode gai Ad of the amplifier assumig a differetial small sigal iput. b) Fid the short circuit output curret (i.e. curret flowig i the output whe the output is shorted to the groud) assumig a differetial small sigal iput. c) Fid the output resistace of the amplifier. 6