ol., Issue., Mr-Apr pp-89-87 I: 49-6645 Perfornce of yetricl nd Asyetricl Multilevel Inverters K. Lkshi Gnesh, U. Chndr Ro, (eprtent of Electricl nd Electronics Engineering, ri svi Engineering College, Indi Abstrct: istributed Energy Resources (ER) re systes tht produce electricl power t the site where the power is needed. If only electricl power is used then the technology is clled istributed Genertion (G). The objective of this pper is to study novel ore thn five level ultistring inverter topology for ERs bsed C/AC conversion syste. The distributed energy resource bsed single-phse inverter is usully dopted in the icrogrid syste. In order to reduce the conversion losses, the key is to sving costs nd size by reoving ny kind of trnsforer s well s reducing the power switches. In this study, high step-up converter is introduced s front-end stge to iprove the conversion efficiency of conventionl boost converters nd to stbilize the output C voltge of vrious ERs such s photovoltic for use with the siplified ultilevel inverter. In ddition, two ctive switches re operted under line frequency. In this project novel syetricl configurtion is proposed. The proposed syetricl configurtion uses less nuber of switches to get ore levels. It will reduce the cost, reduce the nuber of sources, coplexity, losses nd iproves relibility. The proposed converter is siulted by Mtlb/iulink softwre nd siultion results re presented. Key words: C/AC power conversion, ultilevel inverter, hronic nlysis nd Totl Hronic istortion (TH). I. ITROUCTIO The continuous econoic developent of ny countries nd the environentl issues (gs eissions nd the green house effect) observed in the lst decdes forced n intense reserch in renewble energy sources. istributed energy resources re sll, odulr, energy genertion nd storge technologies tht provide electric cpcity or energy where you need it. Typiclly producing less thn egwtts (MW) of power, ER systes cn usully be sized to eet your prticulr needs nd instlled on site. ER technologies include wind turbines, photo voltic (P), fuel cells, icro turbines, reciprocting engines, Hydro, cobustion turbines nd energy storge systes re the ost explored technologies due to their considerble dvntges [],[], such s relibility, resonble instlltion nd energy production costs, low environentl ipct, cpbility to support icro grid [3]. The renewble energy resources consists of photovoltic, fuel cells re generte the voltge re dc voltge. But I wnt the c voltge becuse of ostly used the lods re c lods. o we re convert the dc power to c powerprocessing interfce is required nd is Coercil, hoes, fctories nd utility grid stndrds [4],[7]. iffering converter topogrphies hve been cquired ERs estblish effectul power flow control perfornce of ERs. ER systes y be either connected to the locl electric power grid or isolted fro the grid in stnd-lone pplictions [7], []. The dc-dc converters re two types. They re without glvnic isoltion nd with glvnic isoltion (high frequency trnsforer).the with glvnic isoltion converter (high power pplictions) re used corresponding to size, weight, expense reduces. o low nd ediu power pplictions without glvnic isoltion ens ke no use of trnsforers corresponding to reduces the size, weight expense [7], [8]. The next procedure the output voltge level increses of the inverter output then utoticlly hronic coponent of the output voltge of inverter reduces nd lso corresponding to sll size of filters re used siultneously the cost reduces. The differing ultilevel topogrphies re usully chrcterizing by strong reduction of switching power losses nd electrognetic interference (EMI) [6], [7], [8]. A new siplified single-phse ultistring five-level ultilevel inverter topogrphy of dc/c power conversion with uxiliry circuit proposed [8], [9]. This topogrphy re used, the nuber of switching devices nd output hronics re reduced. The TH of the ultistring five-level inverter is uch less thn the conventionl ultistring three-level inverter becuse of dditionl uxiliry circuit hs high switching losses [9]. The objective of this pper is to study newly constructed trnsforerless five level ultistring inverter topology for ER. In this letter foresid GZ-bsed inverter is reduced to ultistring ultilevel inverter topogrphy tht require only 6 ctive switches insted of existing cscded H-bridge ultilevel inverter hve eight switches[].multi string ultilevel inverter hve six ctive switches. They re iddle two switches re operted fundentl frequency nd reining four switches re operted switching frequency. A high efficiency dc-dc boost converter reduction of trnsforer nd device voltge nd current stresses with continuous input current lekge inductnce energy recovery, nd voiding the use of electrolytic cpcitor due to reduced ripple current[3]. Opertion of the syste configurtion of opertion is shown below. The perfornce of syetricl nd syetricl single phse ultilevel inverter with respect to hronics content nd nuber of switches nd input voltge source is C is siulted by MATLAB/iulink. A detiled hronic 89 P g e
ol., Issue., Mr-Apr pp-89-87 I: 49-6645 nlysis is done on the ultilevel inverter by considering up to 3 rd hronics for 7 levels to 3 levels opertion. II. YTEM COFIGURATIO OF OPERATIO PRICIPLE Fig. ifferent type of ERs re syste configurtion of Multistring Inverter The bove Fig. shows the ERs hve photovoltics or Fuel cell inverter re tken s [4].The individul dc/dc boost converter re connected to the photovoltic odules or Fuel cell. The bidirectionl (buck-boost) dc/dc converter is connected to the only for bttery storge. The individul dc/dc boost converter is connected to the ultistring inverter. These coon inverter for interfce with ll dc/dc converters of ERs [5]. The two odes of opertion bove Fig.. They re stndlone ode nd grid connected ode. In grid connected ode, the bttery storge energy is not connected to the grid. In stndlone opertion, the bttery storge energy is connected to the lod. Fig. ingle phse siplified ultistring five-level inverter topogrphy for high stepup converter fro ERs The bove Fig. shows ER odule- is connected to the high step up dc/dc converter nd ER odule- is connected to high step up dc/dc converter. These two converters re connected to their individul dc-bus cpcitor nd siplified ultilevel inverter. The resistive lod is connected output of the siplified ultilevel inverter fro ER through high step up dc/dc converter. The input sources of ERs re photovoltic or Fuel cells. The bsic circuit hve eight switches of cscded H-bridge Multilevel inverter (CHB) with phse shift crrier pulse width odultion schee re used. The siplified ultilevel inverter hve six switches then best erits of iproved output wvefors, reduced the filter size, low EMI nd TH [],[]. It should be noted tht, by using independent voltge regultion control of the individul high step-up converter, voltge blnce control for the two bus cpcitorsc bus, C bus cn be chieved norlly... High tep-up Converter tge In this study, High Efficiency Converter with Chrge Pup nd Coupled Inductor for Wide Input Photovoltic AC Module Applictions [3].This siplified ultilevel inverter cobines the behvior of three different converter topologies: boost, flybck nd chrge pup. The flybck spect of the topology llows the design to be optiized in ters of the trnsforer turns-rtio, llowing for uch higher voltge gins thn would be possible with boost converter. However, flybck converters re notoriously inefficient nd re very sensitive to lekge inductnce, which cn cuse undue voltge-stress on switches nd diodes. By using clpcircuit- identicl to the output of boost-converter-fter the in switch, uch of the efficiency issues cn be resolved nd the trnsforer design becoes less coplicted. Finlly, dding chrge-pup cpcitor cross the priry nd secondry windings of the trnsforers gives higher converter voltge-gin nd reduced pek current stress by llowing the current of the priry-windings to continuous. The equivlent circuit of the proposed converter is shown in Fig.3. The coupled inductor is odeled s gnetizing inductor L n idel trnsforer with turn s rtio of s : p prirylekge inductor LLk nd secondry lekge inductor L Lk. C c is the clp cpcitor, is the Active switch, is the output diode C pup is the chrge pup cpcitor. According to voltge-seconds blnce condition of the gnetizing inductor, the voltge of the priry winding cn be derived s () Where in v pri in represents ech the low-voltge dc energy input sources nd voltge of the secondry winding is v. v. pri () sec in P P iilr to tht of the boost converter, the voltge of the chrge-pup cpcitor C nd clp cpcitor C c cn be expressed s v C pup pup v. C (3) c in Hence, the voltge conversion rtio of the high step-up converter, ned input voltge to bus voltge rtio, cn be derived s [3]. in. P (4) 8 P g e
ol., Issue., Mr-Apr pp-89-87 I: 49-6645 Fig.3. Equivlent circuit of the high step-up boost converter. iplified Multilevel Inverter tge () Fig.4 Bsic Five-level inverter Circuitry of six switches The siplified ultilevel inverter is the conventionl circuit of five level inverter Fig.4 shows bove. A new single phse ultistring topogrphy, s new bsic circuitry in Fig.4.Referring to Fig., it is should ssued tht, in this configurtion, the two cpcitors in the cpcitive voltge divider re connected directly cross the dc bus nd ll switching cobintions re ctivted in n output cycle. The dynic voltge blnce between the two cpcitors is utoticlly controlled by the preceding high step-up converter stge. Then, we cn ssue s s s. This circuit hs six power switches copre the bsic circuit of cscded H-bridge hs eight power switches which drsticlly reduces the power circuit coplexity nd siplifies odultion circuit design nd ipleenttion. The phse disposition (P) pulse width odultion (PWM) control schee is introduced to generte switching signls nd to produce five output voltge levels:, s, s, s nd s This inverter topology uses two crrier signls nd one reference signl to generte the PWM signls for the switches the odultion strtegy nd its ipleented logic schee in Fig.5 () nd (b) re widely used lterntive for Phse disposition odultion. With the exception of n offset vlue equivlent to the crrier signl plitude. Two coprtors re used in this schee with identicl crrier signls tri nd tri toprovidehigh frequencyswitchingsignls for, b, nd. Another coprtor is used for zero-crossing detection to provide linefrequency switching signls for switches nd. For Fig.4 the switching function of the switch defined s follows. j =, j O j =, j OFF for j=,, 3 bj =, bj =, bj O bj OFF for j=,, 3 (b) Fig.5. Modultion strtegy ) Crrier/reference signls (b) odultion logic Tble-I iplified Five Level Inverter witching Cobintion b AB Tble-I lists switching cobintions tht generte the required five output levels. The corresponding opertion odes of the siplified ultilevel inverter stge re described clerly s follows. ) Mxiu positive output voltge ( ): Active switches, nd b re O. The voltge pplied to the LC output filter is. ) Hlf level positive output voltge ( ): The two switching cobintions re there. One switching cobintion 8 P g e
ol., Issue., Mr-Apr pp-89-87 I: 49-6645 is tht ctive switches, nd b re O, the other is ctive switches, nd re O. uring this operting stge, the voltge pplied to the LC output filter. 3) Zero Output, (): This output condition either one of the leg re left or right ll switches re O. The lod is shortcircuited, nd the voltge pplied to the lod terinls zero. 4) Hlf level negtive output voltge ( ): the two switching cobintions re there. One switching cobintion is such tht ctive switches, nd re O, the other switching is ctive switches, b nd. 5) Mxiu negtive output ( ): uring this stge, ctive switches, nd re O, nd the output voltge pplied to the LC output filter. In these circuit opertions, it cn be observed tht the open voltge stress of the ctive power switches, b, nd is equl to input voltge nd the in ctive switches nd re operted t the line frequency. Hence, the switching losses re reduced in the new topology nd the overll conversion efficiency is iproved. In Fig.5 control circuit digr s shown, t is the sinusoidl odultion signl. Both tri nd tri re two crrier signls. The gnitude vlue nd frequency of the sinusoidl odultion signl re given s =.7 nd pek f =6Hz. The pek to pek vlue of the tringulr odultion signls is equl to nd the switching frequency f tri nd f tri re both given s 8.6 khz. The two input voltge sources feeding fro the high step up converter is controlled t tht is. The five level output of the phse voltge s s of the siultion wvefor is shown in Fig.6..3 Bsic circuit of Cscded H-Bridge (CHB) Inverter Fig.7 Bsic circuit of five-level inverter topology of CHB inverter hve eight switches The bove figure shows the Bsic circuit of five level inverter CCHB inverter hve eight switches. The crrier bsed sinusoidl phse shift crrier pulse width odultions re used in the bsic circuit of CHB inverter. The eight switches re operted of the switching frequency. The CHB inverter re operte t the switching frequency is se s8.6khz the se odultion index =.7. The siplified ultilevel inverter nd Cscded H- bridge inverter re operted the se switching frequency nd se odultion index,the se input voltge = nd output L-C filter, L =H, C =uf, R-lod =Ohs. Tble II nd Tble III shows the hronic coponent nd TH Cscded H-Bridge Inverter nd iplified ultilevel inverter. The siplified ultilevel inverter hve the lesser TH copre to the Cscded H- bridge inverter. o the low vlues of LC filter. The syetricl ultilevel inverters re Cscded H-bridge inverter nd iplified ultilevel inverter. These re tken the equl voltge vlues. The syetricl ultilevel inverters bove re operted with PWM ethod. The Proposing ethods of syetricl ultilevel inverters re repeting sequence is used for even, ine, Eleven nd Thirteen levels. The seven level hve 6switches nd ine, Eleven nd Thirteen level hve 8 switches. The even, ine, Eleven nd Thirteen levels re get by using,6,,4 switches re necessity in syetricl configurtion of Cscded H-bridge inverter. o the less nuber of switches re in syetricl configurtion to get ore nuber of voltge levels, lesser the TH, low cost, reducing the C sources, reduce the coplexity nd driving circuits. Fig.6 iplified ultilevel five level output phse voltge of siultion wvefor AB 8 P g e
ol., Issue., Mr-Apr pp-89-87 I: 49-6645 III. PROPOE YTEM 3.even Level Multi Level Inverter (MLI) Tble- II even Level Multilevel Inverter (MLI) b 3 3 The bove Tble II is shows the ctive switches opertion of seven level, ens the switch is O, the ens the switch is OFF. Then we will get the seven level output voltge fro the six switches only. 3.ine Level Multi Level Inverter (MLI) Tble- III ine level Multilevel (MLI) 3 4 5 6 7 8 4 3 3 4 The bove Tble III is shows the ctive switches opertion of eight switches with nine level, ens the switch is O, the ens the switch is OFF. Then we will get the nine level output voltge fro the eight switches only. 3.3Eleven Level Multilevel inverter (MLI) Tble- I Eleven level ultilevel Inverter (MLI) 3 4 5 6 7 8 5 4 3 3 4 5 The bove Tble I is shows the ctive switches opertion of eight switches with eleven level, ens the switch is O, the ens the switch is OFF. Then we will get the eleven level output voltge fro the eight switches only. 3.4 Thirteen Level ulti Level inverter Tble- Thirteen level ulti level inverter (MLI) 3 4 5 6 7 8 5 4 3 6 3 4 5 6 83 P g e
ol., Issue., Mr-Apr pp-89-87 I: 49-6645 The bove Tble is shows the ctive switches opertion of eight switches with thirteen level, ens the switch is O, the ens the switch is OFF. Then we will get the thirteen level output voltge fro the eight switches only. 3.5ifferent voltges re tken s the source voltges of the syetricl ultilevel inverters TABLE I IFFEERET OLTAGE o of 3 Output oltge in witches 7 6 o of levels 9 8 8-3 4 5 3 8 3 6 The seven level output voltge re get only fro six switches only. The nine level, eleven level nd thirteen level output voltge re get only fro eight switches corresponding to respective voltge sources re tken. The bove tble I shows different voltges re tken for syetricl ultilevel inverters. The syetricl ultilevel inverters re siulted the output voltge re designed by using. The seven level output voltge re get by using =66.66, =33.33. The nine level output voltge re get by using =5, =5, 3=. The eleven level output voltge re get by using =4, =8, 3=8. The thirteen level output voltge re get by using =66.66, =99.99, 3=33.33. The syetricl ultilevel inverters re siulte the bove written voltge vlues. Fig. shows the output voltge with LC filter of CHB inverter of M.I=.7 Fig.shows the unity power fctor t the R-Lod with LC filter of CHB inverter of M.I=.7 I. MATLAB/IMULATIO REULT 4.Bsic circuit of Cscded H-Bridge five level Inverter Fig. shows the five level output voltge CHB inverter without LC of M.I=.8 Fig.8 shows the five level inverter CHB siulink circuit Fig.3 shows the output voltge with LC filter of CHB inverter of M.I=.8 Fig.9 shows the five level output voltge CHB inverter without LC of M.I=.7 84 P g e
ol., Issue., Mr-Apr pp-89-87 I: 49-6645 Fig.4 shows the unity power fctor t the R-Lod with LC filter of CHB inverter of M.I=.8 Tble-II Hronics of CHB Inverter with nd without LC The Tble II shows the CHB inverter operting two odultion indexes. They re.7 nd.8 without nd with LC filter. 4. iplified Five level Inverter Fig.8 shows the unity power fctor t the R-Lod with LC filter of siplified five level inverter of M.I=.7 Fig.5. The siulink of siplified five level ultilevel inverter Fig.9 shows the five level output voltge siplified five level inverter without LC of M.I=.8 Fig.6 shows the five level output voltge of siplified five level inverter without LC of M.I=.7 Hronics =.7 =.8 Fundentl 54. 83.84 h3.4 3.3 h5.9. h7.4.7 h9.5. h..9 %TH WITHOUT LC %TH WITH LC.46.4.5.3 Fig.7 shows the output voltge with LC filter of siplified five level inverter of M.I=.7 Fig. shows the output voltge with LC filter of siplified five level inverter of M.I=.8 Fig. shows the unity power fctor t the R-Lod with LC filter siplified five level inverter of M.I=.8 Tble-III Hronics of iplified Five Level Inverter with nd without LC Hronics =.7 =.8 Fundentl 57.77 85.66 h3.8.98 h5.5.7 h7.7.3 h9.6.6 h.7.5 %TH.7.684 WITHOUT LC %TH WITH LC.5.3 85 P g e
ol., Issue., Mr-Apr pp-89-87 I: 49-6645 The Tble III shows the siplified five level inverter operting two odultion indexes. They re.7 nd.8 without nd with LC filter. The odulting frequency (witching frequency) is 86Hz. The CHB five level inverter operted with =.7 nd =.8 with phse shift crrier pulse width odultion technique then I would get the fundentl coponent voltge increses nd TH vlue decreses when odultion index =.8 copre to the =.7.The siplified five level inverter operted the se odultion index with phse disposition pulse width odultion technique then I would get the fundentl coponent voltge increses nd TH vlue decreses copre to the CHB inverter. After clerly understnd reduce the nuber of switches, iproved output wvefors, sller filter size nd lower EMI of siplified ultistring five level inverter copred to the CHB inverter. 4.3 Proposing syste of even Level ultilevel inverter Fig.6 ine level ultilevel Inverter output voltge Fig.7 TH vlue of the nine level ultilevel inverter using FFT nlysis 4.4 Proposing yste of Eleven Level ultilevel inverter Fig.8 Eleven level ulitlevel Inverter output voltge Fig. iulink of the seven level ultilevel inverter Fig.3 even level ultivlevel Inverter output voltge Fig. 9 TH vlue of the eleven level ultilevel inverter using FFT nlysis 4.5Proposing yste of Thirteen Level ultilevel inverter Fig.4TH vlue of the even level ultilevel inverter using FFT nlysis Fig.3 Thirteen level ultilevel Inverter ouput voltge 4.4 Proposing yste of ine Level ultilevel inverter Fig.5.iulink of the nine, eleven nd thirteen level ultilevel inverter Fig.3 TH vlue of the thirteen level ultilevel inverter using FFT nlysis 86 P g e
ol., Issue., Mr-Apr pp-89-87 I: 49-6645 Tble-IX Fundentl Coponent nd TH vlue of the Multilevel inverter of rious lues Mgnitude of o of Levels individul Hronic content 7 9 3 Fundentl 8.5 8.9 77.34 75.34 h3 7.99 7.93 7.68 8.8 h5 9. 5. 5.43 5.79 h7 3.45.9 3..66 h9 3.7.5.3. h.68.4.4.83 h3.3.9.79.7 h5.59 4..73.4 h7.8.6.8.79 h9.3 9.78 3.55. h.86.7 7.7.69 h3.46.6 7.3.97 (%TH).36 % 4.9% 3.83% 3.33% Tble-X oinnt Hronics in rious Multilevel inverters rious oinnt Hronics Multilevel Inverter even Level,,, ine Level,,, Eleven Level,,,, Thirteen Level,. COCLUIO This work reports Perfornce nlysis of syetricl nd syetricl ultilevel inverters, so reduce the nuber of switching devices, reduce the nuber of C sources, driving circuits nd cost reduces nd lso TH decreses. Multistring ultilevel inverters hve low stress, high conversion efficiency nd cn lso be esily interfced with renewble energy sources (P, Fuel cell). Asyetricl ultilevel inverter uses lest nuber of devices to produce higher voltge level. As nuber of level increses, the TH content pproches to sll vlue s expected. Thus it eliintes the need for filter. Though, TH decreses with increse in nuber of levels, soe lower or higher hronic contents rein doinnt in ech level. These will be ore dngerous in induction drives. Hence the future work y be focused to deterine the pw techniques of seven to thirteen level syetricl ultilevel inverters. REFERECE [] Key world energy sttistics-9,interntionl Energy Agency(IEA),9.Avilble t:http://www.ie.org. [] F. Kininger, Photovoltic systes technology. Kssel, Gerny: Universitt Kssel, Institute for Rtionelle Energiewndlung, 3. Avilble t:www.uni-kssel.de/re. [3] M. Liserre. T.uter. J.Y. Hung, Future energy systes: integrting renewble energy sources into the srt power grid through industril electronics, IEEE Industril Electronics Mgzine, vol.4,no.,pp.8-37,mr.. [4] C. L. Chen, Y. Wng, J..Li, Y.. Lee nd. Mrtin, esign of prllel inverters for sooth ode trnsfer icrogrid pplictions, IEEE Trns.Power Electronics, ol. 5, no., pp.6-6, Jn. [5] F. Blbjerg, Z. Chen nd. B. Kjer, Power electronics s efficient interfce in dispersed power genertion systes, IEEE Trns. Power Electronics, vol. 9, no.5, pp.84-94, ep.4. [6]. G. Infield, P. Onions, A.. ions nd G. A. ith, Power qulity fro ultiple grid-connected single-phse inverters, IEEE Trns. Power elivery, vol. 9, no.4, PP. 983-989, Oct. 4. [7] T. Kerkes. R. Teoderescu nd U. Borup. Trnsforerless photovoltic inverters connected to the grid, IEEE Applied Power Electronics Conference. 7 PP.733-737. [8] G.Cegli.Guzn, C.nchez, F.Ibnez, J. Wlter, nd M. I. Gienez A new siplified ultilevel inverter topology for C-AC conversion, IEEE Trns. Power Electronics, vol., n.5, pp.3-39, ep.6. [9].A. Rhi nd J. elvrj, Multistring five-level inverter with novel PWM control schee for P ppliction, IEEE Trns. Power Electronics, vol.57 no.6 pp. -3, Jun.. []. zquez, J.I.Leon, J.M.Crrsco, L.G. Frnquelo, E. Glvn, M. Reyes, J.A. nchez, nd E. oinguez, Anlysis of the power blnce in the cells of ultilevel Cscded H-bridge converter, IEEE Trns. Industril Electronics, vol.57, no.7, PP.87-96, Jul.. []. Kouro, J. Rebolledo, nd J.Rodriguez, Reduced switching-frequency odultion lgorith for high-power ultilevel inverter, IEEE Trns. Industril Electronics, vol.54, no.5, PP.894-9, Oct.7. [] Y. Liu, H.Hong, nd A. Q. Hung, Rel-tie clcultion of switching ngles iniizing TH for ultilevel inverters with step odultion, IEEE Trns. Industril Electronics, vol. 56, no., pp.85-93, FEB.9. [3] W.Yu. C. Hutchens, J..Li, J. Zhng, G.Lisi, A. jbbri, G.ith, nd T. Hegrty, High Efficiency Converter with Chrge Pup nd Coupled Inductor for Wide Input Photovoltic AC Module Applictions, IEEE Energy Conversion Congress nd Exposition, PP.3895-39, 9. [4]. her, J.chid nd F.L.M. Antunes, Multilevel inverter topologies for tnd-lone P systes, IEEE Trns. Industril Electronics, ol.55, no.7, PP.73-7, Jul.8 [5] M. Meinhrdt nd G.Crer, Pst, present nd future of grid-connected photovoltic nd hybrid-power systes, IEEE-PE uer Meeting, PP.83-88, 87 P g e