Glvnic Isoltion System for Multiple Gte Drivers with Inductive Power Trnsfer Drive of Three-phse inverter Keisuke Kusk, Mskzu Kto Dept. of Energy nd Environment Science Ngok University of Technology Ngok, Niigt, Jpn kusk@stn.ngokut.c.jp, ktom@stn.ngokut.c.jp Koji Orikw, Jun-ichi Itoh Dept. of Science of Technology Innovtion Ngok University of Technology Ngok, Niigt, Jpn orikw@vos.ngokut.c.jp, itoh@vos.ngokut.c.jp Ismu Hsegw, Kzunori Morit, Tkeshi Kondo Reserch & Development Group MEIDENSHA CORPORATION Numzu, Shizuok, Jpn Abstrct Medium-voltge motor drive systems, mediumvoltge inverters, which hve n input voltge nd n output voltge of 3.3 kv or 6.6 kv, re widely used in industry pplictions. In the medium-voltge inverter, robust glvnic isoltion mong control circuit nd ech gte drive supplies is required in order to drive high-voltge switching devices. In present, trnsformer, which is designed to stisfy the sfety stndrds, provides glvnic isoltion. However, trnsformers prevent cost reduction of the isoltion system. In this pper, the glvnic isoltion system using only printed circuit bords re proposed. Moreover, three-phse inverter is driven using the isoltion system in order to confirm the utility of the isoltion system. The proposed system trnsmits power from the trnsmitting bord to six receiving bords using ech trnsmitting coils mde on the printed circuit bords. The ir gp mong the printed circuit bords ssumes glvnic isoltion. From the experimentl results, it is confirmed tht the threephse inverter cn be driven by the proposed glvnic isoltion system. Keywords inductive power trnsfer; wireless power trnsfer; gte driver; mediium-voltge inverter I. INTRODUCTION Medium-voltge motors, which hve rted voltge of 3.3 kv or 6.6 kv, re widely used for high-power pplictions such s fns nd blowers in industry []. For medium-voltge motors, system voltge of three-phse medium voltge inverter hs lso risen to 3.3 kv or 6.6 kv [-4]. In such medium-voltge inverter, robust glvnic isoltion is required mong control circuit nd ech gte driver supply. The stndrds of glvnic isoltion for djustble speed electricl power drive systems [5], which re published by the Interntionl Electrotechnicl Commission (IEC), re wellknown sfety regultions. When the working voltge of the inverter is 8. kv, the sfety stndrds require minimum clernce of 4 mm nd creepge distnce of 8 mm with following conditions; comprtive trcking index (CTI) is CTI < 4 with pollution degree of [5]. In the conventionl system, glvnic isoltion is chieved by isoltion trnsformers with cores. However, they tend to drive up cost of the isoltion system becuse severe mlfunction in the medium-voltge system hs to be voided. Moreover, the trnsformers re typiclly hevy nd bulky in order to obtin the high-voltge isoltion. For exmple, the typicl dimensions of the isoltion trnsformer, which hs n isoltion voltge of kv rms for s, re mm mm mm t weight of pproximtely 5.5 kg [6]. These trnsformers re required t ech the gte driver supplies. Thus, the downsizing nd cost reduction of the glvnic isoltion system hve been difficult to chieve. In order to chieve cost reduction nd downsizing of the isoltion system for power converters, single-chip DCisolted gte drive integrted circuit (IC) hs been proposed [7-9]. It supplies power using microwve from the bottom lyer of spphire substrte to the top lyer. A trnsmission frequency of the system is 5 GHz. The glvnic isoltion is ssumed by spphire substrtes. Thus, it chieves the downsizing of the isoltion. However, the sfety stndrds on creepge distnce re not stisfied. It mens tht it cnnot be used for the medium-voltge inverter. In [-], opticl isoltion method using opticl fibers hve been proposed. Gte signl nd power is supplied through the opticl fiber. However, the trnsmitted power is limited up to mw per one fiber. The power is not sufficient to drive gte drive circuit nd uxiliry circuit such s protection circuit of switching devices. Furthermore, if opticl fibers re repetedly bent, it increses the risk of disconnection of wire. Menwhile, n isoltion system using printed circuit bords (PCBs) hs been proposed by J. W. Kolr et l [6]. The power is supplied from the coil mounted on trnsmitting bord to the coil mounted on receiving bord. It is similr principle of coreless trnsformer [3]. However, one trnsmitting side trnsmits power to only one receiving side s one-by-one ( ) in this system. Mny pirs of the trnsmitting bord nd the receiving bord re required t ech of gte driver supplies. 978--4673-75-3/5/$3. 5 IEEE
In this pper, the glvnic isoltion system, which is constructed by only PCBs, is proposed. Then, the three-phse inverter with the proposed isoltion system is experimentlly tested in order to confirm the utility of the isoltion system. The isoltion system trnsmits power from one trnsmitting bord to six receiving bords ( 6) beyond n ir gp of 5 mm by inductive power trnsfer. The isoltion system contributes cost reduction of the isoltion system. Besides, the isoltion with the ir gp of 5 mm esily stisfies the stndrd of the clernce nd creepge distnce when the system voltge of the inverter is 6.6 kv. Moreover, the ir gp of 5 mm decreses common-mode current, which is induced by high-dv/dt switching of the medium voltge inverter. This effectively increses the relibility becuse common-mode current my cuse mlfunctions in the gte drive circuit nd the control circuit [4]. First, the system configurtion of the proposed isoltion system is described from next chpter. Then, the design method of the resonnce cpcitors for multiple receiver system is mthemticlly clrified. Thirdly, the fundmentl chrcteristics of the proposed system with resistnce lod re provided. Finlly, three-phse inverter is driven with the proposed system in order to confirm the utility of the proposed system. 4V Proposed glvnic isoltion system Glvnic isoltion Receiving bords # Trnsmitting bord # C vinv C fsw = MHz L vin Inductive power trnsfer Fig.. Concept of glvnic isoltion system. 5 5 3 mm vdc Receiving bords Medium-voltge inverter Gte driver # 6.6 kv II. PROPOSED GALVANIC ISOLATION SYSTEM A. System Configurtion Figure shows the concept of the proposed glvnic isoltion system. The proposed system consists of the seven PCBs; one trnsmitting bord nd six receiving bords, nd chssis mde from crylic. The trnsmitting bord is connected to the uxiliry power supply of 4 V in the medium-voltge inverter. On the other hnd, the receiving bords re connected to the gte drivers. The trnsmitting bords supply power to the six receiving bords with the inductive power trnsfer beyond the ir gp. Power fctor from the view point of the power supply decreses with decresing mgnetic coupling between the trnsmitting bord nd the receiving bords. In order to cncel out the rectnce of the lekge inductnce, resonnce cpcitors re inserted into the trnsmitting coil nd the receiving coils in series. This technique is commonly used in the inductive power trnsfer system. In prticulr, technique for inserting cpcitors in series into both trnsmitting coil nd receiving coil is known s the S/S compenstion [5-8]. Using the S/S compenstion, the power is effectively trnsmitted by the inductive power trnsfer even t wek mgnetic coupling. Figure shows the schemtic view of the propose isoltion system. The overll size is 3 5 5 mm. The trnsmitting bord nd the receiving bords re plced in the chssis mde from crylic. Distnce between ech the receiving bords nd the trnsmitting bord is kept t 5 mm for glvnic isoltion. This ir gp meets definition of the creepge distnce nd the clernce. The glvnic isoltion to stisfy the sfety stndrds is chieved by the ir gp. The ir gp is wide enough to fulfill the sfety stndrds of the IEC [5] when the system voltge of medium-voltge inverter is 6.6 5 5 9 5 Trnsmitting bord # #4 #5 5 5 5 Fig.. Schemtic view of proposed isoltion system. Unit: [mm] kv. Note tht this 5-mm n ir gp is designed with sufficient mrgin. Furthermore, this configurtion is effective to improve the relibility. A mlfunction my be cused by the lekge current, which is induced by high dv/dt switching of switching devices [4]. The proposed isoltion system reduces the prsitic cpcitnces between the trnsmitting bord nd the receiving bords. The lekge current, which flows to the controller of the medium-voltge inverter, will be suppressed. The prsitic cpcitnces between the trnsmitting bord nd the receiving bords re corresponded to prsitic cpcitnces between primry winding in trnsformer. Figure 3 nd 4 show the schemtics of the trnsmitting bord nd the receiving bord, respectively. The trnsmitting bord # consists of high-frequency inverter, series resonnce cpcitor, nd trnsmitting coil. The inverter is operted by squre wve opertion with n output frequency of MHz. On the other hnd, the receiving bords # 6 consist of receiving coils, series resonnce cpcitors, the diode bridge rectifiers. As the diodes, silicon-crbide (SiC) schottky brrier diodes re used for high-frequency opertion. The thickness of the copper film nd PCB for both bords is 75 m nd.6
mm, respectively. Besides, the cpcitors re inserted to the coils in series to cncel out the rectnce from the view point of the power supply. This technique is well-known s seriesseries compenstion (S/S) in reserch field of wireless power trnsfer. The resonnce conditions re described below. 43.5 8.6 9.5 3 45 3 R B. Required Rted Power of Gte Driver Supplies The isoltion system trnsmits the power consumption for the gte drivers. In this subsection, the required power of the ech gte driver is estimted. 5 Control circuit Inverter Gte drive circuits Cpcitors C.. Unit: [mm] Figure 5 shows the five-level diode-clmped multilevel inverter s the medium voltge inverter, which hs rted output voltge of 6.6 kv nd rted output power of MVA []. Ech switching device is string of three.7-kv IGBTs connected in series. The power consumption of gte resistnce P G of n IGBT is clculted by () where f c is crrier frequency, Q g is totl gte chrge nd V GE re gteemitter voltge of IGBT. 5 Inverter P f Q Q V V G c g From eq. (), the power consumption of ech gte drive circuit is clculted s bout 4 mw where the switching frequency of the medium voltge inverter is 4 khz, totl gte chrges ±Q g re ± nc nd the gte-emitter voltge is ±5 V. Note tht the vlues, which is used in this clcultion, re typicl vlue of IGBT (V CE = 7 V, I C = 5A). Considering power loss in gte driver circuit nd power consumption except the gte resistnce, the power of t lest W is required per one receiving bord s the output power of the isoltion system. C. Evlution of Prsitic Cpcitnce The prsitic cpcitnce between the trnsmitting bord nd the receiving bords is evluted. The prsitic cpcitnces between the trnsmitting bord nd the receiving bords should be suppressed becuse prsitic cpcitnces reduce the isoltion performnce. The prsitic cpcitnces mong the bords correspond to the cpcitnce between primry winding nd secondry winding in the conventionl isoltion trnsformer. In prticulr, considering use of SiC- MOSFETs for medium-voltge inverter, suppression of the prsitic cpcitnce is strongly required. The reson is tht SiC-MOSFET will improve the switching speed due to its high electronic mobility [9]. However, the lrge common-mode current is induced by high dv/dt. In order to prevent the medium-voltge inverter from mlfunction, the common-mode current hs to be suppressed. The prsitic cpcitnce is clculted using simplified model. It is difficult to clculte the exct prsitic cpcitnce becuse the shpes of the conductors on the trnsmitting bord nd the receiving bords re complicted. The prsitic cpcitnce is evluted in the worst-cse ssumptions. The spce between the trnsmitting bord nd the receiving bords is ssumed s prllel-plte cpcitor. The cpcitnce of prllel plte cpcitor with ir is clculted by (), where ir g GE GE Fig. 3. Schemtics of trnsmitting bord. (Top view) 9 45.5 9.5 Cpcitors 5 45 3 R Rectifier.5.5 Fig. 4. Schemtic of receiving bord. (Top view) 6.6kV Five-level PWM rectifier Rectifier PWM inverter Unit: [mm] 6.6kV M Fig. 5. Configurtion exmple of 6.6-kV, -MVA five-level diodeclmped medium voltge inverter.
is the permittivity of ir, S is the re of the prllel plte, nd d is the distnce between the bords. S C ir d Let S be 9 mm 5 mm nd d be 5 mm s the dimensions of the system; then, the prsitic cpcitnce C of the isoltion system is below.8 pf for the worst-cse ssumptions. This shows tht the proposed isoltion system decreses the prsitic cpcitnce in comprison with the conventionl isoltion systems with trnsformer [-]. III. DESIGN OF RESONANCE CAPACITORS The design of resonnce cpcitors re discussed in this section. First, n equivlent circuit of the proposed isoltion system is introduced. Then the vlidity of the equivlent circuit model is clrified by comprison of the F-mtrix between the equivlent circuit model nd 3-D electromgnetic nlysis. A. Derivtion of Equivlnet Circuit The equivlent circuit with multiple receiving coils is provided in []. The equivlent circuit of the proposed system is derived by chnging the equivlent circuit in []. In [], the mgnetic coupling mong the receiving coils is ssumed. However, the mgnetic coupling mong the receiving coils cn be ignored in the proposed system due to the positionl reltionship of the receiving bords. Figure 6 shows the equivlent circuit of the proposed isoltion system without converters where L 6 re the selfinductnces of ech coil, k ij is the coupling coefficient between bords #i nd #j, N 6 re the numbers of turns, r 6 re the equivlent series resistnces, nd is the turn rtio defined s N 6 / N. B. Evlution fo the Equivlent Circuit In order to evlute the vlidity of the equivlent circuit, the F-mtrix of the frequency chrcteristic (which is defined by Eq. ()) nlyzed by 3-D electromgnetic nlysis (Agilent, Momentum) is compred with the F-mtrix clculted by the equivlent circuit. The F-mtrix shows the reltionship of system between the input port #i nd output port #j bsed on voltge nd current. The suffixes I nd j indicte the number of PCBs( i, j =,,, 6). For simplicity, the F-prmeter from one bord #i to nother bord #j is indicted s F(i, j). V V Aij B j ij V i j F i, j I I C i j ij Dij I j Figure 7 shows the definitions of the F-prmeters in the proposed system. In this evlution, only the chrcteristics of the coils re evluted. Thus, the resonnce cpcitors re omitted becuse the evlution of the equivlent circuit of the trnsmission coils is the min purpose of this section. V I C r L k kl L r Trnsmitting bord # L (- k n) n=,,, 6 L k L k 3 L k 4 L k 5 L k 6 N :N -6 k k k 3 k 4 k 5 k 6 Idel trnsformer kl L k3l L3 k4l L4 k5l L5 k6l L6 Fig. 6. Equivlent circuit of proposed isoltion system. Trnsmitting bord # 5W F(,) Coil F(,) F(,) F(3,) F(4,) F(5,) F(6,) Fig. 7. Definition of F-prmeters. F(,) F(,) F(,3) F(,4) F(,5) F(,6) r r 3 r 4 r 5 r 6 Coil C C C 3 C 4 C 5 C 6 F(,) I V I V I 3 V 3 I 4 V 4 I 5 V 5 I 6 V 6 Receiving bord F(,) #4 #5 Receiving bord # #4 #5 5W # F(,) The idel power supply with resistnces of 5 Wfor the inner impednce is connected insted of the converters. The inner impednce is necessry becuse the F-prmeters re clculted from the nlysis results of scttering prmeters (Sprmeters) by simultor. Figure 8 shows ech of the F-prmeters between the trnsmitting bord nd receiving bord #. The solid line shows the F-prmeter nlyzed from 3-D electromgnetic nlysis. The dshed-dotted line shows the F-prmeter clculted from the equivlent circuit. The dotted line shows the F-prmeter clculted from the equivlent circuit with correction coefficients, which re mentioned lter. The F- prmeter with the 3-D electromgnetic nlysis hs selfresonnce t frequency of pproximtely 7 MHz. However, the equivlent circuit model does not consider self-resonnce becuse the self-resonnce frequency is fr from the operting frequency. This is one of the resons for the error between 3 MHz nd MHz. Moreover, the F-prmeter with the equivlent circuit hs offsets of pproximtely db between khz nd 3 MHz. The reson for the error is the difference between the numbers of the ctul windings nd effective windings. This mens tht
portion of the windings is not effective to induce the voltge. This is specific problem when trnsmitting coil is plced on PCBs. The difference cn be corrected using correction coefficient. The corrected turn-rtio of the trnsformer is represented s Eq. (4) using the correction coefficient. The dotted line shows the F-prmeter with the equivlent circuit considering the correction coefficient in Fig. 8. The correction coefficients, which re derived by tril nd error, re 6 =.6,.8,.7,.6,.8, nd.7, respectively, in the prototype. The difference in the correction coefficients is cused by the difference in the positions of the receiving bords. The correction coefficients re necessry in timedomin nlysis in order to exctly nlyze the circuit performnce. N N The F-prmeter of the equivlent circuit considering the correction coefficient shows greement with one of the electromgnetic nlyses between khz nd 3 MHz. C. Design of Resonnce Cpcitors Figure 9 shows the equivlent circuit of the proposed system with the converters. In the following clcultion, the rectifiers re ssumed s lod resistnces R 6. The resonnce cpcitors should be designed to cncel out the rectnce owing to the lekge inductnce [8]. From the equivlent circuit, the output current of the inverter is expressed s Eq. (5) using expressed s (6) when ll of the prmeters on the receiving bords nd the coupling coefficients re the sme. The prime prmeters re the prmeters referred to the primry side. V I inv r R inv r j L le 6L m C j L le L 6 L m r R j Lle L m m 6 C r R j L le L 5 C m 6 C In order to correct the lod power fctor, rectnce of the eq. (5) hs to be zero. Thus, the resonnce conditions re derived s (5) nd (6) where = f is the output ngulr frequency. From Eq. (5) nd (6), the resonnce conditions re provided s Eq. (7) nd Eq. (8). F-prmeters [db] TABLE I. SPECIFICATIONS OF PROTOTYPE Input voltge (DC) VDC 4 V Switching frequency fsw. MHz Self-inducnces Equivlent series resistnces cpcitnces Coupling coefficients (between the receiving coils nd trnsmitting coil) 8 4-4 C 6 L 6 6 le Lm L 6 B A D C Trnsmitting coil L.3 H Receiving coils L-6 4.8 H Trnsmitting coil R 79 mw Receiving coils R-6 69 mw Trnsmitting bord # C 3 pf Receiving bords #-6 C-6 43 pf Receiving bord # k.7 Receiving bord k.5 Receiving bord k3.8 Receiving bord #4 k4.7 Receiving bord #5 k5.5 Receiving bord k6.7 3-D model (Agilent momentum) Equivlent circuit without correction coefficient Equivlent circuit with correction coefficient Frequency f [MHz] Self resonnce -8. Fig. 8. F-mtrix between trnsmitting bord # nd receiving bord #. Gte drivers for high-frequency inverter Receiving bord # Trnsmitting bord # The equtions show tht the resonnce cpcitors should be resonted with ech self-inductnce. Rectifier C Lle Lm Lm Lm6 L #4 Trnsmitting coil #5 High-frequency Inverter Receiving coil Fig. 9. Prototype of isoltion system.
IV. EXPERIMENTAL VERIFICATIONS A. System setup of the prototype Figure 9 shows the photogrph of the prototype. The trnsmitting bord, which is shown in Fig. 3, nd the receiving bords, which re shown in Fig. 4, re plced s shown in Fig.. The chssis is mde from crylic except for clinchers becuse eddy current losses should be suppressed. Tble I shows the specifictions of the prototype. The lminted cermic cpcitors for resonnce re selected to stisfy the resonnce conditions shown s (7) nd (8). Note tht the coupling coefficients between the bords re simulted vlues becuse it is difficult to mesure the ccurte coupling coefficient in experiment. Inverter output voltge v inv [5V/div] Input voltge of rectifier v in # [V/div] Input voltge of rectifier v in [V/div] Output voltge of receiving bord v dc # [5V/div] [ns/div] B. Fundmentl Chrcteristics Figure shows the opertion wveforms of the proposed isoltion system. Note tht the resistnces of 38 W re connected t the outputs of the system insted of the gte drivers for simplicity. The inverter is operted t frequency of MHz. The DC voltges re obtined s the outputs of receiving bord #. The other bords obtined DC voltges, similrly. C. Efficiency Chrcteristic Figure shows the mesured totl efficiency of the proposed system. The totl efficiency is defined by Eq. (9), where P in is the input DC power of the isoltion system. The totl efficiency is the rtio of the input power nd the sum of the output power for ll of the receiving bords. Note tht the sme resistnce lods re connected to ll of the receiving bords s lod. P outn n,,, 6 h P in The mximum efficiency is 46.9% t n output power of 6.6 W. In the isoltion system for medium-voltge inverter, low efficiency cn be cceptble becuse the power loss in the isoltion system is considerbly smller thn the rted power of medium-voltge inverter (i.e., MW). Thus, the isoltion system is designed to give priority to the isoltion performnce over the efficiency. D. Output Power nd Output Voltge Chrcteristic Figure represents the reltionship between the output voltge nd the output power. In the proposed system, the output voltge is determined by the output power. Thus, DC- DC converters for voltge regultion hve to be connected into the subsequent stge of the system. It mens tht, input voltge rnge of the DC-DC converter provides lower limit nd n upper limit of the output power. In the following experiments, the DC-DC converters, which hve n input voltge rnge from 4.5 V to 8 V, re used. Thus, it is found tht the output power of the receiving bords hve to be lrger thn.4 W. Moreover, the output power of the receiving bords hve to Fig.. Opertion wveforms of proposed system with resistnce lods of 38 W. Efficiency h [%] 5 4 3 R = W (n =,,, 6) Totl output power R = 45 W 5 5 5 Fig.. Efficiency chrcteristic. Output power Pout(n) [W] (n =,,, 6) 6 5 4 3 P min5 P min3 V min P out n [W] n,,,6 Receiving bord #5 4.5 5 5 # #4 Output voltge V out(n) [V] (n =,,, 6) Fig.. Output power v.s. Output voltge on ech bord. be lrger thn.6 W. The difference mong the bords is cused by the difference of the coupling coefficient. In view of using the sme receiving bords, the difference in the coupling coefficient should be smll.
E. Drive of Three-phse Inverter Figure 3 shows the system configurtion for drive test of three-phse inverter. A three-phse inverter is driven by the gte drive circuits with proposed isoltion system. The proposed system is designed with ssuming to be used in diode-clmped five-level inverter. However, two-level inverter, Receiving bords # Trnsmitting bord C # v DC V 5 Hz which hs rted voltge of V, is used for simplicity. The inverter DC voltge is 83 V, crrier frequency is khz, nd n output frequency is 43 Hz. The trnsmitted power is supplied to the gte driver circuit through the DC-DC converter, which ssumes the voltge High-frequency inverter output voltge v inv [5V/div] Input voltge of rectifier v in # [V/div] S S 3 C v inv S S 4 f sw = MHz L #4 #5 Gte driver v uv + Gte driver 3-phse inverter Output voltge of three-phse inverter v uv [5V/div] Output current of three-phse inverter i u [A/div] [ms/div] i u () Output voltge nd current of three-phse inverter High-frequency inverter output voltge v inv [5V/div] () Three-phse inverter with proposed system Gte driver Input voltge of rectifier # [V/div] +5V Photocoupler DC Output voltge of three-phse inverter v uv [5V/div] 8W DC G-6 Output current of three-phse inverter i u [A/div] Control circuit PWM signl -5V G-6 [s/div] (b) Circuit configurtion of gte driver in () (b) Zoomed wveforms of () Fig. 3. System configurtion for experiments with three-phse inverter. High-frequency inverter output voltge v inv [5V/div] Inverter output voltge v inv [5V/div] Input voltge of rectifier v in # [5V/div] Input voltge of rectifier v in # [V/div] Output voltge of three-phse inverter v uv [5V/div] Output voltge V DC (#) [V/div] Output current of three-phse inverter i u [A/div] Gte-emitter voltge v GE (#) [5V/div] [ns/div] [s/div] (c) Zoomed wveforms of (b) Fig. 4. Opertion wveforms of gte drivers with proposed system. Fig. 5. Opertion wveforms of three-phse inverter with proposed isoltion system.
regultion to ±5 V. The resistnces of 8 W re connected in prllel to the DC-DC converters in the gte drive circuits for the protection of the DC-DC converters. Note tht the photocouplers (Toshib, TLP5) re used in order to drive the IGBTs in spite of the deficient isoltion distnce becuse n isoltion of the PWM signl is not min topic of this pper. Figure 4 shows the opertion wveforms the gte drivers with focusing on the gte-emitter voltge of IGBTs. The DC voltges re obtined on the output of the receiving bords. Moreover, gte-emitter voltge of ±5 V is obtined s n output voltge of the gte drivers. Figure 5 shows the opertion wveforms. Fig. 5 () focuses on the opertion wveforms of the three-phse inverter. Fig. 5 (b) focuses on output voltge of the three-phse inverter. The switching wveform with PWM is obtined. Fig. 5 (c) shows the output voltge of the high frequency inverter nd input voltge of the receiving bord #. From the wveforms, it is confirmed tht the three-phse inverter is driven using proposed isoltion system. V. CONCLUSION In this pper, three-phse inverter is driven by the proposed glvnic isoltion system with only printed circuit bords. The proposed system trnsmits power from the trnsmitting bord to six receiving bords using coils mde by the printed circuit bords. This contributes to the cost reduction of the isoltion system. First, the fundmentl chrcteristic of the isoltion system is experimentlly demonstrted. The mximum efficiency is 46.9% t n output power of 6.6 W. Then, the two-level inverter, which hs rted voltge of V, is driven using proposed isoltion system. From these experiments, it is confirmed tht the proposed glvnic isoltion system cn be used in medium-voltge inverter s n isoltion system. ACKNOWLEDGMENT This work ws supported by Jpn Society for the Promotion of Science (JSPS); Grnt-in-Aid for JSPS Fellows (4J8). REFERENCES [] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, S. 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