The up7704 is a 2A ultra low dropout linear regulator specifically designed for motherboard, notebook and graphic card applications. This device works with dual supplies, a control input for the control circuitry and a power input as low as.2 for providing current to output. The up7704 delivers highcurrent and ultralowdrop output voltage as low as 0.8 for applications where O is very close to IN. The up7704 features comprehensive control and protection functions: a power on reset (PO) circuit for monitoring both control and power inputs for proper operation; an input for enabling or disabling the device, a power OK with time delay for indicating the output voltage status, a foldback current limit function, and a thermal shutdown function. The up7704 is available in PSOP8 or WDFN3x30 packages with very low thermal resistance. Desktop PCs, Notebooks, and Workstations Graphic Cards ow oltage ogic Supplies Microprocessor and Chipset Supplies Split Plane Microprocessor Supplies Advanced Graphics Cards Supplies SoundCards and Auxiliary Power Supplies SMPS Post egulators General Description up7704 2A Ultra ow Dropout inear egulator Applications Works with.2~5.5 IN Adjustable Output oltage, Down to 0.8.5% Initial Accuracy Excellent ine and oad egulation 2A Guaranteed Output Current 300m @ 2A Dropout oltage ery ow Onesistance 50mΩ typical O Pull ow esistance when Disabled O Power OK Signal Fast Transient esponse ow External Component Count ow Cost and Easy to Use Enable Pin Over Current and Over Temperature Protection Order Number Package Typ e up7704u8 PSOP8 up7704adda Ordering Information WDFN3x30 Features emark Note: upi products are compatible with the current IPC/ JEDEC JSTD020 and ohs requirements. They are 00% matte tin (Sn) plating and suitable for use in SnPb or Pbfree soldering processes. Pin Configuration & Typical Application Circuit 8 5CC IN 2 3 7 6 O 4 0 O O O 2 3 4 4 5 PSOP8 0 9 8 7 NC IN IN IN 5 6 IN C uf C2 4.7uF IN NC up7704 O 3 0K 2 2.5K 0K C4 option O C3 0uF WDFN3x30
PSOP Pin No. WDFN Name 5 2 6 3 7, 8, 9 IN 4 0 5 X NC 6, 2, 3 O 7 4 Pin Function 8 X G ND Ground. Exposed Pad up7704 Power OK Indication. This pin is an opendrain output and is set high impedance once reaches 90% of its rating voltage. Enable Input. Pulling this pin below 0.4 current to a fraction of its operating value. O turns the regulator off, reducing the quiescent Input oltage. This is the drain input to the power device that supplies current to the output pin. arge bulk capacitors with low ES should be placed physically close to this pin o prevent the input rail from dropping during large load transient. A 4.7uF ceramic capacitor is recommended at this pin. cannot be forced higher than otherwise the current limit IN function may be false triggered and disable the output voltage. Supply Input for Control Circuit. This pin provides bias voltage to the control circuitry and driver for the pass transistor.the driving capability of output current is proportioned to the. For the device to regulate, the voltage on this pin must be at least.5 greater than he output voltage, and no less than t _MIN. Not Internally Connected Functional Pin Description Output oltage. This pin is power output of the device. A pull low resistance exists when the device is disabled by pulling low the pin. To maintain adequate transient response to large load change, typical value of 000uF Al electrolytic capacitor with 0uF ceramic capacitors are recommended to reduce the effects of current transients on O. Feedback oltage. This pin is the inverting input to the error amplifier. A resistor divider the output to is used to set the regulation voltage as = 0.8x(+2)/ ( ) O from Ground. The exposed pad acts the dominant power dissipation path and should be soldered to well designed PCB pads as described in the Application Informations Chapter. Functional Block Diagram IN Thermal imit Power On eset Softstart & Control ogic Current imit 0.8 O Delay 90% 2
Definitions Some important terminologies for DO are specified below. Dropout oltage The input/output voltage differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 2% below its nominal value. Dropout voltage is affected by junction temperature, load current and minimum input supply requirements. ine egulation The change in output voltage for a change in input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that average chip temperature is not significantly affected. oad egulation The change in output voltage for a change in load current at constant chip temperature. The measurement is made under conditions of low dissipation or by using pulse techniques such that average chip temperature is not significantly affected. Maximum Power Dissipation The maximum total device dissipation for which the regulator will operate within specifications. Quiescent Bias Current Current which is used to operate the regulator chip and is not delivered to the load. The quiescent current I Q is defined as the supply current used by the regulator itself that does not pass into the load. It typically includes all bias currents required by the DO and any drive current for the pass transistor. Initialization The up7704 automatically initiates upon the receipt of supply voltage and power voltage. A power on reset circuit continuously monitors IN and pins voltages with rising threshold levels of 0.6 and 2.7 respectively. Chip Enable and Soft Start The up7704 features an enable pin for enable/disable control of the chip. Pulling lower than 0.4 disables the chip and reduces its quiescent current down to 25uA. When disabled, an internal MOSFET of 50Ω DS(ON) turns on to pull output voltage to ground. Pulling higher than.4 enables the output voltage, providing PO is recognized. The up7704 features soft start function that limits inrush current for charging the output capacitors. The soft start time is typically 4ms. Functional Description Output oltage Programming Figure shows a typical application of 2.5 to.8 conversion with a 5.0 control supply. The output voltage is sensed through a voltage divider and regulated to internal reference voltage. The output voltage is programmed as: O = x ( + 2 ) / = 0.8 x (22.5k/0k) =.8 It s recommended to maintain 5000uA through the output divider network for a tight load and line regulation. The internal voltage reference is = 0.8 with.5% initial accuracy. This commands the use of 0.5% or better accuracy resistors to build a precision power supply. 5CC IN 4 0 C uf C2 4.7uF IN NC up7704 O 3 0K 2 2.5K 0K C4 option O C3 0uF Figure. Typical application of 2.5 to.8 conversion with a 5.0 control supply Over Current and Short Circuit Protection The up7704 features a foldback over current protection function as shown in Figure 2. The current limit threshold level is proportional to O / NOM and is typically 2.5A when O = NOM, where NOM is the target output voltage. If the output continuously demands more current than the maximum current, output voltage will eventually drops below its nominal value. This, in turns, will lower its OCP threshold level. This will limit power dissipation in the device when over current limit happens. When output short circuit occurs, the up7704 will try to rebuild the output voltage with maximum allowable current as shown if Figure 3. The duty cycle is about 20% and the averaged short circuit current is about 400mA. 3
Functional Description 2.0.5 O (20m/Div) IN (/Div).0 0.5 0 0A 0.5A.0A.5A 2.0A 2.5A 3.0A 3.5A Figure 2. Current imit Behavior Figure 3. Output Short Circuit Protection 4
Control Input oltage (Note ) 0.3 to +7 Power Input oltage IN 0.3 to +7 Other Pins 0.3 to ( + 0.3) Storage Temperature ange 65 O C to +50 O C Junction Temperature 50 O C ead Temperature (Soldering, 0 sec) 260 O C ESD ating (Note 2) HBM (Human Body Mode) 2k MM (Machine Mode) 200 Package Thermal esistance (Note 3) PSOP8 θ JA 52 C/W PSOP8 θ JC 5 C/W WDFN3x30 θ JA 60 C/W WDFN3x30 θ JC 5 C/W Power Dissipation, P D @ T A = 25 C PSOP8.9W WDFN3x30 θ JA.67W Operating Junction Temperature ange (Note 4) 40 C to +25 C Operating Ambient Temperature ange 40 C to +85 C Supply Input oltage, +3.0 to +5.5 Power Input oltage, IN +.0 to ( = 5, T A = 25 O C, unless otherwise specified) Absolute Maximum ating Thermal Information ecommended Operation Conditions Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Units Supply Input oltage Control Input oltage NT PO Threshold NTTH PO Hysteresis NTHYS Power Input oltage Control Input Shutdown Current in Control Input Current I NT I C O =. 9. 5 C. C IN O =. 0 _SD C Quiescent Current I Q Feedback oltage eference oltage Feedback Input Current IN ine egulatio n (INE ) ine egulatio n ( ) = IN = IN = IN = IN = 5.0, IO = = = = 0A, = 5.0, IO 2 6 2 2. 7 2. 9 0 0. 2 = 0 20 30 ua = 0A, O = = 5.0, I = 0A, = O O = 5.0, IO = 0A. O =.788 0. 3 0. 6 ma 0. 3 0. 6 ma 0 0. 8 0.82 I 20 na.2 < I N < 5.0, = = 5.0, I = 0A. = O O 3.0 < < 5.0, =.2, I = 0A. = IN O O 0.0 0. %/ 0.0 0. %/ 5
Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Units Feedback oltage oad egulation (OAD) oad egulation over Temperature (TOTA ) On esistance DS(ON) Dropout oltage DOP O Enable 0mA < IO < 2.0A, CNT = IN = 0mA < I < 2.0A, = O IN O O 40 C < T < 25 C, by design J IO IO Pull ow esistance = 00mA, CNT = 2.0A, CNT = IN = = = 5.0, O = = = 5.0, =, O = 5.0, O =.6 0. 0. 5 %/ A 0. 5 3 % 50 250 mω = 5.0, =.6, by design 300 500 m O = 5.0, = 0, 50 Ω E N Enable Disable Source High evel ow evel Current Input Impedance Output oltage Time PWOK amp Up. 4 SD 0. 4 I N E = 0, CNT = 5.0 0 20 ua Z 65 KΩ.5 3. 0 4. 5 ms Power OK Threshold T H Power OK Hysteresis HY S Delay Time Overcurrent Protection IO IO From = 0A, CNT = 0A, CNT O = IN = IN = = = 5.0, O = 5.0, O = = 92 % 8 % > 92% to rising 2 4 6 ms NOM OCP Threshold evel I CP Averaged Output Short Circuit Current Thermal Protection O I SC = IN = IN = = = 5.0, O =. 5 2 2. 8 A = 5.0, = 0 00 400 ma O Thermal Shutdown Temperature Thermal Shutdown Hysteresis T SD T SDHYS IO IO = 0A, CNT = 0A, CNT = IN = IN = = = 5.0, O = 5.0, O = = 70 O C 30 O C Note. Stresses listed as the above Absolute Maximum atings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θ JA is measured in the natural convection at T A = 25 C on a low effective thermal conductivity test board of JEDEC 57 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions. 6
Typical Operation Characteristics Power On from Power On from IN (2/Div) IN (2/Div) O (0.5/Div) O (0.5/Div) (2/Div) (2/Div) 2.5ms/Div = IN = 5, C O = 470uF, No oad. Turn On Waveform 2.5ms/Div = IN = 5, C O = 470uF, No oad. Power Off from (2/Div) O (0.5/Div) (2/Div) (2/Div) (2/Div) O (0.5/Div) 2.5ms/Div = IN = 5, C O = 470uF, No oad. Power Off from IN 2.5ms/Div IN = 5, C O = 470uF, I O = 0.2A. Turn Off Waveforms IN (2/Div) O (0.5/Div) O (0.5/Div) (2/Div) (5/Div) (5/Div) 2.5ms/Div = 5, C O = 470uF, I O = 0.2A. 2.5ms/Div = IN = 5, C O = 470uF, I O = 0.2A. 7
Typical Operation Characteristics oad Transient esponse Dropout oltage vs. Output Current O (50m/Div) I O (A/Div) Dropout oltage (m) 300m 250m 200m 50m 00m 50m 0m 0A 0.5A.0A.5A 2.0A 2.5us/Div = 5, C O = 4.7uF, I O = 0A to.6a Output Current (A) Quiescent Current vs. Input oltage Enable/Disable Threshold vs. Input oltage Quiescent Current (ua) 400 350 300 250 200 50 00 50 Enable/Disable Threshold ().2. 0.9 0.8 0.7 0.6 0.5 Disable Enable 0 2.5 3 3.5 4 4.5 5 5.5 IN = () O = 0.4 2.5 3 3.5 4 4.5 5 5.5 IN = () O = Output oltage ine egulation Output oltage oad egulation 0. 0.9 Output oltage ariation (%) 0.05 0 0.05 0. 0.5 Output voltage ariation (%) 0.7 0.5 0.3 0. 0. 0.3 0.2 2.5 3 3.5 4 4.5 5 5.5 IN = () 0.5 0 0.5.5 2 Output Current (A) 8
Typical Operation Characteristics On esistance (mω) 200 90 80 70 60 50 40 30 20 0 00 On esistance vs. Input oltage Output oltage ariation (%) 0.5 0 0.5.5 2 Output oltage vs. Temperature 2.5 3 3.5 4 4.5 5 5.5 Control Input () O =.8 50 0 50 00 50 Junction Temperature ( O C) Current imit Output oltage () 2.0.5.0 0.5 0 0A 0.5A.0A.5A 2.0A 2.5A 3.0A 3.5A Output Current (A) 9
Application Information The up7704 is a high performance linear regulator specifically designed to deliver up to 2A output current with very low input voltage and ultra low dropout voltage. With dualsupply configuration, the up7704 operates with a wide input voltage IN range from.2 to 5.5 and is ideal for applications where O is very close to IN. Supply oltage for Control Circuit Unlike other linear regulators that use a PChannel MOSFET as the pass transistor, the up7704 uses an N Channel as the pass transistor. NChannel MOSFET provides lower onresistance and better stability meeting stringent requirements of current generation microprocessors and other sensitive electronic devices. The drain of NChannel MOSFET is connected to IN and the source is connected to O. This requires that the supply voltage for control circuit is at least.5 higher than the output voltage to provide enough overdrive capability for the pass transistor thus to achieve low dropout and fast transient response. It is highly recommended to bias the device with 5 voltage source if available. Use a minimum uf ceramic capacitor plus a 0Ω resistor to locally bypass the control voltage. Input/Output Capacitor Selection The up7704 has a fast transient response that allows it to handle large load changes associated with high current applications. Proper selection of the output capacitor and its ES value determines stable operation and optimizes performance. The typical application circuit shown in Figure was tested with a wide range of different capacitors. The circuit was found to be unconditionally stable with capacitor values from 0uF to 000uF and ES ranging from 0.5mΩ to greater then 75mΩ. 5CC IN 4 0 C uf C2 4.7uF IN NC up7704 O 3 0K 2 2.5K 0K C4 option O C3 0uF Figure. Typical Application Circuit Input capacitor: A minimum of 4.7uF ceramic capacitor is recommended to be placed directly next to the IN pin. This allows for the device being some distance from any bulk capacitance on the rail. Additionally, bulk capacitance may be added closely to the input supply pin of the up7704 to ensure that IN does not sag, improving load transient response. Output capacitor: A minimum bulk capacitance of 0uF, along with a 0.uF ceramic decoupling capacitor is recommended. Increasing the bulk capacitance will improve the overall transient response. The use of multiple lower value ceramic capacitors in parallel to achieve the desired bulk capacitance will not cause stability issues. Although designed for use with ceramic output capacitors, the up7704 is extremely tolerant of output capacitor ES values and thus will also work comfortably with tantalum output capacitors. Thermal Consideration The up7704 integrates internal thermal limiting function to protect the device from damage during fault conditions. However, continuously keeping the junction near the thermal shutdown temperature may remain possibility to affect device reliability. It is highly recommended to keep the junction temperature below the recommended operation condition 25 O C for maximum reliability. Power dissipation in the device is calculated as: P D = ( IN O ) x I O + x I It is adequate to neglect power loss with respective to control circuit x I when considering thermal management in up7704 Take the following moderate operation condition as an example: IN = 3.3, O =.5, I O = A, the power dissipation is: P D = (3.3.5) x A =.8W This power dissipation is conducted through the package into the ambient environment, and, in the process, the temperature of the die (T J ) rises above ambient. arge power dissipation may cause considerable temperature raise in the regulator in large dropout applications. The geometry of the package and of the printed circuit board (PCB) greatly influences how quickly the heat is transferred to the PCB and away from the chip. The most commonly used thermal metrics for IC packages are thermal resistance from the chip junction to the ambient air surrounding the package (θ JA ): θ JA = ( T J T A ) / P D θ JA specified in the Thermal Information section is measured in the natural convection at T A = 25 O C on a high effective thermal conductivity test board (4 ayers, 2S2P) of JEDEC 57 thermal measurement standard. The case point of 0
Application Information θ JC is on the exposed pad for PSOP8 package. Given power dissipation P D, ambient temperature and thermal resistance θ JA, the junction temperature is calculated as: O NC T J = T A + ΔT JA = T A + P D x θ JA To limit the junction temperature within its maximum rating, the allowable maximum power dissipation is calculated as: 8 7 6 2 3 4 5 up7704 P D(MAX) = ( T J(MAX) T A ) /θ JA where T J(MAX) is the maximum operation junction temperature 25 O C, T A is the ambient temperature and the θ JA is the junction to ambient thermal resistance. θ JA of PSOP8 packages is 75 O C/W on JEDEC 57 (4 layers, 2S2P) thermal test board with minimum copper area. The maximum power dissipation at T A = 25 O C can be calculated as: P D(MAX) = (25 O C 25 O C) / 75 O C/W =.33W The thermal resistance θ JA highly depends on the PCB design. Copper plane under the exposed pad is an effective heatsink and is useful for improving thermal conductivity. Figure 3 show the relationship between thermal resistance θ JA vs. copper area on a standard JEDEC 57 (4 layers, 2S2P) thermal test board at T A = 25 O C. A 50mm 2 copper plane reduces θ JA from 75 O C/W to 52 O C/W and increases maximum power dissipation from.33w to.9w. IN Figure 4. ecommended PCB ayout. ayout Consideration. Place a local bypass capacitor as closed as possible to the IN pin. Use short and wide traces to minimize parasitic resistance and inductance. 2. The exposed pad should be soldered on plane with maximum area and with multiple vias to inner layer of ground place for improving thermal performance. 3. Connect voltage divider directly to the point where regulation is required. Place voltage divider close to the device. 00 90 T hermal esistance θ JA ( O C/W) 80 70 60 50 40 30 0 0 20 30 40 50 60 70 Copper Area (mm 2 ) Figure 3. Thermal esistance θ JA vs. Copper Area Figure 4 illustrated the recommended PCB layout for best thermal performance.
0.70.27.50 PSOP8 Package 4.80 5.00 3.00 BSC Package Information 3.00 2.20 BSC 3.80 4.00 5.80 6.20 4.00 2.20 5.50 7.00 ecommended Solder Pad ayout.27 BSC 0.32 0.52.45.60 0.20 BSC 0.8 0.25.75 MAX 0.05 0.25 0.40 0.90 3.8 BSC Note.Package Outline Unit Description: BSC: Basic. epresents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. : eference. epresents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.5mm. 2
WDFN3x30 Package Package Information 2.90 3.0 0.35 0.45 2.25 2.35 6 0.55.65 2.90 3.0 5 0.50 BSC 0.8 0.28 2.25 2.35 0.20 0.00 0.05 0.80 MAX.55.65.95 2.05 3.55 3.65 0.50 BSC 0.8 0.28 ecommended Solder Pitch and Dimensions Note.Package Outline Unit Description: BSC: Basic. epresents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. : eference. epresents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.5mm. 3