NTF955 Power MOSFET V,. A, Single P Channel SOT Features TMOS7 Design for low R DS(on) Withstands High Energy in Avalanche and Commutation Modes Pb Free Package is Available Applications Power Supplies PWM Motor Control Converters Power Management V (BR)DSS V R DS(on) TYP 5 m @ V P Channel D I D MAX. A MAXIMUM RATINGS (T J = 5 C unless otherwise noted) G Parameter Symbol Value Unit Drain to Source Voltage V DSS V S Gate to Source Voltage V GS ± V Continuous Drain Current (Note ) Power Dissipation (Note ) T A = 5 C I D. A T A = 5 C. T A = 5 C P D. W SOT CASE E STYLE Continuous Drain Current (Note ) Power Dissipation (Note ) T A = 5 C I D.7 A T A = 5 C. T A = 5 C P D. W MARKING DIAGRAM AND PIN ASSIGNMENT Drain Pulsed Drain Current tp = s I DM. A Operating Junction and Storage Temperature T J, T STG Single Pulse Drain to Source Avalanche Energy (V DD = 5 V, V G = V, I PK =.7 A, L = mh, R G = 5 ) Lead Temperature for Soldering Purposes (/ from case for seconds) THERMAL RESISTANCE RATINGS 55 to 75 C EAS 5 mj T L C Parameter Symbol Max Unit Junction to Tab (Drain) (Note ) R JC Junction to Ambient (Note ) R JA 5 Junction to Ambient (Note ) R JA 5 C/W Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. When surface mounted to an FR board using in. pad size (Cu. area =.7 in [ oz] including traces). When surface mounted to an FR board using the minimum recommended pad size (Cu. area =. in ) Gate AYW 955 Drain Source A = Assembly Location Y = Year W = Work Week 955 = Device Code = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping NTF955T SOT /Tape & Reel NTF955TG SOT (Pb Free) /Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD/D. Semiconductor Components Industries, LLC, January, Rev. Publication Order Number: NTF955/D
NTF955 ELECTRICAL CHARACTERISTICS (T J =5 C unless otherwise stated) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = 5 A V Drain to Source Breakdown Voltage Temperature Coefficient V (BR)DSS /T J. mv/ C Zero Gate Voltage Drain Current I DSS V GS = V, V DS = V T J = 5 C. A T J = 5 C Gate to Source Leakage Current I GSS V DS = V, V GS = ± V ± na ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V DS, I D =. ma.. V Drain to Source On Resistance R DS(on) V GS = V, I D =.75 A 5 7 m 5 V GS = V, I D =.5 A 5 V GS = V, I D =. A 5 5 Forward Transconductance g FS V GS = 5 V, I D =.75 A.77 S CHARGES AND CAPACITANCES Input Capacitance C ISS V GS = V, f =. MHz, 9 pf Output Capacitance C OSS V DS = 5 V 5 Reverse Transfer Capacitance C RSS 5 Total Gate Charge Q G(TOT) V GS = V, V DS = V,. nc Threshold Gate Charge Q G(TH) I D =.5 A. Gate to Source Charge Q GS. Gate to Drain Charge Q GD 5. SWITCHING CHARACTERISTICS (Note ) Turn On Delay Time t d(on) V GS = V, V DD = 5 V, ns Rise Time t r I D =.5 A, R G = 9. R L = 5 7. Turn Off Delay Time t d(off) 5 Fall Time t f DRAIN SOURCE DIODE CHARACTERISTICS Forward Diode Voltage V SD V GS = V, I S =.5 A Reverse Recovery Time t RR T J = 5 C.. V T J = 5 C.9 Charge Time t a V GS = V, di S /dt = A/ s, Discharge Time t b I S =.5 A Reverse Recovery Charge Q RR.9 nc. Pulse Test: pulse width s, duty cycle %.. Switching characteristics are independent of operating junction temperatures. ns
NTF955 TYPICAL PERFORMANCE CURVES (T J = 5 C unless otherwise noted) V GS = V V GS = V to 7 V T J = 5 C V GS = 5.5 V V GS = 5 V V GS =.5 V V GS =. V 5 7 9 V DS V T J = 55 C T J = 5 C T J = 5 C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) V GS, GATE TO SOURCE VOLTAGE (VOLTS) Figure. On Region Characteristics Figure. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ) R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED)............ V GS = V.5 Figure. On Resistance versus Drain Current and Temperature I D =.5 A V GS = V T J = 5 C T J = 5 C T J = 55 C 5 5 5 5 75 5 T J, JUNCTION TEMPERATURE ( C) Figure 5. On Resistance Variation with Temperature 5 R DS(on), DRAIN TO SOURCE RESISTANCE ( ) I DSS, LEAKAGE (na).5.5..75.5.5..75 T J = 5 C V GS = 5 V Figure. On Resistance versus Drain Current and Gate Voltage V GS = V V GS = V T J = 5 C T J = 5 C 5 5 5 5 5 5 55 V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure. Drain to Source Leakage Current versus Voltage
NTF955 TYPICAL PERFORMANCE CURVES (T J = 5 C unless otherwise noted) C, CAPACITANCE (pf) C iss C rss V DS = V V GS = V T J = 5 C C oss C rss 5 5 5 5 V GS V DS GATE TO SOURCE OR DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation C iss V GS, GATE TO SOURCE VOLTAGE (VOLTS) Q GS Q GD Q T V GS V DS I D =.5 A T J = 5 C Q g, TOTAL GATE CHARGE (nc) Figure. Gate to Source and Drain to Source Voltage versus Total Charge 5 V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) t, TIME (ns) V DD = 5 V I D =.5 A V GS = V t d(off) t f t d(on) t r I S, SOURCE CURRENT (AMPS) 5 V GS = V T J = 5 C.5.5 R G, GATE RESISTANCE ( ) Figure 9. Resistive Switching Time Variation versus Gate Resistance.75.5.5 V SD, SOURCE TO DRAIN VOLTAGE (VOLTS).75 Figure. Diode Forward Voltage versus Current I D, DRAIN CURRENT (AMPS) V GS = V SINGLE PULSE T C = 5 C dc s s ms ms. R DS(on) LIMIT 5 THERMAL LIMIT PACKAGE LIMIT.. 5 5 75 5 5 75 V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) T J, STARTING JUNCTION TEMPERATURE ( C) Figure. Maximum Rated Forward Biased Safe Operating Area E AS, SINGLE PULSE DRAIN TO SOURCE AVALANCHE ENERGY (mj) 5 5 I PK =.7 A Figure. Maximum Avalanche Energy versus Starting Junction Temperature
NTF955 PACKAGE DIMENSIONS SOT (TO ) CASE E ISSUE L D b NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 9.. CONTROLLING DIMENSION: INCH.. () H E e A e b E A L C MILLIMETERS DIM MIN NOM MAX MIN A.5..75. A.... b..75.9. b.9...5 c..9.5.9 D..5.7.9 E..5.7. e....7 INCHES NOM MAX......5.....5...5.9.9 e.5.9.5..7. L.5.75...9.7 HE.7 7. 7...7.7 STYLE : PIN. GATE. DRAIN. SOURCE. DRAIN SOLDERING FOOTPRINT*..5..79..9..9....79.5.59 SCALE : mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Phoenix, Arizona 5 USA Phone: 9 77 or Toll Free USA/Canada Fax: 9 779 or 7 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 955 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, Meguro ku, Tokyo, Japan 5 5 Phone: 577 5 5 ON Semiconductor Website: Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NTF955/D