Lab 6: MOSFET AMPLIFIER

Lab 6: MOSFET AMPLIFIER NOTE: This is a "take home" lab. You are expected to do the lab on your own time (still working with your lab partner) and then submit your lab reports. Lab instructors will be available to provide help if you run into problems, but you are not expected to do the lab in the scheduled lab session. NOTE: You are still REQUIRED to demonstrate the final working amplifier to a Lab Instructor (Lab Instructors will be available at the start of the scheduled lab sessions or contact a Lab Instructor to make alternate arrangements). 1. Learning Outcomes In this lab, students design and implement a single-stage MOSFET amplifier and explore the frequency response of the amplifier. A breadboard and an Analog Discovery Module are used in this experiment. The students will use various tools and functions from the Waveforms software to perform measurements and to plot the amplifier response. 2. Health and Safety Any laboratory environment may contain conditions that are potentially hazardous to a person s health if not handled appropriately. The Electrical Engineering laboratories obviously have electrical potentials that may be lethal and must be treated with respect. In addition, there are also mechanical hazards, particularly when dealing with rotating machines, and chemical hazards because of the materials used in various components. Our LEARNING OUTCOME is to educate all laboratory users to be able to handle laboratory materials and situations safely and thereby ensure a safe and healthy experience for all. Watch for posted information in and around the laboratories, and on the class web site. 3. Lab Report Each student must have a lab book for the labs. The lab book is used for lab preparation, notes, record, and lab reports. The lab books must be handed before 5:00 pm on the due date into the box labeled for your section across from 2C94. The lab books are marked and returned before the next lab. 4. Background Background given in Procedure section and Appendices. Rev A Copyright 2016 University of Saskatchewan Page 1 of 13

5. Material and Equipment Material (supplied by department) Capacitors: 0.1 µf, various values calculated for the lab Resistor: 100 Ω (from Lab #5), 10 kω, various values calculated for the lab CD4007UB CMOS Dual Complementary Pair Plus Inverter (from Lab #5) Equipment (supplied by student) Analog Discovery Module Waveforms software Breadboard and wiring kit Note that extra required parts can be picked up from 2C80/82 (resistors) or from the Support Engineers in 2C94. You should measure the actual values of the resistors and capacitors that you pick up, both to confirm the right nominal values but also, as there are some variations in their values, to make sure you are ending up with values reasonably close to your calculated required values. Note that often you may be required to combining two resistors in series to get overall resistances of specific values. Capacitors are less of an issue for coupling caps, you can usually go to the next largest value available compared to your target value. 6. Prelab No Prelab as this is a "take home" Lab. 7. Lab Procedures Debugging (or What To Try When Things Aren't Working) There are a number of things/procedures you should use to debugging circuits when things are not working correctly. These include (but are not limited to): Check that all component pins are correctly inserted in the breadboard (sometimes they get bent underneath a component). Make sure that components are not "misaligned" in the breadboard (e.g. off by one row). Double check component values (you can measure resistors, capacitors, and inductors). Try a different section in the breadboard (in case there is a bad internal connection). Measure the source voltages to verify power input. Measure key points in the circuit for proper voltage/waveform (i.e. divide-and-conquer). Rev A Copyright 2016 University of Saskatchewan Page 2 of 13

N-Channel MOSFET I-V Characteristics This section of the procedure determine the V GS for the transistor for an I D = 2 ma as well as the threshold voltage V th (which will be used later in this lab). 1. Construct the circuit shown Figure 7-1 on your breadboard: Wavegen Channel 1 R D 100 Ω G 3 CD4007UB D S 4 5 7 Figure 7-1: I D versus V GS Circuit 2. Set Wavegen Channel 1 to a 100 Hz Triangle wave, Amplitude = 2.5 V, Offset = 2.5 V. Should appear similar to Figure 7-2. 3. Connect Scope Channel 1 to measure V GS. 4. Connect Scope Channel 2 to measure the voltage across Resistor R D. We will use this voltage to determine the current I D into the MOSFET. 5. Use the Scope to show the I D versus V GS: 5.1. Add Math 1 to calculate I D (i.e. "C2 / 100"). Change the units of Math 1 to "A" and set the Range to something appropriate (e.g. 1 ma/div). 5.2. Turn off the display of Channel 2 and adjust the Time and Channel parameters to provide a good view of Channel 1 and Math 1. 5.3. Use "Add XY" to display the I D versus V GS graph (X = Channel 1 and Y = Math 1). 5.4. Adjust the parameters for Channel 1 and Math 1 to provide a good view of the I D versus V GS graph. 5.5. Obtain a screen capture/print out of the I D versus V GS graph (should be similar to Figure 7-3). 5.6. From the XY graph (you can also use the X-cursor on the "Main time view"), determine and record the V GS that results in an I D = 2 ma as well as the threshold voltage V th (the minimum V GS for the transistor to turn on and start to conduct current). Note that you will need these values in the next parts of the lab. Rev A Copyright 2016 University of Saskatchewan Page 3 of 13

Figure 7-2: Wavegen Settings Figure 7-3: I D versus V GS Rev A Copyright 2016 University of Saskatchewan Page 4 of 13

6. Display the I D versus V DS curve for your selected V GS: 6.1. Disconnect the Gate from the Drain in Figure 7-1. 6.2. Use Wavegen Channel 2 to drive V GS. Set to a DC value corresponding to the V GS you determined on the previous step which results in an I D = 2 ma (i.e. select the "DC" standard waveform and set "Offset" appropriately). 6.3. Move Channel 1 to measure V DS (i.e. 1+ on "D" and 1- on "S"). 6.4. Display and capture the I D versus V DS plot (should look similar to Figure 7-4). Figure 7-4: I D versus V DS Rev A Copyright 2016 University of Saskatchewan Page 5 of 13

Design the MOSFET Amplifier Design a MOSFET amplifier using the circuit shown in Figure 7-5 with a voltage gain AA VV = 2 (i.e. determine suitable values for R D, R S, R 1 and R 2). The design is based on the I-V characteristics of the n- channel MOSFET obtained in the previous step. Design for VDD = 10 V (i.e. ±5 V supply from the Analog Discovery module), ID = 2 ma, Rin > 100 kω, and V D normally sitting at the half way point (i.e. 0 V). +5 V D G S -5 V Figure 7-5: MOSFET Amplifier Circuit Schematic The following analysis is appropriate for good quality transistors where the output current, ID, is largely independent of the output voltage VDS (the output characteristic curves are approximately flat ). The small signal FET equivalent circuit is shown in Figure 7-6. We can calculate the amplifier AC gain using the small signal FET transconductance gm and we assume ro can be neglected because it is very large in comparison to other circuit resistances, therefore A = -g mr D. The input resistance is essentially R1 R2 and the output impedance is equal to RD if ro is very large. The small signal AC gain is calculated assuming that capacitors have negligible impedance. Figure 7-6: Small Signal FET Equivalent Circuit Rev A Copyright 2016 University of Saskatchewan Page 6 of 13

The amplifier gain can be found by: i e = V + ir = + ir e d in gs d S d S gm = ir o d D eo RD gmrd Av = = = e 1 in + R 1 + gmrs S g m Transconductance g m can be calculated by (using the parameters determined in section 7.2): 2 I D g = ; V = V V V m OV GS th OV R D can be determined by: R D V = I RD D Using the equation for the amplifier gain, the specified values of A V and I D, the determined values for V GS and V T (from section 7.2), and the calculated value for R D, calculate the required value for R S. Determine the resulting V DS and plot on the I D versus V DS plot from section 7.2.6. The voltage at the MOSGET gate, V G, is set by the values of resistors R 1 and R 2 and must also be equal to: VG = VGS + ID RS Calculate the value for V G and then select R 1 and R 2 which achieve the required voltage while also having an input impedance > 100 kω (i.e. R 1 R 2 > 100 kω). Rev A Copyright 2016 University of Saskatchewan Page 7 of 13

Simulate the MOSFET Amplifier 1. Using the values for R D, R S, R 1, and R 2 calculated in section 7.3, modify the SPICE deck in Figure 7-8 below (i.e. replace the "XXX' with appropriate values, also set the value of VTO which is the transistor threshold voltage): MOSFET CS Amplifier Vdd vdd 0 DC 10V Vin vin 0 SIN(0 100mV 1kHz) C1 vin vg 1uF R1 vdd vg XXX R2 vg 0 XXX M1 vd vg vs vs NMOSFET Rd vdd vd XXX Rs vs 0 XXX C2 vd vo 1uF.TRAN 0.01m 4m ; 10 V voltage source ; 100 mv, 1 khz AC input ; DC blocking capacitor ; Bias resistor ; Bias resistor ; MOSFET D G S B ; Drain resistor ; Source resistor ; DC blocking capacitor ; Simulate in 0.01 ms steps until 4 ms.model CMOSN NMOS ( LEVEL = 1 L=5u W=20u +VTO = 1.00 Kp = 2.169e-4 GAMMA = 4.10 +PHI = 0.65 LAMBDA = 1.5e-2 CBD = 20e-12 +CBS = 0 IS = 1e-15 PB = 0.87 +CBS = 2e-14 CGDO = 88e-8 CGBO = 0 +CJ = 2e-10 MJ = 0.5 CJSW = 1e-9 +MJSW = 0.33 JS = 1e-8 TOX = 1.265e-10).end Figure 7-7: SPICE Deck for MOSFET Amplifier 2. Using LTspice, include a screen capture of the plot of the V o and V in in your lab report. It should indicate a gain of -2 if your calculated values are correct. Use "Plot Settings Add Trace" to view "V(vin)" and "V(vo)". The plot should look similar to Figure 7-9. Rev A Copyright 2016 University of Saskatchewan Page 8 of 13

Figure 7-8: SPICE Output Build and Test the MOSFET Amplifier 1. Construct the amplifier indicated in Figure 7-5 using a CD4007 n-channel FET and other components of your design. Select C 1 to have a cut-off frequency of 50 Hz and C 2 to have a cut-off frequency of 100 Hz (See Appendix 1 on selecting appropriate capacitors). Do not connect a signal generator and the capacitors C1 or C2 yet: 1.1. Measure ID, VDS, V D, VG, VS and VGS and comment how they compare to your design calculations. 2. Connect capacitors C1 and C2 and use Wavegen Channel 1 to apply a 100 mv peak 1 khz sinusoid to the input. Use Channel 1 to measure the input and Channel 2 to measure the output on the Scope. Connect 1- and 2- of the Scope channels to the Analog Discovery ground. 3. Add measurements: 3.1. Channel 1 Frequency. 3.2. Channel 1 Amplitude. 3.3. Channel 2 Amplitude. 4. Add Gain measurement: 4.1. Select Measurements Add Custom Global. Rev A Copyright 2016 University of Saskatchewan Page 9 of 13

4.2. Set the content to Scope.Channel2.measure("Amplitude")/Scope.Channel1.measure("Amplitude ). 4.3. Set Name to Gain. 4.4. Set Units to blank. 5. Add an X-Y window of C1 and C2, the slope represents the gain of the amplifier. 5.1. If everything is working well, your Scope window should look similar to Figure 7-10. Include a screen capture of your Scope window in your lab report. 5.2. Comment if the observed gain matches the design goals. Figure 7-9: Scope Window Showing Unloaded Gain 6. Determine if the input impedance at 1 khz is what you were expecting: 6.1. Calculate the theoretical input impedance (i.e. R1 R2). 6.2. Insert a resistor, R x, between Wavegen Channel 1 and C 1. Repeat three times with the values of R x being approximately one-half, equal-to, and twice that of the theoretical input impedance. 6.3. For each case, measure the input voltage between R x and C 1 (to ground) and compare it to the input voltage from Wavegen Channel 1. Calculate the measured input impedance from these values and compare to the theoretical input impedance. 6.4. Remove R x before proceeding to the next step. Rev A Copyright 2016 University of Saskatchewan Page 10 of 13

7. Place a bypass capacitor, CS = 0.1 μf, in parallel with RS. Calculate the magnitude of the gain of the amplifier at 1 khz and verify it experimentally. You will need to use the approximate value of gm which you calculated using the drain current: 7.1. Increase the frequency of the input signal until you see a distortion of the output signal. Record this frequency and take a screen shot of the distorted output signal. 7.2. Is the output signal first distorted at the high voltage or the low voltage portion of its waveform? Provide an explanation. 8. Remove the bypass capacitor C S added in the previous step. Connect a 10 kω load resistor as shown in Figure 7-11. Measure e o and compare to the calculated expected value. +5 V -5 V Figure 7-10: Amplifier with Load Resistor 9. Leave the 10 kω load resistor connected. For this step, you are going to determine the bandwidth of the amplifier: 9.1. Reduce the frequency of the input signal until the magnitude of the output voltage is 0.707 of what it was when the input signal was at 1 khz. Record this frequency (f L). 9.2. Increase the frequency of the input signal past 1 khz until the magnitude of the output voltage is 0.707 of what it was when the input signal was at 1 khz. Record this frequency (f H). 9.3. The amplifier bandwidth is defined as f H - f L. Document the frequencies in your report. A discussion of the frequency response of a FET amplifier can be found in Appendix 2. Rev A Copyright 2016 University of Saskatchewan Page 11 of 13

Appendix 1 Selecting Coupling Capacitors Be careful when choosing your coupling capacitors (C1 and C2). For this experiment, you should be able to use non-polarized capacitors. Polarized capacitors tend to have higher capacitance values, usually 5 μf, and they are always marked with either a + or a (or both) next to one of their terminals. They may also be marked with a band to indicate the negative end (same convention as a diode). Remember that the potential of the + terminal should be always higher than the terminal when connected in a circuit. Otherwise, it will induce the leak current between the two terminals and eventually damage the capacitor. In the signal path of a circuit such as C1 and C2, this condition may not be met in all cases since the connected circuits are unknown. Therefore you should avoid polarized capacitors in the signal path. Coupling capacitors must be chosen so that they have a small impedance at the frequency of interest compared with the input impedance of the circuit to which they re connected. This is to ensure that little voltage will be dropped or lost across the capacitor itself after all, an amplifier is supposed to amplify voltages, not attenuate them. A good rule of thumb is that Z coupling C should be no more than approximately 10% of the input impedance of the amplifier (for the input coupling capacitor) or the input impedance of whatever circuit the amplifier drives (for the output coupling capacitor). For the FET amplifier you just constructed, the input impedance is supposed to be > 100 kω. Therefore the impedance of C1 at the lowest frequency the amplifier is expected to see should be no more than approximately 10 kω. Calculate the value of C 1 such that its impedance is less than 10 kω at a lowest expected frequency of 50 Hz. Similarly, the amplifier drives a load of 10 kω. Following the same argument the impedance of C 2 at the lowest expected frequency should be no more than approximately 1 kω. Calculate the value of C 2 such that its impedance is less than 1 kω at a lowest expected frequency of 100 Hz. Appendix 2 Frequency Response of a FET Amplifier The typical Frequency Response of an amplifier is presented in a form of a graph that shows output amplitude (or, more often, voltage gain) plotted versus log frequency. Typical plot of the voltage gain is shown in the figure below. The gain is null at zero frequency, then rises as frequency increases, level off for further increases in frequency, and then begins to drop again at high frequencies. The frequency response of an amplifier can be divided into three frequency regions. Rev A Copyright 2016 University of Saskatchewan Page 12 of 13

The frequency response begins with the lower frequency region designated between 0 Hz and lower cutoff frequency. At lower cutoff frequency, f L,the gain is equal to 0.707 A mid. A mid is a constant midband gain obtained from the midband frequency region. The third, the upper frequency region covers frequency between upper cutoff frequency and above. Similarly, at upper cutoff frequency, f H, the gain is equal to 0.707 A mid. After the upper cutoff frequency, the gain decreases with frequency increases and dies off eventually. The Lower Frequency Response: Since the impedance of coupling capacitors increases as frequency decreases, the voltage gain of a FET amplifier decreases as frequency decreases. At very low frequencies, the capacitive reactance of the coupling capacitors may become large enough to drop some of the input voltage or output voltage. Approximately, the following equations can be used to determine the lower cutoff frequency of the amplifier, where the voltage gain drops 3 db from its midband value (= 0.707 times the midband A mid): (1) f 1 = 1/ ( 2πR inc 1 ) where: f 1 = lower cutoff frequency due to C 1, C 1 = input coupling capacitance, R in = input resistance of the amplifier. (2) f 2 = 1/ ( 2πR outc 2 ) where: f 2 = lower cutoff frequency due to C 2, C 2 = output coupling capacitance, R out = output resistance of the amplifier. Provided that f 1 and f 2, are not close in value, the actual lower cutoff frequency is approximately equal to the larger of the two. The Upper Frequency Response: Transistors have inherent shunt capacitances between each pair of terminals. At high frequencies, these capacitances effectively short the AC signal voltage. Rev A Copyright 2016 University of Saskatchewan Page 13 of 13