Course Introduction Purpose This module provides an overview of sophisticated peripheral functions provided by the MCUs in the M32C series, devices at the top end of the M16C family. Objectives Gain a basic understanding of the features and operation of the Intelligent I/O peripheral. Understand the benefits the X-Y Converter provides. Discover how the DMAC II peripheral operates. Learn about the CAN peripheral Content 26 pages 4 questions Learning Time 40 minutes 1
Intelligent I/O Peripheral Multi-functional I/O port with many capabilities: Time measurement Waveform generation Clock-synchronous serial I/O Clock-asynchronous serial I/O (UART) IEBus* communications HDLC data processing and more Consists of four circuit groups, each of which has the following: One 16-bit free-running timer Eight 16-bit registers Two 8-bit shift registers (or one 16-bit register) * IEBus is a trademark of NEC Corporation 2
Functions Available, by Group Intelligent I/O Function Group 0 Group 1 Group 2 Group 3 Time Measurement 1 Digital Filter Trigger Input Pre-scaler Trigger Input Gate Waveform Generation 1 Single Phase Waveform Output Digital Filter Phase Delayed Waveform Output SR Waveform Output Bit Modulation PWM Output RTP Output Parallel PWM Output Communication 1 Clock Sync Serial I/O Mode UART Mode HDLC Data Processing Mode IE Mode 4 channels 8 channels (3 channels) 2 (2 channels) 8 channels 4 channels (3 channels) (2 channels) 2 channels 2 channels 2 channels 2 channels 4 channels (2 channels) Available Not Available 8 channels (3 channels) Available Not Available Not Available 8 channels (3 channels) Not Available 8 channels (2 channels) Groups 0, 1 cascaded 8 channels (3 channels) 8 channels (3 channels) 2 channels 2 channels 8 channels (3 channels) Available Available Available Not Available 8 bits, fixed Variable 8 bits/16 bits Not Available Available Available Available Not Not Not Available Available Available Not Available Available 1) Time Measurement Function shares pins with the Waveform Generation function 2) Channels for the 100-pin Package are shown in parentheses. 3
Time Measurement Function Time measurement The time between every edge (rising, falling or both) is measured. Digital filter function The Digital filter samples an input signal every f 1 of f BTi pulses. (Base Counter) An edge is excepted/counted if the input pulse >3 (<3.5) Base Counter pulses. Cascaded connection function Groups 0 and 1 are connected to operate as a 32-bit timer. Pre-scaler function (Channels 6 and 7) The time period measured is the time taken for [ x +1] edges, where x is defined in the Timer Prescaler. Gate function (Channels 6 and 7) Input signals are only accepted when the Gate is enabled. ( Gate is software controlled.) 4
Time Measurement Examples INPCij Input Pin Clock H FFFF m n p H 0 Input Pin Signals which do not match 3 clock cycles are ignored. Trigger Signal After Digital Filter Digital Filter Function Maximum of 3.5 Clock Cycles GiTMj n m p INPCij Input Pin Time Measurement Function Rising Edge Selected as Trigger H FFFF m n H FFFF y H 0 z m x n Input Pin Gate Control is not Enabled. Therefore this input is ignored. p H 0 Gate Control GiTMj n x m y p m z Time Measurement Function Both Edges Selected as Trigger GiTMj n Gate Function m 5
Waveform Generation Function Waveforms are generated when the value of the base timer matches the value of the GiPOj registers. (i = 0 to 3, j = 0 to 7) Six output modes are available: Single-Phase Waveform (supported by Groups 0, 1, 2, 3) Phase-Delayed Waveform (supported by Groups 0, 1, 2, 3) Set/Reset Waveform (supported by Groups 0, 1, 2, 3) Bit-Modulation PWM (supported by Groups 2 and 3) Real-Time Port (supported by Groups 2 and 3) Parallel Real-Time Port (supported by Groups 2 and 3) 6
Waveform Generation Examples H FFFF m + 2 n H 0 OUTCik pin Waveform Generation Function Single-Phase Waveform Output H FFFF p + 2 n m H 0 OUTCik pin Waveform Generation Function Set-Reset Waveform Output H FFFF m + 2 n H 0 OUTCik pin Waveform Generation Function Phase-Delayed Waveform Output 7
Bit-Modulation PWM Mode T = 1024 Pulses n 64/f Width of LOW / HIGH period is modified by 1 clock Value of m 0000000000 0000000001 0000000010 0000000100 0000001000 : 100000000 Pulse to which Bit Time will be added None t 512 t 256, t 768 t 128,t 384, t 640, t 896 t 64, t 192, t 320, t 448, t 576, t 704, t 832, t 960 : t 1, t 3, t 5, t 7,.. t 1019, t 1021, t 1023 n = 0 to 63 m = 0 to 1023 - Specifies which PWM pulse is modified Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIPOj 8
Communication Function Communication capabilities vary from group to group within the Intelligent I/O peripheral: Groups 0 and 1 support 8-bit Synchronous Serial I/O 8-bit Asynchronous Serial I/O High-Level Data-Link Control (HDLC) data processing, including bit stuffing, flag detection, abort detection and CRC processing Group 2 supports Variable Clock Synchronous Serial I/O IEBus Group 3 supports 8-bit Clock Synchronous Serial I/O 16-bit Clock Synchronous Serial I/O 9
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X-Y Conversion Function Converts a 16 x 16 matrix of data by 90 degrees, and inverts high-order and low-order bits WRITE TO Xn s X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 CONVERSION READ FROM Yn s Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Before After After the conversion process, these bits effectively remain stationary. Bit positions after 90 O rotation and high-order to low-order inversion 11
DMAC II Function Transfers performed: Memory to Memory ( Memory to Memory Transfer ) Immediate Data to Memory ( Immediate Data Transfer ) Memory ( or Immediate Data ) + Memory to Memory ( Arithmetic Transfer ) Item DMAC II Request Transfer Data Transfer Block Transfer Space Transfer Direction Transfer Mode Chained Transfer Function Interrupt At End Of Transfer Multiple Transfer Function Specification Interrupt request from all peripheral functions if the Interrupt Priority of the interrupt is set to level 7 Memory Memory (Memory to Memory Transfer) Immediate Data Memory (Immediate Data Transfer) Memory ( or Immediate Data ) + Memory Memory (Arithmetic Transfer) 8 bits or 16 bits 64 KByte space; addresses H 0000 to H FFFF Fixed or Incrementing; can be specified for the Source or Destination address Single or Burst transfer When the preceding transfer has completed its specified number of transfers (counter=0), then the DMAC II automatically begins next set of transfers. Interrupt is generated when transfer count reaches 0 A single Interrupt request causes multiple DMAC II transfers 12
Configuring the DMAC II Required data when performing Memory to Memory, Immediate, and Arithmetic Transfers 16-bit registers Transfer Mode Transfer Counter Transfer Source Address (or immediate Data) Operation Address 1 Transfer Destination Address Chained Transfer Address 2 Chained Transfer Address 2 End of Transfer Interrupt Address 3 End of Transfer Interrupt Address 3 (MOD) (SADR) (OADR) (DADR) (CADR0) (CADR1) 1. Data required only when using Arithmetic Transfer function 2. Data required only when using Chained Transfer function 3. Data required only when using End-of-Transfer interrupt Required data when performing Multiple Transfers Transfer Mode Transfer Counter Transfer Source Address ( or immediate Data ) Transfer Destination Address. (MOD) (SADR1) (DADR2). (COUNT) (IADR0) (IADR1) (COUNT) Base Address Transfer 2 Address Data Format for Chained Transfer Base Address Addr, transfer 2 Addr, transfer 3 Interrupt Vector Table Transfer Source Address ( or immediate Data ) Transfer Destination Address (SADR7) (DADR7) RAM 13
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Controller Area Network Function Implements a high-integrity, asynchronous, serial data communication bus for automotive and industrial applications FullCAN module fully compatible with Version 2.0B of the Bosch Specification Features include: 16 slots/message buffers/mailboxes Acceptance filter masks - One for mailboxes 0 to 13 - One each for mailboxes 14 and 15 1Mbps maximum baud rate Remote-frame automatic answering function Time-stamp function BasicCAN function by using mailboxes 14 and 15 Transmit abort Loop-back Error-clearing mode 15
CAN Implementation DATA BUS C0SLPR C0CTLR0,1 C0GMR0 to 4 C0EIMKR C0EISTR C0SLOT0_0 to 15 C0AFS C0BRP C0CONR C0LMAR0 to 4 C0SIMKR C0SIMKR C0SLOT1_0 to 15 f1 C0IDR C0MCTRL0 to 15 C0LMBR0 to 4 C0STR C0TEC C0REC Interrupt Control Circuit Interrupt Request CAN TX CAN RX CAN Protocol Controller, Version 2.0B Acceptance Filter 16-bit timer C0STR Message Mailbox 0 to 15 16
CAN0 Control s CAN0 Control 0 (C0CTRL0) Reset CAN module via bits RESET0 and RESET1 Loop-back mode BasicCAN / FullCAN Time-stamp functionality - Prescaler - Counter Reset Forced clearing of REC / TEC CAN0 Control 1 (C0CTRL1) CAN0 bank-select switch - Switches between Global Mask register Message-Slot Control register 17
Sleep, Status, ID s CAN0 Sleep Control Enters and Exits CAN Sleep Mode CAN0 Status Read-only register; shows the status of the CAN peripheral CAN0 Extended ID 16-bit register; specifies whether a mailbox will have a standard 11-bit identifier, or an extended 29-bit identifier 18
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CAN0 Configuration CAN0 Configuration Controls the timing parameters of the CAN bit time and the number of sample points. Nominal Bit Time / Bit Interval SAMPLE POINT(S) SJW SJW PROP_SEG PHASE_SEG 1 PHASE_SEG2 SYNC_SEG = 1 T q (Time Quantum): Smallest time unit defined by the CAN protocol; derived from the System Oscillator Period. 20
Pre-scaler, TEC, REC and COSTR CAN0 Baud Rate Pre-Scaler Determines the T q time, which is used to build-up CAN bit timing CAN0 Transmit Error Counter (TEC) Incremented/decremented in accordance with the CAN protocol CAN Receive Error Counter (REC) Incremented/decremented in accordance with the CAN protocol CAN0 Time-Stamp (C0STR) C0STR value is automatically stored into the message mailbox when a message is transmitted or received 21
Interrupt s CAN0 Slot Interrupt Mask Specifies whether a corresponding message mailbox will request or not request an interrupt. CAN0 Slot Interrupt Status Shows which mailbox was the source of the interrupt. CAN0 Error Interrupt Mask Enables / Disables interrupts: - Bus OFF - Error Passive - CAN BUS Error CAN0 Error Interrupt Status Shows the source of the interrupt. 22
Global/Local Mask s CAN0 Global Mask s C0GMR0 - - - STD ID10 STD ID9 STD ID8 STD ID7 STD ID6 C0GMR1 C0GMR2 C0GMR3 C0GMR4 - - STD ID5 STD ID4 - - - - ID13 ID12 - - ID11 ID5 ID10 ID4 STD ID3 ID17 ID9 ID3 STD ID2 ID16 ID8 ID2 STD ID1 ID15 ID7 ID1 STD ID0 ID14 ID6 ID0 Operate on Mailboxes 0 to 13 If a bit is set to 1, then the corresponding bit in the received message is checked. If a bit is cleared to 0, then the corresponding bit in the received message is not checked. For example: - If Global Mask s = all 0, messages with any ID will be accepted. - If Global Mask s = all 1, only messages with the exact ID of the mailbox will be accepted. CAN0 Local Mask A and B C0LMAR0 - C0LMAR4 C0LMBR0 - C0LMBR4 Operate on Mailbox 14 Operate on Mailbox 15 23
Slot Control CAN0 Message Slot Control Used to indicate or select CAN module has Transmitted / Received a message. CAN module is in the process of Transmitting / Receiving a message. Message Lost / Message Overrun. Can module has Transmitted / Received a Remote Frame. Automatic answering of Remote Frames. Acceptance of Remote Frames / Data Frames. Transmit / Receive Message Enable 24
Buffer s CAN0 Slot Buffer Select Mailbox and Buffer Slot is selected via this 8-bit register. MB8 MB4 MB2 MB1 MB8 MB4 MB2 MB1 SLOT BUFFER 1 SLOT BUFFER 0 CAN0 Message Slot Buffer s, 0 and 1 CAN0 Message Slot Buffer (0 / 1) Standard ID0 CAN0 Message Slot Buffer (0 / 1) Standard ID1 CAN0 Message Slot Buffer (0 / 1) Extended ID0 CAN0 Message Slot Buffer (0 / 1) Extended ID1 CAN0 Message Slot Buffer (0 / 1) Extended ID2 CAN0 Message Slot Buffer (0 / 1) Data Length Code CAN0 Message Slot Buffer (0 / 1) Data 0 to 7. CAN0 Message Slot Buffer (0 / 1) Time Stamp High CAN0 Message Slot Buffer (0 / 1) Time Stamp Low Example ----0000 : Access Mailbox 0 via Buffer 0 0101---- : Access Mailbox 5 via Buffer 1 25
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Course Summary Intelligent I/O DMAC II X-Y converter CAN 27