LSI/CSI UL A800 FEATURES: LSI Computer Systems, Inc. 1 Walt Whitman Road, Melville, NY 114 (1) 1-0400 FAX (1) 1-040 STEPPER MOTOR CONTROLLER Controls Bipolar and Unipolar Motors Cost-effective replacement for L in Bipolar applications Full, 1/, 1/4, 1/8, 1/1, 1/, step mode selected with mode inputs Direction control Reset input Step control input Enable input PWM chopper circuit for current control 8-bit PWM resolution Two peak current comparators with external reference input Step control frequency and duty cycle controlled by an external frequency source or by an internal crystal controlled oscillator (typically 8MHz) All inputs and outputs TTL/CMOS compatible (TTL for V operation) V to.v Operation (VDD - VSS). (DIP), -S (SOIC), -TS (TSSOP) - See Figure 1 - DESCRIPTION: The generates Phase Drive outputs and PWM outputs for controlling two phase Bipolar motors or four phase Unipolar motors, respectively. The contains a mode controlled look-up table for generating the motor duty cycle drive sequences. There are four outputs which are used to drive two H- Bridges for the two motor windings in the Bipolar motor or the four Driver Transistors for the two center-tapped windings in the Unipolar motor (Refer to Table ). The can step a motor in full steps, half steps or in 1/4, 1/8, 1/1 or 1/ microsteps. The uses microstepping phase controls for each motor step in half step or in 1/4, 1/8, 1/1 or 1/ microsteps. The uses stepping as shown in Table for full step control. A table pointer is used which is incremented or decremented by a value determined by the operating mode and the direction control. The 8-bit PWM control and the refresh rate are set using an internal oscillator controlled by a crystal or by use of an external input clock. Typical refresh rate is equal to 1.kHz. Peak current feedback control using pulse width modulation chopping can only be used in full-step or half-step modes. The chopper consists of a voltage comparator, flip-flop and external sense resistor. The internal oscillator sets the flip-flop and enables the and INH outputs at the beginning of each PWM cycle. Once the peak motor current causes the voltage across the sense resistors to reach the voltage set by, the outputs are disabled until the next oscillator pulse. The voltage sets the peak current in each motor winding. In all other modes, the input should be set to VDD and the sense inputs should be grounded. INPUT/OUTPUT DESCRIPTION RESET Input Active low. Resets the PWM table pointer to HOME position per Table and brings and INH low. Upon power-up, a POR circuit also resets the PWM table pointer. Input Active low. When high (inactive), brings,,,, and INH outputs low. STEP Input Active low. A low-going pulse on this input causes the motor to advance one step. M0 M1 M RESET STEP FRD/REV HOME Rx CLK Cx VSS PIN ASSIGNMENT TOP VIEW July 00 FRD/RVRS Input A low input causes the motor to move in decremental steps per Table. A high input causes the motor to move in incremental steps per Table Switching directions can occur at any time. M0, M1, M Inputs Defines the stepping modes as follows: M M1 M0 full step mode 0 0 0 1/ step mode 0 0 1 1/4 step mode 0 1 0 1/8 step mode 0 1 1 1/1 step mode 1 0 0 1/ step mode 1 0 1 1/ step mode 1 1 0 1/ step mode 1 1 1 1 4 8 11 1 Stepping Mode can be changed at any time. LSI FIGURE 1 SENSE1 / SENSE Inputs SENSE1 is the input for the voltage across the sense resistor determined by the current in the motor winding driven by the and power stages. SENSE is the input for the voltage across the sense resistor determined by the current in the motor winding driven by the and power stages. Input External voltage reference for current control comparators. 4 1 0 1 18 1 1 1 14 1 V DD INH DS1 DS0 SENSE1 SENSE 0-0-1
Rx, Cx, CLK These three pins can be configured in one of three ways to obtain the primary clock. A crystal connected between Rx and CLK pins or a resistor-capacitor pair connected among all three pins (see Figure 4) can make use of the internal oscillator. Alternatively, the CLK pin can be driven from an external clock source. DS0 / DS1 Inputs The phase drive is blanked out between steps by switching outputs and INH low in order to reduce audible noise and power consumption. The duration of the blanking is selected by DS0 and DS1 according to Table 1 / / / Outputs The state of these phase outputs are determined by the look-up table and are used to control either the left or right half of each of the H- Bridge drivers. A low on a phase output enables the bottom driver while a high on the output enables the top driver. HOME Output Indicates Step0 state per Table with a logic low. / INH Outputs These outputs are used to provide PWM control to each of the two H- Bridge drivers. Table 1 DS1 DS0 Blanking Time, IPB, at fc = 8MHz 0 0 1.us 0 1.0us 1 0.us 1 1.00us The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. (+V ) 4 V DD M0 M1 1 MODE SELECT M RESET STEP FRD/RVRS 4 LOOK-UP TABLE OUTPUT CONTROL LOGIC 1 0 INH HOME 8 1 RX 18 CLK OSCILLATOR 1 DS0 C X 11 + - + - 1 1 DS1 SENSE1 14 SENSE V SS 1 (-V ) 1 FIGURE. BLOCK DIAGRAM 0-00-
ABSOLUTE MAXIMUM RATINGS: PARAMETER SYMBOL VALUE UNIT DC Supply Voltage VDD - VSS + V Any Input Voltage VIN VSS - 0. to VDD +0. V Operating Temperature TA -0 to +8 C Storage Temperature TSTG -8 to +10 C ELECTRICAL SPECIFICATIONS (- C < TA < +8 C) PARAMETER SYMBOL MIN TYP MAX UNIT CONDITIONS Supply Voltage VDD.0 -. V - Supply Current IDD -.0 ma Outputs floating, Inputs high CLK frequency fc - 8.00 - MHz - Enable Propagation Delay tepd 0 - - ns - FRD / RVRS Setup Time tds 0 - - us - (before step pulse) Step Pulse Width SPW 1.0 - - us at fc = 8 MHz Interstep Pulse Delay ISD - - us at fc = 8 MHz Interstep Phase Blanking IPB 1. -.0 us at fc = 8 MHz Reset Pulse Width RPW 1.0 - - us at fc = 8 MHz Reset to Step Pulse Delay trs 0 - - us - Hi-Level Input Voltage ViH - - V VDD = ± 0.V Low-Level Input Voltage VIL - - 0.8 V VDD = ± 0.V Hi-Level Input Current IH - - 0 na Leakage Current Low-Level Input Current IL - - 0 na Leakage Current Output Sink Current Io - - - ma Vo = 0.4V, VDD = V Io - - - ma Vo = 0.4V, VDD =.V Output Source Current Io - - ma Vo = 4.0V, VDD = V Io. - - ma Vo =.V, VDD =.V Comparator Offset Voltage VOS - 1 mv = 1V Input Reference Voltage 0. -.0 V VDD = V 0. - 1. V VDD =.V +V 4 VDD RX fc ~ 1/RC R CLK C At VDD = V and R =.k, C = 1pF, oscillator frequency is 8MHz (typical) 11 CX VSS 1 FIGURE. RC OSCILLATOR FOR CLOCK GENERATOR 0-1108-
RESET RPW STEP SPW IPB IPB INH IPB IPB PWM HOME FIGURE 4. PARTIAL SEQUENCE IN FORWARD 1/ STEP MODE 0-01140-4
V VM 4 4 1 M0 M1 M VDD INH 11 INH MCU 4 RESET STEP FRD/RVRS 1 0 1 18 1 L8 1 14 STEPPER MOTOR WINDINGS pf R X M CLK pf 1 VSS SENSE1 SENSE 1 14 1 0 0 1 1 8 0.01uF 0.01uF FIGURE. TYPICAL APPLICATION SCHEMATIC FOR A TWO SE BIPOLAR MOTOR USING A SINGLE MOTOR DRIVER IC 0-0008-
V V M MCU 1 4 4 VDD M0 M1 M RESET STEP FRD/RVRS 1 IN1 0 IN1 0nF L01 L01PS L0 L0 VS BOOT1 OUT1 BOOT OUT SENSE 1nF 1nF MOTOR WINDINGS GND pf M pf R X CLK INH 1 18 0nF IN1 IN1 L01 L01PS L0 L0 VS BOOT1 OUT1 BOOT 1nF 1nF MOTOR WINDINGS OUT SENSE GND 1 VSS SENSE1 SENSE 1 14 1 0.01uF 0 0 0.01uF R R FIGURE. TYPICAL APPLICATION SCHEMATIC FOR A TWO SE BIPOLAR MOTOR USING TWO SEPARATE MOTOR DRIVER ICs 0-0-
V V M MCU 1 4 4 M0 VDD M1 M RESET STEP SENSE1 FRD/RVRS 1 0 1 1 4 4HC08 Q1 Q 0 R 0.01uF pf RX M V M pf CLK INH 1 18 1 1 Q 8 4HC08 11 Q4 1 VSS SENSE 14 1 0 0.01uF R NOTE: Q1, Q, Q, Q4 are MOSFET Power Transistors suitable for V Gate Drive Typical P/Ns = IRLZ44N and IRF08 FIGURE. TYPICAL APPLICATION SCHEMATIC FOR A FOUR SE UNIPOLAR MOTOR USING DISCRETE MOSFET TRANSISTORS 0-0008-
TABLE Step Number % Duty Cycle Phases Full 1/ 1/4 1/8 1/1 1/ INH Step Angle 0 0 0 0 0 0 0.0 0.0 1 0 1 0 HOME 1. 4. 1 0 1 0.81 1..8 1 0 1 0. 8. 14. 1 0 1 0 8.44 1 4 8.1 1. 1 0 1 0 11..0 4. 1 0 1 0 14.0..0 1 0 1 0 1.88 4.. 1 0 1 0 1. 1 4 8.4 8. 1 0 1 0.0 0.4 4.8 1 0 1 0.1 88. 4.1 1 0 1 0 8.1 11 8.8 1.4 1 0 1 0 0.4 1 8.1. 1 0 1 0. 1 80.. 1 0 1 0. 14..4 1 0 1 0.8 1 4.1. 1 0 1 0 4.1 1 4 8 1 0. 0. 1 0 1 0 4.00 1. 4.1 1 0 1 0 4.81 18.4. 1 0 1 0 0. 1. 80. 1 0 1 0.44 0. 8.1 1 0 1 0. 1 1.4 8.8 1 0 1 0.0 11 4.1 88. 1 0 1 0 1.88 4.8 0.4 1 0 1 0 4. 1 4 8..4 1 0 1 0.0. 4. 1 0 1 0 0.1 1.0. 1 0 1 0.1 4..0 1 0 1 0.4 14 8 1. 8.1 1 0 1 0 8. 14. 8. 1 0 1 0 81. 1 0.8. 1 0 1 0 84.8 1 4.. 1 0 1 0 8.1 1 4 8 1 0.0 0.0 0 1 1 0 0.00-4.. 0 1 1 0.81 1 4 -.8. 0 1 1 0. -14. 8. 0 1 1 0 8.44 18-1. 8.1 0 1 1 0 1. -4..0 0 1 1 0 4.0 1 8 -.0. 0 1 1 0.88 0-00-8
TABLE (continued) Step Number % Duty Cycle Phases Full 1/ 1/4 1/8 1/1 1/ INH Step Angle -. 4. 0 1 1 0. 0 40-8..4 0 1 1 0 11.0 41-4.8 0.4 0 1 1 0 11.1 1 4-4.1 88. 0 1 1 0 118.1 4-1.4 8.8 0 1 1 0 10.4 11 44 -. 8.1 0 1 1 0 1. 4 -. 80. 0 1 1 0 1. 4 -.4. 0 1 1 0 1.8 4 -. 4.1 0 1 1 0 1.1 1 4 48-0. 0. 0 1 1 0 1.00 4-4.1. 0 1 1 0 1.81 0 -..4 0 1 1 0 140. 1-80.. 0 1 1 0 14.44 1-8.1. 0 1 1 0 14. -8.8 1.4 0 1 1 0 14.0 4-88. 4.1 0 1 1 0 11.88-0.4 4.8 0 1 1 0 14. 14 8 -.4 8. 0 1 1 0 1.0-4.. 0 1 1 0 10.1 8 -..0 0 1 1 0 1.1 -.0 4. 0 1 1 0 1.4 1 0 0-8.1 1. 0 1 1 0 18. 1-8. 14. 0 1 1 0 11. 1 -..8 0 1 1 0 14.8 -. 4. 0 1 1 0 1.1 4 8 1 4-0.0 0.0 0 1 0 1 180.00 -. -4. 0 1 0 1 18.81 -. -.8 0 1 0 1 18. -8. -14. 0 1 0 1 188.44 1 4 8-8.1-1. 0 1 0 1 11. -.0-4. 0 1 0 1 14.0 0 -. -.0 0 1 0 1 1.88 1-4. -. 0 1 0 1 1. 18 -.4-8. 0 1 0 1 0.0-0.4-4.8 0 1 0 1 0.1 4-88. -4.1 0 1 0 1 08.1-8.8-1.4 0 1 0 1.4 1 8-8.1 -. 0 1 0 1 1. -80. -. 0 1 0 1 1. 8 -. -.4 0 1 0 1 1.8-4.1 -. 0 1 0 1.1 0 40 80-0. -0. 0 1 0 1.00 81 -. -4.1 0 1 0 1.81 41 8 -.4 -. 0 1 0 1 0. 8 -. -80. 0 1 0 1.44 0-00-
TABLE (continued) Step Number % Duty Cycle Phases Full 1/ 1/4 1/8 1/1 1/ INH Step Angle 1 4 84 -. -8.1 0 1 0 1. 8-1.4-8.8 0 1 0 1.0 4 8-4.1-88. 0 1 0 1 41.88 8-4.8-0.4 0 1 0 1 44. 11 44 88-8. -.4 0 1 0 1 4.0 8 -. -4. 0 1 0 1 0.1 4 0 -.0 -. 0 1 0 1.1 1-4. -.0 0 1 0 1.4 4-1. -8.1 0 1 0 1 8. -14. -8. 0 1 0 1 1. 4 4 -.8 -. 0 1 0 1 4.8-4. -. 0 1 0 1.1 1 4 48 0.0-0 1 0 0 1 0.00 4. -. 1 0 0 1.81 4 8.8 -. 1 0 0 1. 14. -8. 1 0 0 1 8.44 0 0 1. -8.1 1 0 0 1 81. 1 4. -.0 1 0 0 1 84.0 1.0 -. 1 0 0 1 8.88. -4. 1 0 0 1 8. 1 4 8. -.4 1 0 0 1.0 4.8-0.4 1 0 0 1.1 4.1-88. 1 0 0 1 8.1 1.4-8.8 1 0 0 1 00.4 4 8. -8.1 1 0 0 1 0.. -80. 1 0 0 1 0. 1.4 -. 1 0 0 1 0.8 111. -4.1 1 0 0 1 1.1 14 8 11 0. -0. 1 0 0 1 1.00 11 4.1 -. 1 0 0 1 1.81 114. -.4 1 0 0 1 0. 11 80. -. 1 0 0 1.44 8 11 8.1 -. 1 0 0 1. 11 8.8-1.4 1 0 0 1.0 118 88. -4.1 1 0 0 1 1.88 11 0.4-4.8 1 0 0 1 4. 1 0 0 10.4-8. 1 0 0 1.0 11 4. -. 1 0 0 1 40.1 1 1. -.0 1 0 0 1 4.1 1.0-4. 1 0 0 1 4. 1 14 8.1-1. 1 0 0 1 48. 1 8. -14. 1 0 0 1 1. 1. -.8 1 0 0 1 4.8 1. -4. 1 0 0 1.1 0 0 0 0 0 0 0.0 0.0 1 0 1 0 HOME 0-00-
SLOW / FAST L8 1 0 FIGURE 8. Selecting Between Fast and Slow Decay for One Stepper Motor Winding (Use identical circuit for the other stepper motor winding) NOTE: In fast decay mode, inhibit windings are chopped. In slow decay mode mode, phase windings are chopped NOR Gates: CD4001 OR Gates: CD401 0-010-11
VM = 10V 1 (1 ) 1N8 1k Q1 1N400 Q 1k 1N8 k k MOTOR WINDING N1 N1 k 0 (18) 1N400 Q Q4 () k SENSE1 1 (14) Inverters = 4HC04 Gates = 4HC08 Q1 = Q = IRF18 (Typical) Q = Q4 = IRF1(Typical) FIGURE. 10V Motor Discrete Component Driver 0-010-1