Monolithically integrated InGaAs nanowires on 3D structured silicon-on-insulator as a new platform for full optical links Hyunseok Kim 1, Alan C. Farrell 1, Pradeep Senanayake 1, Wook-Jae Lee 1,* & Diana. L. Huffaker 1,2 1 Department of Electrical Engineering, University of California Los Angeles, Los Angeles, California 90095, United States 2 California Nano-Systems Institute, University of California Los Angeles, Los Angeles, California 90095, United States 1
Supporting Information S1. Sample preparation processes A lightly p-doped (Boron, 10.cm) 6-inch SOI (111) wafer (SEH America Inc., USA) with an SOI layer thickness of 2 m, a buried oxide layer thickness of 2 m, and a Si handling layer thickness of 675 m is used for the nanowire growth. Wafer thinning. The wafer thinning process is necessary if the SOI layer of a bare SOI wafer is thicker than the desired SOI layer thickness. We adopted thermal oxidation process to reduce the thickness of the SOI layer, because other thinning processes such as wet chemical etching and dry etching typically degrade the surface roughness of the SOI layer. A bare SOI wafer is first cleaned using a piranha solution (4:1 H2SO4:H2O2) for 15 min at 120 ⁰C to remove organic contaminants. The wafer is then loaded into a furnace (TYTAN mini 3600, Tystar Co., USA) for thermal oxidation. Following the wet oxidation carried out at 1050 ⁰C (Fig. S1(b)), the as-grown thermal oxide is removed using a 6:1 buffered oxide etch (BOE) solution. The final SOI layer thickness is precisely controlled to be 220 nm, as shown in Fig. S1(c). (b) (a) (c) (d) (g) (h) E-beam resist Si SiO2 Si (d) (f) Si3N4 nanowires Figure S1. Fabrication process for InGaAs nanowires on SOI platform. 2
3D structure patterning. 3D structures including waveguides, gratings, and alignment markers are patterned on the thinned SOI layer by e-beam lithography and dry etching processes. First, e- beam resist, ZEP520A (ZEON Co., Japan) diluted with ZEP-A (ZEON Co., Japan) by the ratio of 2:1, is spin-coated on the thinned SOI wafer, followed by e-beam lithography using e-beam writer (Vistec EBPG 5000+, Vistec Electron Beam GmbH, Germany) and developing using ZED-N50 (ZEON Co., Japan), as shown in Fig. S1(d). Then, dry etching is carried out using the e-beam resist as an etch-mask. The SOI layer is etched using an ICP etcher (Oxford 80Plus, Oxford instruments, UK) by flowing 10 sccm of SF6, 25 sccm of CHF3, and 2 sccm of O2 under the RF power of 200 W and the chamber pressure of 30 mtorr. The depth of the trench is controlled to be 180 nm. The etch-mask is removed after the dry etching, as shown in Fig. S1(e), by N-Methyl-2-pyrrolidone (NMP) rinsing and piranha cleaning. Growth mask patterning. A dielectric mask is required to control the position of nanowires in selective-area epitaxy. First, a 20 nm-thick Si3N4 film is deposited using low-pressure chemical vapor deposition (LPCVD) (Tystar 17, Tystar Co., USA) at 800 ⁰C on the 3D structured SOI wafer (Fig. S1(f)). E-beam resist, ZEP520A diluted with ZEP-A by the ratio of 1:2, is then spin-coated on the wafer. The dilution ratio is different from the e-beam resist employed for the 3D structure patterning, because the nanohole size is on the order of tens of nanometers, requiring thinner e- beam resist for fine patterning. Next, e-beam writing is carried out to pattern nanoholes, employing the alignment markers patterned on the substrate to precisely align the position of the nanoholes on the 3D structures. The alignment error was less than 20 nm in our system. After developing the e-beam resist using ZED N-50, dry etching is carried out to expose nanoholes on the Si3N4 mask. The Si3N4 mask is patterned using an ICP etcher (Oxford 80Plus) by flowing 98 sccm of CHF3 and 2 sccm of O2 under the RF power of 50 W and the chamber pressure of 35 mtorr. 3
Sample preparation for growth. Following the growth mask patterning, the 6-inch wafer is diced into square-shaped samples with the size of 8 mm 8 mm for the growth. After the dicing, the resist is stripped by N-Methyl-2-pyrrolidone (NMP) rinsing and piranha cleaning, as shown in Fig. 1(g). Right before loading the sample into the MOCVD reactor, the native oxide on the exposed Si is stripped using a 6:1 BOE solution for 30 seconds, and rinsed using deionized water for 20 seconds followed by drying with compressed nitrogen gas. S2. Temperature-dependent photoluminescence of InGaAs nanowires Room-temperature photoluminescence (PL) spectra of InGaAs nanowires grown on SOI substrates are compared with PL spectra measured at cryogenic temperature to demonstrate optical properties of the nanowires. Nanowire arrays grown under different In and Ga flow rates are optically pumped using a diode laser with a 660 nm peak wavelength and an average pump power of 900 W. The emission spectra are measured using Fourier transform infrared spectroscopy under nitrogen condition in order to prevent CO2 and H2O absorption. The PL spectra of an In0.32Ga0.68As nanowire array and an In0.68Ga0.32As nanowire array measured at 77 K and room temperature are shown in Fig. S2. The peak intensities of nanowire arrays measured at 77 K are normalized for comparison with the spectra at 300 K. As the temperature increases from 77 K to 300 K, the emission of both Ga-rich and In-rich InGaAs nanowire arrays red-shifts and broadens, which are typical features originating from the change of the bandgap and the thermal excitation of electrons. It should be highlighted that the peak emission intensities of both In0.32Ga0.68As and In0.68Ga0.32As nanowires at 300 K are still ~25 % compared with 77 K measurements, which explicitly shows that the proposed platform can be potentially used for room-temperature 4
Figure S2. PL spectra of an In 0.32 Ga 0.68 As and an In 0.64 Ga 0.36 As arrays measured at 77 K and room temperature. The peak intensities of nanowire arrays measured at 77 K are normalized to 100 for comparison with the spectra at 300K. applications. Passivating the surface of nanowires with larger bandgap materials can further improve the emission properties of InGaAs nanowires by suppressing non-radiative surface recombination. S3. Pump power-dependent PL intensity of InGaAs nanowires A single InGaAs nanowire and a nanowire array with 500 nm pitch are optically pumped with various pump powers to investigate emission characteristics. A 660 nm pulsed laser is used as a pump source, and the emission spectra are measured using an InGaAs focal plane array detector at room temperature. The pump power is varied from 1.67 W to 3270 W, and Fig. S3(a) shows the PL spectra of the nanowire array at several pump powers as an example. The light-light (LL) curves of the nanowire array and the single nanowire are depicted in Fig. S3(b), where the integrated PL intensity (y-axis) is derived by integrating the emission spectra. 5
As shown in Fig. S3(b), the output intensity linearly increases with the pump power until it saturates due to the heating of the nanowires, which is a common aspect of optically pumped emitters. Interestingly, the saturation pump power of the single nanowire is 3110 W, which is about twice higher than that of the nanowire array (1570 W). These saturation pump powers of 3110 W and 1570 W correspond to the pump power densities of 15.8 kw/cm 2 and 8.0 kw/cm 2, respectively, assuming that the beam spot size is 5 m. This difference can be explained by the dissipation of heat accumulated in nanowires. The dissipation of heat from each nanowire in a densely packed nanowire array is not as effective as a single nanowire standing alone with no nearby structure, and this results in higher nanowire array temperature compared with the case of a single nanowire pumped with the same intensity. This local heating makes the saturation pump power of the nanowire array lower than the single nanowire. Although the quantum efficiency of the InGaAs nanowires cannot be directly derived because the collection efficiency of the objective lens and the responsivity of the detector are unknown, the linear increase of the emission intensity (a) 300 K (b) 10 Figure S3. (a) Photoluminescence spectra of an InGaAs nanowire array with various pump powers measured at room temperature. (b) LL curves of an InGaAs nanowire array and a single nanowire. The PL intensity of the single nanowire is magnified 10 times for visibility. 6
with the pump power density up to 15.8 kw/cm 2 at room temperature implies good optical properties of the nanowire. S4. Pump power-dependent spectral linewidth of InGaAs nanowires The material quality of InGaAs nanowires can be inferred from the spectral linewidth of the emission spectra. To evaluate the material quality, the full-width at half-maximum (FWHM) is calculated from room-temperature PL spectra of an InGaAs nanowire array, which are measured and shown in the previous section (S3). The emission spectra shown in Fig. S3(a) is normalized in Fig. S4(a) for comparison, which clearly show that the emission from the nanowires broadens as the pump power increases. The FWHM is calculated from the pump power of 16.8 W to the pump power of 3270 W, as the emission spectra are too noisy to calculate the FWHM when the pump power is below 16.8 W. The FWHM is 98 mev when the pump power is 16.8 W, which increases with the pump power due to the sample heating and the band filling effect, as shown in Fig. S4(b). Theoretically the FWHM of bulk InGaAs at room temperature is between 64 mev (a) 300 K (b) Figure S4. (a) Normalized PL spectra of an InGaAs nanowire array with various pump powers measured at room temperature. (b) Spectral linewidths of the InGaAs nanowire array as a function of pump power. 7
(2.5kbT) and 77 mev (3kbT). Although the FWHM of 98 mev at low pump power is around 21 34 mev wider than bulk InGaAs, the discrepancy is not significant, implying the reasonably good material quality of InGaAs nanowires. Possible reasons for the broader linewidth of nanowires compared with bulk InGaAs include In/Ga composition inhomogeneity, zinc-blende/wurtzite polytypism, and ionized impurity scattering. S5. Difference between InGaAs nanowires grown on SOI and bulk Si substrates In the case of the III-V film growth on Si, a compliant SOI substrate instead of a Si substrate is known to improve the quality of the epitaxial layer grown on top by releasing the strain. To the best of our knowledge, however, there has been no report yet about the effect of compliant layers on the growth and material properties in the case of nanowires grown by selective-area epitaxy. SEM images of InGaAs nanowire arrays grown on bulk Si and SOI are shown in Fig. S5(a) and (b), respectively. These two samples are loaded together in the MOCVD reactor to ensure that the growth condition is exactly same for the two samples. The diameter and the height of the nanowires grown on Si are 308 nm and 1880 nm, while the nanowires grown on SOI have smaller size with (a) (b) (c) 300 K Figure S5. (a-b) SEM images of InGaAs nanowires grown on (a) bulk Si and (b) SOI. All images are tilted 30 from normal view and scale-bars represent 500 nm. (c) Room-temperature PL of InGaAs nanowires grown on Si and SOI. 8
the diameter of 270 nm and the height of 1730 nm. The difference in the size of the nanowires is thought to be from the insulating SiO2 layer of the SOI substrate, which makes the temperature of the surface of the SOI substrate different from the surface of bulk Si during the MOCVD growth. Interestingly, even though the volume of each nanowire grown on Si is around 40 % larger than the nanowires on SOI, the PL intensity of the nanowire array on Si is around 7 % lower than the nanowire array on SOI, as shown in Fig. S5(c). This implies that the material quality of InGaAs nanowires on SOI is superior to InGaAs nanowires on Si. We speculate that the compliant SOI substrate decreases the misfit dislocation density of the substrate-nanowire interface, in a similar way to the case of the film growth. However, further study is necessary to verify this speculation. 9