DESIGN OF CURRENT CONVEYOR USING OPERATIONAL AMPLIFIER Nidhi 1, Narender kumar 2 1 M.tech scholar, 2 Assistant Professor, Deptt. of ECE BRCMCET, Bahal 1 nidhibajaj44@g mail.com Abstract-- The paper focuses on design and implementation of current-mode second-generation current conveyors (CCIIs).Designing high performance analog circuits is becoming increasingly challenging with the persistent trend towards reduced supply voltages. Low voltage and Low power mixed mode circuit design and current mode circuits (CMCs) fulfill this need very well.in this paper a general method for converting an operational amplifier into a second-generation current conveyor is used. This method applies to a wide variety of types of op-amps. It is illustrated by an in-depth analysis of a current conveyor constructed from a simple two-stage op-amp with compensation.the circuit uses four operational amplifiers and the resulting current conveyors have a low impedance X-input, high impedance Y-input. Results are confirmed using TSPICE. Keywords: Index Terms Current conveyors, conventional Op-amp, I. INTRODUCTION The current conveyor (CC) is the basic building block of a number of contemporary applications both in the current and the mixed modes.the current conveyor is receiving considerableattention as they offer analog designers some significant advantages over the conventional op-amp[1-2]. These advantages can be pointed out as follows: Improve AC performance with better linearity. Wider and nearly constant bandwidth independent of closed loop gain. Relatively High slew rate Flexibility of driving current or voltage signal output at its two separate nodes, hence suitable for current and voltage mode devices. Reduced supply voltage of integrated circuits. Accurate port transfer ratios equal to unity hence employed in low sensitivity design. The second generation current conveyor CCII introduced by Sedra and Smith [8] is widely used in realization of filters and oscillators [11-12]. Diagram shows the black box representation of the current conveyor [8] Figure 1.1: Black box representation of the basic current conveyor. Basic function of each port is shown below: Port x: here port x is a hybrid port and functions as input port for current signals and output port for voltage signals at the same time. Port y: This port is a voltage input port Port z: This port is a current output port, which can either sink or source current equal to the current injected into port x. If port y is connected to a potential V an equal voltage will appear on the port x and if a current I is forced through port x, an equal current will flow through port y (depending upon the nature of the CC). The same current I, the sign of which is governed by the current transfer characteristics, is also conveyed and supplied through output port z at a high impedance level in the manner of a current source and so the output current remains unaffected by the load. The potential at port x is independent of the current I forced into x and the current I through port y is independent of the voltage V applied to y. Thus the device exhibits a virtual short circuit input characteristic at port x and a dual virtual open-circuit input characteristic at port y [8]. Today, the current conveyor is considered a universal analog building block with wide spread applications in the current/voltage/mixed mode signal processing. Its features find most applications in the current mode, when its socalled voltage input y is grounded and the current, flowing into the low-impedance input x, is copied by a simple current mirror into the z output. The relation between the currents and voltages at various ports can be summarized as ISSN 2278-5787 Page 32
where i x (v x ), i y (v y ), and i z (v y ) are the currents(voltages) at ports x, y, and z respectively. b characterizes their current Supply VDD 2.5V transfer from x to z and a is related to the nature of the conveyor as below. VSS -2.5V b > 0, the circuit is a positive transfer conveyor (CC+) b < 0, the circuit is a negative transfer conveyor(cc-). Gain Bandwidth 5MHz a = 1, the circuit is a first generation current conveyor (CCI)[ 7] Gain 5000V/V a = 0, the circuit is a second generation current conveyor (CCII)[8] Settling Time 1u Sec a = -1, the circuit is a third generation current conveyor (CCIII) [9]. Slew Rate 10V/uSec It is desired that a CC should have large bandwidth and consume low quiescent power. Ideally a CC should have Input common Mode Range -1V to 2V Infinite input impedance (Rin) at port y. Zero input impedance (Rx) at port x for current inputs. Infinite output Power dissipation 2V impedance (Rout) at port z. The schematic of the op amp is given in figure 2.1. We adopted a common procedure to design the op amp. The procedure is given below: II. BLOCK DIAGRAM OF TWO STAGE AMPLIFIER The main constraints in the design are the requirement of low power consumption & stability. Schematic of the two stage op amp with Miller Compensation scheme[4,6] is shown in the figure 4.1 1. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60 phase margin we use the following relationship. This assumes that z 10GB. Cc > 0.22CL Figure 2.1 Schematic of miller compensated two stage Op amp This op amp is designed using TSMC 0.35µm technology. The value of the load capacitance is taken as 10pf. Various specifications for the parameters are described below: III. DESIGN OF TWO STAGE OPERATIONAL AMPLIFIER: Table 3.1: Custom Design Specifications of the amplifier 2. Determine the minimum value for the tail current (I 5 ) from the largest of the two values. I5=SR C C 3. Design for S3 from the maximum input voltage specification. S 3,4 = I5/ K' 3 [VDD Vin(max) VT0 3 (max) - VT 1 (min)] 2 4. Now we can check the value of the mirror pole, p3, to make sure that it is in fact greater than 10GB. The mirror pole can be found as P3= gm 3 /2Cgs 3 = - (2K ps 3 I 3 ) 1/2 / 2W 3 L 3 (O.667)C OX 5. Now Find gm 1 gm 1 = (C C )(BW) Therefore (W/L) 1,2 = gm 12 /2K N 1 (4 6. Calculate VDSS VDS 5 (sat) = Vin(min) VSS- (I5/β 1 ) 1/2 -VT 1 (max) ( Therefore S 5 = 2I 5 / K 5 [VDS 5 (sat)] 2 7. FOR 60 phase margin We Know That gm 6 10gm 1 ( calculate the value of S6 From gm6 & gm4 S6 = S4(gm 6 /gm 4 ) (4.10) 8. Calculate I 6 from I 6 = (gm 6 ) 2 /2K' 6 S 6 (4 Design S7 to achieve the desired current ratios between I5 &I6 S7 = (I 6 /I 5 )S 5 (4 9. Check again the gain & power dissipation Av= 2gm 2 gm 6 / I5(λ 2 + λ 3 )I6(λ 6 + λ 7 ) (4 P diss = (I 5 + I 6 )(VDD +VSS) (4 Specification Names Values Table: 3.2Transistor sizing of the circuit is given below ISSN 2278-5787 Page 33
Sr. No. Transistor lengths Transistor widths 1 L1 = 1u W1 = 4u S1= 4 International Journal of Technical Research (IJTR) W/L ratios single end and GND. In figure 4.1, one method of measuring the AC performance is presented. In this configuration, the amplifier is open loop, and the AC. 2 L2 = 1u W2 = 4u S2= 4 3 L3 = 1u W3 = 14u S3=14 4 L4 = 1u W4 = 14u S4=14 5 L5 = 1u W5 = 3.5u S5=3.5 6 L6 = 1u W6= 90u S6=90 7 L7 = 1u W7=16 u S7=16 8 L8 = 1u W8= 3.5u S7=3.5 Figure 4.1 Configuration for simulating the open loop frequency response of op-amp 4.2 Simulation Result of AC Analysis 3.1Symbol Mode of Two Stage Op Amp With Miller Compensation Now we have created the symbol mode of op amp. And the symbol mode of op-amp as shown in fig.4.2 Figure 4.2 Frequency response of op-amp Figure 2.2: Symbol of miller compensated two stage Op amp Prepared circuit of amplifier is simulated at tanner tool at 0.35µm technology. The amplifier is to be powered from a 2.5volts power supply. All values have been measured at load capacitance of 10pF.The simulations include AC response, Transient analysis, DC response Analysis. This design provided an overall with Unity gain bandwidth is 5.9 MHz The phase margin comes out to be nearly 65º making design relatively stable. This design provided an overall with Unity all gain 5727V/V 4.3 TRANSIENT ANALYSIS In figure 4.2, a step from ground to VDD is applied at the input with unity feedback configuration. IV. SIMULATION & RESULT 4.1 AC RESPONSE This response is used for observing open loop gain, Unity Gain Bandwidth (UGB), 3 -db bandwidth and the Phase Margin of the circuit. In the test setup a differential AC signal of 1V is applied to the inputs along with this the dc bias potential is also applied. The output was taken between ISSN 2278-5787 Page 34
Figure 4.3 Schematic for the simulation and measurement of the slew rate 4.4 Simulation Result of Transient Analysis The amplifier s slew rate is 9.2V/μs for the rising edge and 1.5V/µs for the falling edge. Figure 4.4 Slew rate for the rising and falling edge with opamp in unity gain configuration 4.5DC ANALYSIS DC analysis of the circuit provides the ICMR. This test is performed to test the offset voltage and the input common mode range of the op-amp that is the range of op-amp for which there is a linear relationship between input and the output.figure 4.6 shows the setup of simulating ICMR opamp is in unity gain configuration and at non-inverting terminal dc voltage sweep from -2.5 to 2.5 is applied. Figure 4.6 Result for the DC Analysis Table4.1: Simulation of the amplifier Specification Names Gain Bandwidth Gain Slew Rate Input common Mode Range Values 5.9MHz 5727V/V 9.2V/uSec -2.3 to +1.6V Phase margin 65 0 Gain margin Power dissipation 75DB 0.835mV 4.7 DESIGN& SIMULATION OF CURRENT CONVEYOR USING OP AMP: We have designed current conveyor operational amplifiers. We have used four operational amplifiers fig. 4.7 shows the schematic of current conveyor II[10] Figure 4.5 Schematic for the DC Analysis 4.6Simulation Result of DC Analysis ISSN 2278-5787 Page 35
[2] B. Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill, 2002. [3] www.ece.unm/-payman/classes/ece638/tspice.pdf [4] R. G. H. Eschauzier and J. H. Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers, Boston: Kluwer, 1995. [5] Sedra and Smith(1998),A. S. Sedra and K. C. Smith, Micro Electronics Circuits, pp. 613-616. New York: Oxford University Press, fourth edition, 1998. [6] G. Palmisano and G. Palumbo., A Compensation Strategy for Two-Stage CMOS Op- Amps Based on Current Buffer. IEEE Trans. on Circuits and Systems (part I) 44(3), pp. 257 262, Mar. 1997. [7] SMITH, K.C., SEDRA, A. The current conveyor: a new circuit building block. IEEE Proc. CAS, vol. 56, no. 3, p. 1368-1369, 1968. [8] SEDRA, A.S., SMITH, K.C. A second generation current conveyor and its application. IEEE Trans.,CT- 17, p. 132-134,1970. [9] FABRE, A. Third generation current conveyor: A new helpful active element. Electron. Lett., vol. 31, no. 5, p. 338 339, 1995 [10]Huertas, J. L., Circuit implementation of current conveyor Electronics Letters., vol. 16, pp. 225-226, 1980. [11]Khan, I.A., and Jaidi, H., Mehmood, Multifunctional Figure 4.7: Schematic of Current Conveyor using two translinear-c-current mode filter Int. J. Electronics, stage Op amp. vol.87, no.9, pp.1047-1051, 2000. [12]Minaei & Tuskog New current-mode current-controlled universal filter with single input and three outputs JEE, vol. 88, no. 3 pp. 333-337, (2001). Figure 4.8 Frequency response of current conveyor II V. CONCLUSION In this paper a current conveyor is designed using two stage high gain low power operational amplifier. In the design of the operational amplifier the compensation capacitor play an important role for power consumption. The operational amplifier has been designed and simulated using Tanner in 0.35 µ CMOS process technology. The operational amplifier achieves dc gain 75dB, unity gain bandwidth 5.9 MHz, phase margin 65. Using this operational amplifier we have designed the current conveyor. The designed current conveyor uses four operational amplifier. Current Conveyor gives improved Bandwidth & Slew Rate than that of Op-Amp. REFERENCES [1] Philips E. Allen, Douglas R. Holberg, CMOS Analog Circuit Design 2nd Edition, Oxford University press, 2002. ISSN 2278-5787 Page 36