Course Overview Where does this course fit into the Electrical Engineering curriculum? Page 5 Course Overview Where does this course fit into the Computer Engineering curriculum? Page 6 3
Course Content What is this course? - In EE261 you learned: - basic combinational logic design - basic sequential logic design - In EE262 you learned: - how to implement logic circuits using off-the-shelf parts - EE367 is a follow-on course that looks at: - Large scale digital designs - Performance of digital circuitry - Programmable Logic Page 7 Course Content What does "Large" mean? - Large means that you can't do it by hand. We need a way to design and simulate Millions of gates - K-maps for a Pentium would take too much paper Page 8 4
Course Content We will learn VHDL in order to describe large digital designs - VHDL is a text based Hardware Description Language - We can simulate our digital designs created in VHDL Page 9 Course Content We can also prototype our designs using an FPGA - FPGA = Field Programmable Gate Array - An FPGA is a programmable logic device - In Lab, we will implement our designs and test them in FPGA hardware Page 10 5
Course Content What topics will be covered? 1) VHDL (Exam #1 Topics) 2) Medium Scale Combinational Logic Devices 3) More Complex Finite State Machines (Exam #2 Topics) 4) Computer Systems 5) FPGA Timing and Implementation Instead of a final, we will have a final project ex) - 4-bit microprocessor - peripheral controller (USB, Ethernet, RS232) - memory controller (EEprom, DDR, SRAM) Page 11 Combinational Logic Combinational Logic Gates : - Output depends on the logic value of the inputs - no storage Page 12 6
NOT out = in = in f(in) = in = in OR out = a+b f(a,b) = a+b AND out = a b f(a,b) = a b Page 13 XOR out = a b f(a,b) = a b NOR out = a+b f(a,b) = a+b NAND out = a b f(a,b) = a b Page 14 7
XNOR out = a b f(a,b) = a b Also remember about XOR Gates: f(a,b) = a b = (a b + b a) Also remember the priority of logic operations (without parenthesis) is: NOT, AND, OR Page 15 DeMorgan s Theorems - Inverting the output of any gate results in the same function as the opposite gate (AND/OR) with inverted inputs Page 16 8
DeMorgan s Theorems - Graphically : breaking the bar changes the logic function (AND-OR) under the break out = a+b out = a+b out = a b 1) Break bar 2) Change + to under break Page 17 Boolean Expressions Using SOP - Logic functions can be described using a Sum of Products techniques - Sum of Products (SOP) is the summation of all minterms resulting in the truth table - A minterm is the expression for an input configuration which yields a TRUE output - A minterm expression is the AND ing of the input "1" signal configuration Truth Table a b out 0 0 0 1 minterm m1 = a b 1 minterm m2 = a b 1 1 0 SOP Expression : f(a,b) = a b + a b Note : un-minimized Boolean expression Page 18 9
Boolean Expressions Using POS - Logic functions can be described using a Product of Sums techniques - Product of Sums (POS) is the multiplication of all maxterms resulting in the truth table - A maxterm is the expression for an input configuration which yields a FALSE output - A maxterm expression is the OR ing of the input "0" signal configuration Truth Table a b out 0 0 0 maxterm m0 = a+b (input configuration of 0's) 1 1 1 1 0 maxterm m3 = a'+b' (input configuration of 0's) POS Expression : f(a,b) = (a+b) (a'+b') Page 19 Boolean Expressions Using SOP & POS - SOP and POS functions are equivalent SOP Expression : f(a,b) = a b + a b is equal to POS Expression : f(a,b) = (a+b) (a'+b') Page 20 10
Karnaugh Maps - K-maps provide a graphical method to find SOP/POS expressions - K-maps also provide a graphical method to perform logic minimization K-map SOP Process 1) Circle minterms to create SOP 2) Circle in Horizontal & Vertical manner 3) Circle in groups with powers of 2 (1,2,4,8, ) Truth Table a b out 0 0 0 1 1 1 1 1 b 0 1 a 1 1 No dependency on b, No dependency on a, SOP expression : minterm = a minterm = b f(a,b) = a + b Page 21 Karnaugh Maps - K-maps provide a graphical method to find SOP/POS expressions - K-maps also provide a graphical method to perform logic minimization K-map POS Process 1) Circle maxterms to create SOP 2) Circle in Horizontal & Vertical manner 3) Circle in groups with powers of 2 (1,2,4,8, ) Truth Table a b out 0 0 0 1 1 1 1 1 b 0 1 a 1 1 Dependency on a' and b', maxterm = a+b POS expression : f(a,b) = a + b Page 22 11
Sequential Logic - Concept of Storage Element - With Storage, logic functions can depend on current & past values of inputs - Sequential State Machines can be created D-Flip-Flop - on timing event (i.e., edge of clock input), D input goes to output CLK D D tc2q Page 23 State Machines - Moore : Outputs depend on present state - Mealy : Outputs depend on present state and current inputs Page 24 12
State Machine Example : Design a 2-bit Gray Code Counter 00 01 1) Number of States? : 4 2) Number of bits to encode states? : 2 n =4, n=2 3) Moore or Mealy? : Moore For this counter, we can make the outputs be the state codes 11 10 Page 25 State Machine Example : Design a 2-bit Gray Code Counter 00 01 11 10 STATE Current Next Acur Bcur Anxt Bnxt 0 0 1 1 1 1 1 0 1 0 0 0 Acur 0 1 Anxt Logic Bcur Anxt = Bcur Acur 0 1 A B Bnxt Logic Bcur 1 1 0 0 Bnxt = Acur counter output CLK D A D B Page 26 13