FAST PROUCTS 74F373 Octal traparent latch (3-State) 74F374 Octal flip-flop (3-State) 1994 ec 05 IC15 ata Handbook Philips Semiconductors
74F373 Octal traparent latch (3-State) 74F374 Octal -type flip-flop (3-State) FATURS 8-bit traparent latch 74F373 8-bit positive edge triggered register 74F374 3-State outputs glitch free during power-up and power-down Common 3-State output register Independent register and 3-State buffer operation SSOP Type II Package SCRIPTION The 74F373 is an octal traparent latch coupled to eight 3-State output devices. The two sectio of the device are controlled independently by enable () and output enable (O) control gates. The data on the inputs is traferred to the latch outputs when the enable () input is high. The latch remai traparent to the data input while is high, and stores the data that is present one setup time before the high-to-low enable traition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active low output enable (O) controls all eight 3-State buffers independent of the latch operation. When O is low, latched or traparent data appears at the output. The 74F374 is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sectio of the device are controlled independently by clock (CP) and output enable (O) control gates. The register is fully edge triggered. The state of the input, one setup time before the low-to-high clock traition is traferred to the corresponding flip-flop s output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active low output enable (O) controls all eight 3-State buffers independent of the register operation. When O is low, the data in the register appears at the outputs. When O is high, the outputs are in high impedance off state, which mea they will neither drive nor load the bus. TYP TYPICAL PROPAGATION LAY TYPICAL SUPPLY CURRNT (TOTAL) 74F373 4.5 35mA TYP TYPICAL f max CURRNT TYPICAL SUPPLY (TOTAL) 74F374 165MHz 55mA When O is high, the outputs are in high impedance off state, which mea they will neither drive nor load the bus. ORRING INFORMATION ORR CO SCRIPTION COMMRCIAL RANG PKG WG # V CC = 5V ±10%, T amb = 0 C to +70 C 20-pin plastic IP N74F373N, N74F374N SOT146-1 20-pin plastic SOL N74F373, N74F374 SOT163-1 20-pin plastic SSOP type II N74F373B, N74374B SOT399-1 INPUT AN OUTPUT LOAING AN FAN OUT TABL PINS SCRIPTION 74F (U.L.) HIGH/LOW LOA VALU HIGH/LOW 0-7 ata inputs 1.0/1.0 20µA/0.6mA (74F373) nable input (active high) 1.0/1.0 20µA/0.6mA O Output enable inputs (active low) 1.0/1.0 20µA/0.6mA CP (74F374) Clock pulse input (active rising edge) 1.0/1.0 20µA/0.6mA 0-7 3-State outputs 150/40 ma/24ma NOT: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. ecember 5, 1994 2 853-0369 14383
PIN CONFIGURATION 74F373 PIN CONFIGURATION 74F374 O 1 20 0 0 1 1 2 2 3 3 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 GN 10 11 V CC 7 7 6 6 5 5 4 4 O 0 0 1 1 2 2 3 3 GN 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 V CC 7 7 6 6 5 5 4 4 CP SF00250 SF00253 LOGIC SYMBOL 74F373 IC/I SYMBOL 74F374 3 4 7 8 13 14 17 18 3 4 7 8 13 14 17 18 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 11 1 O 0 1 2 3 4 5 6 7 11 1 CP O 0 1 2 3 4 5 6 7 2 5 6 9 12 15 16 19 2 5 6 9 12 15 16 19 V CC = Pin 20 GN = Pin 10 SF00251 V CC = Pin 20 GN = Pin 10 SF00254 IC/I SYMBOL 74F373 1 N1 11 3 4 7 8 13 14 17 N2 2 1 2 5 6 9 12 15 16 IC/I SYMBOL 74F374 1 N1 11 3 4 7 8 13 14 17 18 C2 2 1 2 5 6 9 12 15 16 19 18 19 SF00255 SF00252 ecember 5, 1994 3
LOGIC IAGRAM FOR 74F373 0 3 1 4 2 7 3 8 4 13 5 14 6 17 7 18 11 1 O 2 5 6 9 12 15 16 19 V CC = Pin 20 GN = Pin 10 0 1 2 3 4 5 6 7 SF00256 LOGIC IAGRAM FOR 74F374 0 3 1 4 2 7 3 8 4 13 5 14 6 17 7 18 CP CP CP CP CP CP CP CP CP 11 V CC = Pin 20 GN = Pin 10 O 1 2 0 5 1 6 2 9 3 4 12 5 15 6 16 7 19 SF00257 FUNCTION TABL FOR 74F373 INPUTS INTRNAL OUTPUTS O n RGISTR 0-7 L H L L L L H H H H L l L L L h H H L L X NC NC Hold H L X NC Z H H n n Z NOTS: H = High-voltage level h = High state must be present one setup time before the high-to-low enable traition L = Low-voltage level l = Low state must be present one setup time before the high-to-low enable traition NC= No change X = on t care Z = High impedance off state = High-to-low enable traition OPRATING MO nable and read register Latch and read register isable outputs ecember 5, 1994 4
FUNCTION TABL FOR 74F374 INPUTS INTRNAL OUTPUTS O CP n RGISTR 0-7 L l L L L h H H L X NC NC Hold H X NC Z H n n Z NOTS: H = High-voltage level h = High state must be present one setup time before the low-to-high clock traition L = Low-voltage level l = Low state must be present one setup time before the low-to-high clock traition NC= No change X = on t care Z = High impedance off state = Low-to-high clock traition = Not low-to-high clock traition OPRATING MO Load and read register isable outputs ABSOLUT MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMTR RATING UNIT V CC Supply voltage -0.5 to +7.0 V V IN Input voltage -0.5 to +7.0 V I IN Input current -30 to +5 ma V OUT Voltage applied to output in high output state -0.5 to VCC V I OUT Current applied to output in low output state 48 ma T amb Operating free air temperature range 0 to +70 C T stg Storage temperature range -65 to +150 C RCOMMN OPRATING CONITIONS LIMITS SYMBOL PARAMTR MIN NOM MAX UNIT V CC Supply voltage 4.5 5.5 V V IH High-level input voltage V V IL Low-level input voltage 0.8 V I Ik Input clamp current -18 ma I OH High-level output current -3 ma I OL Low-level output current 24 ma T amb Operating free air temperature range 0 +70 C ecember 5, 1994 5
C LCTRICAL CHARACTRISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL V OH V OL High-level output voltage Low-level output voltage PARAMTR TST LIMITS CONITIONS 1 MIN TYP 2 MAX UNIT V CC = MIN, V IL = MAX, ±10%V CC 2.4 V V IH = MIN, I OH = MAX ±5%V CC 2.7 3.4 V V CC = MIN, V IL = MAX, ±10%V CC 0.35 0.50 V V IH = MIN, I OL = MAX ±5%V CC 0.35 0.50 V V IK Input clamp voltage V CC = MIN, I I = I IK -0.73-1.2 V I I Input current at maximum input voltage V CC = MAX, V I = 7.0V 100 µa I IH High-level input current V CC = MAX, V I = 2.7V 20 µa I IL Low-level input current V CC = MAX, V I = 0.5V -0.6 ma I OZH Off-state output current, high-level voltage applied V CC = MAX, V O = 2.7V 50 µa I OZL Off-state output current, low-level voltage applied V CC = MAX, V O = 0.5V -50 µa I OS Short-circuit output current 3 V CC = MAX -60-150 ma 74F373 35 60 ma I CC Supply current (total) 74F374 V CC = MAX 57 86 ma NOTS: 1. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type. 2. All typical values are at V CC = 5V, T amb = 25 C. 3. Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I OS tests should be performed last. AC LCTRICAL CHARACTRISTICS LIMITS T amb = +25 C T amb = 0 C to +70 C SYMBOL PARAMTR TST V CC = +V V CC = +V ± 10% UNIT CONITION C L = 50pF, R L = 500Ω C L = 50pF, R L = 500Ω t PLH t PHL t PLH t PHL t PZH t PZL t PHZ t PLZ Propagation delay n to n Propagation delay to n Output enable time to high or low level Output disable time from high or low level 74F373 Waveform 3 Waveform 2 Waveform 6 Waveform 7 Waveform 6 Waveform 7 MIN TYP MAX MIN MAX f max Maximum clock frequency Waveform 1 150 165 140 t PLH t PHL t PZH t PZL t PHZ t PLZ Propagation delay CP to n Output enable time to high or low level Output disable time from high or low level 74F374 Waveform 1 Waveform 6 Waveform 7 Waveform 6 Waveform 7 3.5 3.5 5.3 3.7 9.0 4.0 5.6 4.5 3.8 9.0 5.3 5.3 4.3 7.0 11.5 7.0 11.0 7.5 6.5 7.5 7.5 11.0 7.5 6.0 5.5 8.0 6.0 1 8.0 11.5 8.5 7.0 6.0 8.5 8.5 1 8.5 7.0 6.5 ecember 5, 1994 6
AC STUP RUIRMNTS T amb = +25 C LIMITS T amb = 0 C to +70 C SYMBOL PARAMTR TST V CC = +V V CC = +V ± 10% UNIT CONITION C L = 50pF, R L = 500Ω C L = 50pF, R L = 500Ω t su (H) t su (L) t h (H) t h (L) Setup time, high or low level n to Hold time, high or low level n to 74F373 Waveform 4 Waveform 4 MIN TYP MAX MIN MAX t w (H) Pulse width, high Waveform 1 3.5 4.0 t su (H) t su (L) Setup time, high or low level n to CP Waveform 5 0 1.0 0 1.0 t h (H) t h (L) Hold time, high or low level n to CP 74F374 Waveform 5 0 0 0 0 t w (H) t w (L) CP Pulse width, high or low Waveform 5 3.5 4.0 3.5 4.0 AC WAVFORMS For all waveforms, = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/f max n CP t w (H) t PLH t PHL t PLH t w (L) t PHL n n SF00260 SF00258 Waveform 1. Propagation delay for clock input to output, clock pulse widths, and maximum clock frequency Waveform 3. Propagation delay for data to output n t w (H) t su (H) t h (H) t su (L) t h (L) t PHL t PLH SF00261 n Waveform 4. ata setup time and hold times Waveform 2. Propagation delay for enable to output and enable pulse width SF00259 ecember 5, 1994 7
AC WAVFORMS (Continued) For all waveforms, = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. n On CP t su (H) t h (H) t su (L) t h (L) n, n t PZL t PLZ V OL +0.3V SF00262 Waveform 5. ata setup time and hold times SF00264 Waveform 7. 3-State output enable time to low level and output disable time from low level On t PZH t PHZ V OH -0.3V n, n 0V SF00263 Waveform 6. 3-State output enable time to high level and output disable time from high level TST CIRCUIT AN WAVFORMS SWITCH POSITION TST SWITCH t PLZ, t PZL closed All other open V IN PULS GNRATOR R T V CC.U.T. V OUT Test circuit for 3-state outputs C L R L R L 7.0V FINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to Z OUT of pulse generators. 90% t w 90% AMP (V) NGATIV PULS 10% 10% 0V t THL ( t f ) t TLH ( t r ) t TLH ( t r ) t THL ( t f ) AMP (V) 90% 90% POSITIV PULS 10% 10% w 0V Input pulse definition INPUT PULS RUIRMNTS family amplitude rep. rate t w t TLH t THL 74F V 1.5V 1MHz 500 2.5 2.5 SF00265 ecember 5, 1994 8
74F373, 74F374 IP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 1994 ec 05 9
74F373, 74F374 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 1994 ec 05 10
74F373, 74F374 NOTS 1994 ec 05 11
FAST Products 74F373, 74F374 FINITIONS ata Sheet Identification Product Status efinition Objective Specification Preliminary Specification Product Specification Formative or in esign Preproduction Product Full Production This data sheet contai the design target or goal specificatio for product development. Specificatio may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contai Final Specificatio. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips lectronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. LIF SUPPORT APPLICATIONS Philips Semiconductors and Philips lectronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips lectronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips lectronics North America Corporation customers using or selling Philips Semiconductors and Philips lectronics North America Corporation Products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips lectronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 ast Arques Avenue P.O. Box 3409 Sunnyvale, California 94088 3409 Telephone 800-234-7381 Philips Semiconductors and Philips lectronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips lectronics North America Corporation 1994 All rights reserved. Printed in U.S.A. (print code) ate of release: July 1994 ocument order number: 9397-750-05119