Vol:9, No:3, 015 Relacig MOSFETs with Sigle Electro Trasistors (SET) to Reduce Power Cosumtio of a Iverter Circuit Ahmed Shariful Alam, Abu Hea M. Mustafa Kamal, M. Abdul Rahma, M. Nasmus Sakib Kha Shabbir, Atiqul Islam Iteratioal Sciece Idex, Nuclear ad Quatum Egieerig Vol:9, No:3, 015 waset.org/publicatio/100056 Abstract Accordig to the rules of quatum mechaics there is a o-vaishig robability of for a electro to tuel through a thi isulatig barrier or a thi caacitor which is ot ossible accordig to the laws of classical hysics. Tuelig of electro through a thi isulatig barrier or tuel juctio is a radom evet ad the magitude of curret flowig due to the tuelig of electro is very low. As the curret flowig through a Sigle Electro Trasistor (SET) is the result of electro tuelig through tuel juctios of its source ad drai the suly voltage requiremet is also very low. As a result, the ower cosumtio across a Sigle Electro Trasistor is ultra-low i comariso to that of a MOSFET. I this aer simulatios have bee doe with PSPICE for a iverter built with both SETs ad MOSFETs. 35mV suly voltage was used for a SET built iverter circuit ad the suly voltage used for a CMOS iverter was 3.5V. Keywords ITRS, ehacemet tye MOSFET, islad, C aalysis, trasiet aalysis, ower cosumtio, backgroud charge co-tuelig. I. INTROUCTION HE advacemet CMOS Techology has bee doe by Tthe egieers for almost 30 years uder Moore s law. Some researchers showed that ossibly CMOS caot be scaled dow further after a few ext years. Iteratioal Techology Road ma for Semicoductors (ITRS) has determied the size of itegrated circuits for ext several years obeyig the rule of Moore s Law. MOSFET (metal oxide semicoductor field effect trasistor) is take to be the leadig electroic device i the la of ITRS. Accordig to ITRS the reset comutig hardware are based o aometer techology. m techology meas the feature size (geerally the gate legth) of a tyical MOSFET is m. ITRS has a roadma where 14 m techology, 10 m techology ad 7 m techology will be the successor to m techology i 014, 016 ad 018 resectively. The miimum size of the MOSFET does ot suort the 7 m techology ad ot eve 10 m techology (MOSFET ca Ahmed Shariful Alam, Abu Hea Md. Mustafa Kamal, Md. Abdul Rahma was with the Islamic Uiversity of Techology, Boardbazar, Gaziur 1704, Bagladesh. He is ow with the eartmet of Electrical ad Electroic Egieerig, Bagladesh Uiversity of Busiess ad Techology, Mirur, haka 116, Bagladesh (hoe: +8801675110451; e-mail: estiak16@yahoo.com). Md. Nasmus Sakib Kha Shabbir ad Atiqul Islam are with the eartmet of Electrical ad Electroic Egieerig, Bagladesh Uiversity of Busiess ad Techology, Mirur, haka 116, Bagladesh (e-mail: eg.sakib@gmail.com, atiqulislam.atiq@gmail.com). suort u to 11m techology oly). So it is clearly uderstood that CMOS techology is gradually gettig ivalid uder Moore s Law [1]. To assure further develomet i this field, ew switchig devices must be itroduced. I this coditio Sigle electro trasistor (SET), a ultra-small device ca be a romisig relacemet of MOSFET. Low suly voltage requiremet ad the tuelig curret made SET a romisig ucomig device. II. SUPPORTING THEORIES A. Theory of MOSFET I CMOS techology geerally the egieers use ehacemet tye MOSFETs. I case of ehacemet tye NMOS the threshold voltage V t (at zero body bias) is take to be ositive ad i case of ehacemet tye PMOS the threshold voltage V t (at zero body bias) is take to be egative []. Figs. 1 ad show a ehacemet tye NMOS ad ehacemet tye PMOS resectively. For a NMOS the curret I flows through it from drai to source ad (1)-(3). Whe NMOS is i cut off regio V V ), ( GS t I 0 (1) Whe NMOS is i resistive regio ( V GS V t ad VS VGS Vt), W V S I VGS VtVS L Whe NMOS is i saturatio regio ( V GS V t ad VS VGS Vt), () 1 W I VGS Vt (3) L where, = mobility of a electro. For a PMOS the curret I flows through it from source to drai ad follows (4), (5) ad (6). Whe PMOS is i cut off regio ( VSG Vt ), I 0 (4) Iteratioal Scholarly ad Scietific Research & Iovatio 9(3) 015 405 scholar.waset.org/1307-689/100056
Vol:9, No:3, 015 Whe PMOS is i resistive regio ( VSG Vt ad VS VSG V ), t W V S I VSG Vt VS L Whe PMOS is i saturatio regio ( VSG Vt ad (5) VS VSG Vt ), 1 W I VSG Vt (6) L where, = mobility of a hole. These equatios [3] were used to simulate a MOSFET based iverter circuit. Iteratioal Sciece Idex, Nuclear ad Quatum Egieerig Vol:9, No:3, 015 waset.org/publicatio/100056 B. Theory of Sigle Electro Trasistor (SET) Fig. 3 shows a tyical sigle trasistor which has 3 electrodes-gate, source ad drai ad a islad. For the urose of roer switchig aother gate (gate ) has bee itroduced. The gates are couled with the islad (sometimes which is termed as quatum dot) with two caacitors C G1 ad C G resectively. Source ad drai are coected with the islad by two tuel juctios. These two tuel juctios have ultra-low caacitive imedace C 1 ad C resectively. By the two gates the coditio of flowig tuelig curret from source to drai ca be cotrolled. Here oe thig should Fig. 1 Structure ad actio of a ehacemet tye NMOS Fig. Structure ad actio of a ehacemet tye PMOS be remembered that the curret flow causes due to tuelig of electros through the two tuel juctios. Fig. 4 shows the equivalet circuit for a SET. A outut stray caacitor C 0 ad a backgroud charge Q 0 is itroduced to this circuit model. SET is extremely charge sesitive which causes the backgroud charge. Whe e (where = a iteger which idicates the umber of elemetary charges i.e., a electro that was added to the islad ad e = ositive elemetary charge) charge is reset o the islad the simle electrostatics show that voltage of the islad V (which is a fuctio of ): Iteratioal Scholarly ad Scietific Research & Iovatio 9(3) 015 406 scholar.waset.org/1307-689/100056
Vol:9, No:3, 015 e V1C 1VC VG 1CG1VGC G Q0 (7) V here, C C1 C CG 1 CG C0. C has bee igored here. Therefore, there are four ossible ways of tuelig of charge e. They are, Γ L1 = tuelig through tuel juctio 1 towards left, Γ L = tuelig through tuel juctio towards left, Γ R1 = tuelig through tuel juctio 1 towards right, Γ R = tuelig through tuel juctio towards right. After determiig the tuel rates for all the ertiet charge states the robabilities of the charge states gettig occuied ca be calculated from (11): L( 1) R 1( 1) P ( ) P ( 1) R( ) L 1( ) (11) Iteratioal Sciece Idex, Nuclear ad Quatum Egieerig Vol:9, No:3, 015 waset.org/publicatio/100056 Fig. 3 Circuit reresetatio of a sigle electro trasistor (SET) Fig. 4 Sigle electro trasistor schematic diagram The amout of electrostatic eergy eeded to add a charge equivalet to e ca be exressed by (8): e ev ( ) (8) The chage of eergy due to the tuelig of a charge e from a lead to the islad is ΔΕ i. Assume the voltage of the lead is V i. So, C e Ei evi ev( ) (9) Tuel resistace, absolute temerature ad the Boltzma costat are exressed by R i, T ad k resectively. Now the rate of tuelig Γ i ca be calculated usig the chage of eergy due to the tuelig of a charge e. C The average curret from tuel juctio 1 to ca be determied from (1): ( ) R1( ) L1( ) (1) I ep The islad s average voltage ca be determied by (13): V V( ) P( ) (13) The voltage ad curret ca be calculated efficietly the charge state should be calculated which has the highest ossibility to be occuied. This charge state ca be calculated by the (14): ot QVCVC V C V C C RV RV e e RR 0 1 1 G1 G1 G G 1 1 1 (14) The basic oeratio of sigle electro trasistor ca be foud i [4] ad all these equatios which were imlemeted usig the orthodox theory of electro tuelig [5] i SET SPICE model are available i [6]. III. THE SIMPLEST IGITAL CIRCUIT: AN INVERTER i eri Ei Ei kt 1 (10) Higher order tuel evets where two or more charges tuel simultaeously are called co-tuelig. Co-tuelig Fig. 5 CMOS iverter Fig. 6 shows a iverter usig SET. The islad of the uer SET is red colored. This meas the backgroud charge is Iteratioal Scholarly ad Scietific Research & Iovatio 9(3) 015 407 scholar.waset.org/1307-689/100056
Vol:9, No:3, 015 Iteratioal Sciece Idex, Nuclear ad Quatum Egieerig Vol:9, No:3, 015 waset.org/publicatio/100056 egative. For exactly the oosite reaso the islad of the lower SET is blue colored. The sig of the backgroud charge of red ad blue islads are oosite but their absolute values are assumed equal. A short descritio o backgroud charges ad SET iverter characteristics ca be foud i [7]. Fig. 6 SET based iverter IV. COMPARISONS OF CMOS INVERTER AN SET BASE INVERTER A. Comariso of C Aalysis Both circuits were simulated i PSPICE. Figs. 7 ad 8 show the simulatio results of the C aalysis of iverters usig MOSFET ad SET resectively. I case of CMOS iverter, the suly voltage=3.5 V, iversio voltage=1.7514 V. I case of SET built iverter, the suly voltage=3.5 mv, iversio voltage=17.514 mv. B. Comariso of Trasiet Aalysis ad Power Cosumtio The iut voltage & outut voltage curves ad the ower cosumtio curves across PMOS & NMOS for a CMOS iverter circuit are show i Figs. 9 ad 10 resectively. Agai the iut voltage & outut voltage curves ad the ower cosumtio curves across PSET & NSET for a SET based iverter circuit are show i Figs. 11 ad 1 resectively. Takig ower cosumtio values for differet times the average ower cosumtio has bee calculated usig MATLAB for both circuits. Followig observatio were made from the simulated results of MATLAB: For a CMOS iveter: The average ower dissiatio across PMOS = 3.3713 10-5 Watt. The average ower dissiatio across NMOS = 3.1703 10-5 Watt. The total average ower dissiatio across the CMOS iverter = 6.5416 10-5 Watt. For a SET based iveter: The average ower dissiatio across PSET = 6.6063 10-1 Watt. The average ower dissiatio across NSET = 6.78 10-1 Watt. The total average ower dissiatio across the SET based iverter = 13.391 10-1 Watt. V. CONCLUSION The PSPICE C aalysis ad trasiet aalysis show similar results for both CMOS iverter ad SET based iverter. The simulatio results clearly show that total ower cosumtio of a SET based iverter is almost 5 millio times less tha that of CMOS iverter. Still this SPICE model has may limitatios. This model has bee desiged cosiderig the orthodox theory where co-tuelig is eglected. Moreover, these simulatios were doe takig the temerature at 7 k which is a very low temerature comared to the room temerature. If these limitatios of SET ca be miimized the SET ca be a leadig device i future techologies. Fig. 7 C characteristics of a CMOS iverter Iteratioal Scholarly ad Scietific Research & Iovatio 9(3) 015 408 scholar.waset.org/1307-689/100056
Vol:9, No:3, 015 Fig. 8 C characteristics of a SET based iverter Iteratioal Sciece Idex, Nuclear ad Quatum Egieerig Vol:9, No:3, 015 waset.org/publicatio/100056 Fig. 9 Trasiet aalysis of a CMOS iverter Fig. 10 Power cosumtio across the PMOS ad the NMOS of a CMOS iverter Iteratioal Scholarly ad Scietific Research & Iovatio 9(3) 015 409 scholar.waset.org/1307-689/100056
Vol:9, No:3, 015 Iteratioal Sciece Idex, Nuclear ad Quatum Egieerig Vol:9, No:3, 015 waset.org/publicatio/100056 Fig. 11 Trasiet aalysis of a SET based iverter Fig. 1 Power cosumtio across the PSET ad the NSET of a SET based iverter REFERENCES [1] R.R. Schaller, Moore's Law: Past, Preset, ad Future, Sectrum, IEEE, vol. 34,. 5-59, August 00. [] ouglas A. Puckell ad Kamra Eshraghia, Basic VLSI esig, 3rd ed., Pretice-Hall, 1995,.6-10. [3] Lida E. M. Brackebury, esig of VLSI Systems: A Practical Itroductio, Macmilla, 1987,.13-18. [4] K. K. Likharev, Sigle-Electro evices ad Their Alicatios, Proceedigs of the IEEE, vol. 87,. 606-63, August 00. [5] A. Scholze Imulatio of Sigle-Electro evices, Ph.. dissertatio, Swiss Federal Istitute of Techology, Zurich, Switzerlad, 000,.15-17. [6] G. Lietschig Sigle-Electro ad Molecular evices, Ph.. Thesis, elft Uiversity of Techology, elft, Netherlads, November 003,.13-0. [7] J. R. Tucker Comlemetary igital Logic Based o the Coulomb Blockade, Joural of Alied Physics, 7, 4399, 199. Iteratioal Scholarly ad Scietific Research & Iovatio 9(3) 015 410 scholar.waset.org/1307-689/100056