EE 435 Switched Capacitor Amplifiers and Filters Lab 7 Spring 2014 Amplifiers are widely used in many analog and mixed-signal applications. In most discrete applications resistors are used to form the feedback network and the standard inverting and noninverting amplifier configurations of Fig.1 are often the amplifier of choice. In integrated applications, the physical size of the resistor often makes the use of such configurations impractical. As an alternative, the switched capacitor amplifier is often used. Switched-capacitor amplifiers often provide a significant reduction in total area because the physical size of a switched-capacitor feedback network can practically be smaller than the physical size of a resistive feedback network. Switched-capacitor concepts apply well beyond the amplifier. Other applications include filters, ADCs, DACs, and a host of other useful functions. This laboratory experiment focuses on investigating basic properties of switchedcapacitor amplifiers and switched-capacitor filters. Switched-Capacitor Amplifier (a) (b) Fig. 1 Basic Noninverting and Inverting Feedback Amplifiers with Resistive Feedback Page 1 of 6
There are several variants of the switched capacitor amplifier. Tradeoffs in performance between various implementations will be discussed in class. Two simple switched capacitor amplifiers are shown in Fig. 2. The first is an inverting amplifier and the second is an inverting amplifier. Some other structures appear in Chapter 14 of the Johns and Martin text. C 2 (a) C 2 (b) Fig. 2 Basic Switched-Capacitor Amplifiers a) Inverting b) Noninverting The clock signals that control the switches, φ 1 and φ 2, are complimentary nonoverlapping clocks. In Fig. 2, the switches are closed when the control signal is high and open when it is low. In practical implementations, the switches are generally single n-channel transistors although there may be applications where p-channel switches or transmission gate switches are actually used. Complimentary nonoverlapping clock signals are shown in Fig. 3 Page 2 of 6
T NO T Fig. 3 Complimentary Nonoverlapping Clock Signals The period of the clock signals is T and the nonoverlap interval is denoted at T NO in the figure. It is critical that the nonoverlapping property be maintained for proper operation of many switchedcapacitor circuits. There are different ways to generate nonoverlapping clocks on silicon. One is shown in Section 10.1 of your text. Although it is relatively straightforward to generate nonoverlapping clocks on silicon, it is a challenge to generate high frequency nonoverlapping clocks off-chip. Thus, for this experiment, an alternative nonoverlapping clock generation scheme will be used. This is shown in Fig. 4. Although this may be useful for low-frequency nonoverlapping clock generation, it is not practical on-chip. 1V V TRIAG -1V V TRIAG V X -V X Fig. 4 Low Frequency Nonoverlapping Clock Generator In this circuit, the voltage V X is between 0 and 1V and the amount of overlap can be controlled with V X. Page 3 of 6
Part 1 Derive the voltage gain for the two switched-capacitor circuits of Fig. 2. This derivation is straightforward if you use the principle of charge conservation and analyze the circuit for one clock period. Part 2 Simulate the circuits of Fig. 1b and Fig. 2a in SPICE and compare the results. Assume both circuits are designed for a gain of -2. Do this simulation in the time domain with an input sinusoid for both circuits of 1V 0-P at 250Hz and for the switched capacitor circuit, with a clock frequency of 10KHz. Use ideal op amps and n-channel MOS transistors for the switches. Pick a large enough clock voltage and wide enough switches so that there is no problem with charging or discharging the capacitors in a half-period. Be sure to make the clocks nonoverlapping. After you have the switched-capacitor simulation working with a clock frequency of 10KHz a) decrease the clock frequency to 2KHz and then to 1KHz and observe the output. Does it still perform as an amplifier with the lower clock frequencies? b) Vary the nonoverlap interval from 1% of the clock period to 25% of the clock period. What effect does it have on the gain? Comment on how sensitive this circuit is to the nonoverlap time. Part 3 Build the circuit of Fig. 2a designed for a gain of -2 in the laboratory and measure the performance. Use analog switches available in your parts kit for the switches. The nonoverlapping clock generator of Fig. 4 with a second signal generator for the triangle wave generation will be useful. Use a nominal clock frequency of 10KHz and a 250Hz input sinusoid for testing this circuit. To obtain a gain of -2, you may want to use 1nF or 5nF capacitors by placing two in parallel if you need a capacitor that is twice as big. If you make the capacitors too large, the op amp will have a problem driving the feedback network. If you make the capacitors too small, the parasitics on your circuit board will cause problems. Switched-Capacitor Filters A continuous-time low-psss filter is shown below. This circuit works very well for lowerfrequency applications in discrete form but is impractical to build in integrated form because of the large area required to realize the passive components and because of the high tolerances on the integrated components. Both issues are of such major consequences that this continuoustime filter has almost no practical on-chip appications. Page 4 of 6
C R R 1 V V R/ R = - 1+RCs OUT 1 Low-pass Active Filter 1 p = - RC IN A switched-capacitor low-pass active filter is shown below. It has both inverting and noninverting inputs. Either input block can be eliminated if only a single input is required. Though this circuit is affected by parasitic components, it will work quite well in discrete applications and is a bit less complicated to work with in the laboratory than the stray-insensitive structures that have a more complicated switching scheme. φ 2 φ 1 φ 1 φ 2 1 C 3 C φ 1 φ 2 2 Switched-capacitor low-pass active filter Page 5 of 6
Part 4 Design a non-inverting switched-capacitor low-pass filter that has a 3dB band edge of 1KHz. Assume a clocking frequency of 50KHz Part 5 Build and measure the performance in the laboratory of the design of Part 4 and compare with the theoretical results. Page 6 of 6