TVS Diode Transient Voltage Suppressor Diodes ESD3B12LRH Low Clamping & Low Capacitance ESD/Surge Protection Diode ESD3B12LRH Data Sheet Revision 1.2, 2131126 Final Power Management & Multimarket
Revision History: Revision 1.1, 213617 Page or Item Subjects (major changes since previous revision) Revision 1.2, 2131126 4 Update of Figure 21) Trademarks of Infineon Technologies AG AURIX, BlueMoon, C166, CanPAK, CIPOS, CIPURSE, COMNEON, EconoPACK, CoolMOS, CoolSET, CORECONTROL, CROSSAVE, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPIM, EiceDRIVER, eupec, FCOS, HITFET, HybridPACK, I²RF, ISOFACE, IsoPACK, MIPAQ, ModSTACK, myd, NovalithIC, OmniTune, OptiMOS, ORIGA, PRIMARION, PrimePACK, PrimeSTACK, PROSIL, PROFET, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SIPMOS, SMARTi, SmartLEWIS, SOLID FLASH, TEMPFET, thinq!, TRENCHSTOP, TriCore, XGOLD, XPMU, XMM, XPOSYS. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTIICE, KEIL, PRIMECELL, REALVIEW, THUMB, µvision of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CATiq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. murata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Satellite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update 21126 Final Data Sheet 2 Revision 1.2, 2131126
Low Clamping & Low Capacitance ESD/Surge Protection Diode 1 Low Clamping & Low Capacitance ESD/Surge Protection Diode 1.1 Features Extremely high ESD and surge protection IEC6142 (ESD): ±3 kv (air/contact discharge) IEC6145 (surge): ±18 A (8/2 μs) Low clamping voltage V CL < 8 V (8 kv contact) Maximum peak pulse power P PP =26W (8/2μs) Extremely low dynamic resistance: R DYN =.23Ω typ. Supports applications with signal voltage 3.3 V max. Line capacitance: C L = typ. 1.2 pf Package TSLP217 compatible to SOD882D leadless ultra small SurfaceMounted Device (SMD) Size 1 mm x.6 mm x.39 mm (42) 1.2 Application Examples Reliable ESD and surge protection of highly susceptible IC/ASICs in computers and peripherals, audio, headset, human digital interfaces, video equipment, cellular handsets and accessories and portable electronics Dedicated solution to boost ESD and surge protection performance in miniaturized modern electronics 1/1/1 Ethernet 1.3 Product Description Pin 1 Marking Pin 1 Pin 1 Pin 2 TSLP217 Pin 2 a) Pin configuration b) Schematic diagram Configuration_Schematic_Diagram.vst.vsd Figure 11 Pin Configuration and Schematic Diagram Table 11 Ordering Information Type Package Configuration Marking code ESD3B12LRH TSLP217 1 line, bidirectional S3 Final Data Sheet 3 Revision 1.2, 2131126
Characteristics 2 Characteristics 2.1 Maximum Ratings Table 21 Maximum Ratings at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Min. Typ. Max. ESD 1) contact discharge air discharge V ESD 3 3 Peak pulse current (t p = 8/2 μs) 2) I PP 18 18 A Peak pulse power (t p = 8/2 μs) 2) P PP 26 W Operating temperature range T OP 55 125 C Storage temperature T stg 65 15 C 1) V ESD according to IEC6142 (R = 33, C = 15 pf discharge network) 2) I PP according to IEC6145 (t p = 8/2 μs) Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 2.2 Electrical Characteristics at T A = 25 C, unless otherwise specified 3 3 kv Figure 21 Definitions of electrical characteristics Final Data Sheet 4 Revision 1.2, 2131126
Characteristics Table 22 DC Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Reverse working voltage V RWM 3.3 3.3 V Reverse current I R 1 na V R =3.3V Table 23 RF Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Line capacitance C L 1.2 1.8 pf V R =V, f =1MHz Table 24 ESD Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Clamping voltage 1) V CL 8 V V ESD =8kV, t p =3ns contact discharge Clamping voltage 2) V CL V t p =8/2µs 5 I PP =1A 8.5 I PP =12A 1.5 I PP =18A Clamping voltage 3) 9.5 12.5 Dynamic resistance 3) R DYN.23 Ω 1) V ESD according to IEC6142 (R =33Ω, C = 15 pf discharge network) 2) I PP according to IEC6145 (t p =8/2μs) 3)ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitive Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z =5Ω, t p =1ns, t r=.6ns, I TLP and V TLP averaging window: t 1 =3ns to t 2 = 6 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between I TLP1 = 1 A and I TLP2 = 4 A. Please refer to Application Note AN21 [1] t p = 1 ns I PP =16A I PP =3A Final Data Sheet 5 Revision 1.2, 2131126
Typical Characteristics at T A = 25 C, unless otherwise specified 3 Typical Characteristics at T A = 25 C, unless otherwise specified 1 6 1 7 1 8 I R [ma] 1 9 1 1 1 11 1 12 1 13 3.5 3 2.5 2 1.5 1.5.5 1 1.5 2 2.5 3 3.5 V R [V] Figure 31 Reverse current: I R = f(v R ) 4 3.5 3 2.5 C L [pf] 2 1.5 1.5 3.5 3 2.5 2 1.5 1.5.5 1 1.5 2 2.5 3 3.5 V R [V] Figure 32 Line capacitance: C L = f(v R ), f =1MHz Final Data Sheet 6 Revision 1.2, 2131126
Typical Characteristics at T A = 25 C, unless otherwise specified 6 5 ESD3B12LRH R DYN 3 25 4 2 3 2 R DYN =.223 Ω 15 1 I TLP [A] 1 1 5 5 Equivalent V IEC [kv] 2 3 R DYN =.227 Ω 1 15 4 2 5 25 6 3 2 15 1 5 5 1 15 2 V TLP [V] Figure 33 Clamping voltage (TLP): I TLP = f(v TLP ) according ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z =5Ω, t p =1ns, t r =.6ns, I TLP and V TLP averaging window: t 1 =ns to t 2 = 6 ns, extraction of dynamic resistance using squares fit to TLP characteristics between I TLP1 = 1 A and I TLP2 = 4 A. Please refer to Application Note AN21 [1] Final Data Sheet 7 Revision 1.2, 2131126
Typical Characteristics at T A = 25 C, unless otherwise specified 25 ESD3B12LRH R DYN 2 15 R DYN =.3 Ω 1 5 I PP [A] 5 1 15 R DYN =.3 Ω 2 25 15 1 5 5 1 15 V CL [V] Figure 34 Pulse current (IEC6145) versus clamping voltage: I PP = f(v CL ) Final Data Sheet 8 Revision 1.2, 2131126
Typical Characteristics at T A = 25 C, unless otherwise specified 7 6 Scope: 6 GHz, 2 GS/s V CL [V] 5 4 3 2 1 1 V CLmaxpeak = 64 V V CL3nspeak = 8 V 2 5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 35 IEC6142 : V CL = f(t), 8 kv positive pulse from pin 1 to pin 2 2 1 Scope: 6 GHz, 2 GS/s V CL [V] 1 2 3 4 5 6 V CLmaxpeak = 63 V V CL3nspeak = 8 V 7 5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 36 IEC6142 : V CL = f(t), 8 kv negative pulse from pin 1 to pin 2 Final Data Sheet 9 Revision 1.2, 2131126
Typical Characteristics at T A = 25 C, unless otherwise specified 1 Scope: 6 GHz, 2 GS/s 8 V CL [V] 6 4 2 V CLmaxpeak = 92 V V CL3nspeak = 11 V 2 5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 37 IEC6142 : V CL = f(t), 15 kv positive pulse from pin 1 to pin 2 2 Scope: 6 GHz, 2 GS/s 2 V CL [V] 4 6 8 V CLmaxpeak = 91 V V CL3nspeak = 1 V 1 5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 38 IEC6142 : V CL = f(t), 15 kv negative pulse from pin 1 to pin 2 Final Data Sheet 1 Revision 1.2, 2131126
Package Information 4 Package Information 4.1 TSLP217 Top view +.1.39.3 Bottom view.5 MAX..6 ±.5.65 ±.5 2 1 1±.5 Cathode marking 1).5 ±.35 1) Dimension applies to plated terminal 1).25 ±.35 TSLP27PO V2 Figure 41 TSLP217 Package outline (dimension in mm).6.35.45 1.3.925.275.35.275.375 Copper Solder mask Stencil apertures TSLP27FP V1 Figure 42 TSLP217 Footprint (dimension in mm) 4.5 1.16 8 Orientation marking.76 TSLP27TP V3 Figure 43 TSLP217 Packing (dimension in mm) 12 Type code Cathode marking Figure 44 TSLP217 Marking (example) TSLP218MK V1 Final Data Sheet 11 Revision 1.2, 2131126
References References [1] Infineon AG Application Note AN21: Effective ESD Protection design at System Level Using VFTLP Characterization Methodology Final Data Sheet 12 Revision 1.2, 2131126
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