TM ADVANCED LINEAR DEVICES, INC. EPAD ALD1721E E N A B L E D EPAD MICROPOWER CMOS OPERATIONAL AMPLIFIER KEY FEATURES EPAD (Elctrically Programmabl Analog Dvic) Usr programmabl V OS trimmr Computr-assistd trimming Rail-to-rail input/output Compatibl with standard EPAD Programmr High prcision through in-systm circuit prcision trimming Rducs or liminats V OS, PSRR, CMRR and TCV OS rrors Systm lvl calibration capability Application Spcific Programming mod In-Systm Programming mod Elctrically programmabl to compnsat for xtrnal componnt tolrancs Achivs.1pA input bias currnt and 35µV input offst voltag simultanously Compatibl with industry standard pinout BENEFITS Eliminats manual and laborat systm trimming procdurs Rmot controlld automatd trimming In-Systm Programming capability No xtrnal componnts No intrnal choppr clocking nois No choppr dynamic powr dissipation Simpl and cost ffctiv Small packag siz Extrmly small total functional volum siz Low systm implmntation cost Micropowr and Low Voltag GENERAL DESCRIPTION Th ALD1721E is a monolithic rail-to-rail prcision CMOS oprational amplifir with intgratd usr programmabl EPAD (Elctrically Programmabl Analog Dvic) basd offst voltag adjustmnt. Th ALD1721E oprational amplifir is a dirct rplacmnt of th ALD171 oprational amplifir, with th addd fatur of usr-programmabl offst voltag trimming rsulting in significantly nhancd total systm prformanc and usr flxibility. EPAD tchnology is an xclusiv ALD dsign which has bn rfind for analog applications whr prcision voltag trimming is ncssary to achiv a dsird prformanc. It utilizs CMOS FETs as incircuit lmnts for trimming of offst voltag bias charactristics with th aid of a prsonal computr undr softwar control. Onc programmd, th st paramtrs ar stord indfinitly within th dvic vn aftr powrdown. EPAD offrs th circuit dsignr a convnint and cost-ffctiv trimming solution for achiving th vry highst amplifir/systm prformanc. Th ALD1721E oprational amplifir faturs rail-to-rail input and output voltag rangs, tolranc to ovr-voltag input spiks of 3mV byond supply rails, capacitiv loading up to 5pF, xtrmly low input currnts of.1pa typical, high opn loop voltag gain, usful bandwidth of 7KHz, slw rat of.7v/µs, and low typical supply currnt of 12µA. APPLICATIONS Snsor intrfac circuits Transducr biasing circuits Capacitiv and charg intgration circuits Biochmical prob intrfac Signal conditioning Portabl instrumnts High sourc impdanc lctrod amplifirs Prcision Sampl and Hold amplifirs Prcision currnt to voltag convrtr Error corrction circuits Snsor compnsation circuits Prcision gain amplifirs Priodic In-systm calibration Systm output lvl shiftr PIN CONFIGURATION VE1 1 8 VE2 ORDERING INFORMATION ( L suffix dnots lad-fr (RoHS)) Oprating Tmpratur Rang C to +7 C C to +7 C -55 C to +125 C 8-Pin 8-Pin 8-Pin Small Outlin Plastic Dip CERDIP Packag (SOIC) Packag Packag ALD1721ESAL ALD1721EPAL ALD1721EDA -IN +IN V - 2 3 4 2 TOP VIEW SAL, PAL, DA PACKAGES * N/C Pin is intrnally connctd. Do not connct xtrnally. 7 6 5 V+ OUT N/C * Contact factory for ladd (non-rohs) or high tmpratur vrsions. Rv 2.1 211 Advancd Linar Dvics, Inc. 415 Tasman Driv, Sunnyval, CA 9489-176 Tl: (48) 747-1155 Fax: (48) 747-1286 www.aldinc.com
FUNCTIONAL DESCRIPTION Th ALD1721E uss EPADs as in-circuit lmnts for trimming of offst voltag bias charactristics. Each ALD1721E has a pair of EPAD-basd circuits connctd such that on circuit is usd to adjust V OS in on dirction and th othr circuit is usd to adjust V OS in th othr dirction. Whil ach of th EPAD dvics is a monotonically adjustabl programmabl dvic, th V OS of th ALD1721E can b adjustd many tims in both dirctions. Onc programmd, th st V OS lvls ar stord prmanntly, vn whn th dvic powr is rmovd. Th ALD1721E is pr-programmd at th factory undr standard oprating conditions for minimum quivalnt input offst voltag. It also has a guarantd offst voltag program rang, which is idal for applications that rquir lctrical offst voltag programming. Th ALD1721E is an oprational amplifir that can b trimmd with usr application-spcific programming or insystm programming conditions. Usr application-spcific circuit programming rfrs to th situation whr th Total Input Offst Voltag of th ALD1721E can b trimmd with th actual intndd oprating conditions. For xampl, an application circuit may hav +6V and -2.5V powr supplis, and th oprational amplifir input is biasd at +.7V, and an avrag oprating tmpratur at 55 C. Th circuit can b wird up to ths conditions within an nvironmntal chambr with th ALD1721E insrtd into a tst sockt connctd to this circuit whil it is bing lctrically trimmd. Any rror in V OS du to ths bias conditions can b automatically zrod out. Th Total V OS rror is now limitd only by th adjustabl rang and th stability of V OS, and th input nois voltag of th oprational amplifir. Thrfor, this Total V OS rror now includs V OS as V OS is traditionally spcifid; plus th V OS rror contributions from PSRR, CMRR, TCV OS, and nois. Typically this total V OS rror trm (V OST ) is approximatly ±35µV for th ALD1721E. Th V OS contribution du to PSRR, CMRR, TCV OS and xtrnal componnts can b larg for oprational amplifirs without trimming. Thrfor th ALD1721E with EPAD trimming is abl to provid much improvd systm prformanc by rducing ths othr sourcs of rror to provid significantly rducd V OST. USER PROGRAMMABLE V OS FEATURE Each ALD1721E has two pins namd VE1 and VE2 which ar intrnally connctd to an intrnal offst bias circuit. VE1/ VE2 hav initial typical valus of 1.2V/1.7V. Th voltag on ths pins can b programmd using th ALD E1 EPAD Programmr and th appropriat Adaptr Modul. Th usful programming rang of VE1 and VE2 is 1.2V to 3.V. VE1 and VE2 pins ar programming pins, usd during programming mod to injct charg into th intrnal EPADs. Incrasing voltag on VE1 dcrass th offst voltag whras incrasing voltag on VE2 incrass th offst voltag of th oprational amplifir. Th injctd charg is prmanntly stord and dtrmins th offst voltag of th oprational amplifir. Aftr programming, VE1 and VE2 trminals must b lft opn to sttl on a voltag dtrmind by intrnal bias currnts. During programming, th voltags on VE1 or VE2 ar incrasd incrmntally to st th offst voltag of th oprational amplifir to th dsird Vos. Not that dsird Vos can b any valu within th offst voltag programmabl rangs, and can b zro, a positiv valu or a ngativ valu. This V OS valu can also b rprogrammd to a diffrnt valu at a latr tim, providd that th usful VE1 or VE2 programming voltag rang has not bn xcdd. VE1 or VE2 pins can also srv as capacitivly coupld input pins. Intrnally, VE1 and VE2 ar programmd and connctd diffrntially. Tmpratur drift ffcts btwn th two intrnal offst bias circuits cancl ach othr and introduc lss nt tmpratur drift cofficint chang than offst voltag trimming tchniqus such as offst adjustmnt with an xtrnal trimmr potntiomtr. Whil programming, V+, VE1 and VE2 pins may b altrnatly pulsd with 12V (approximatly) pulss gnratd by th EPAD Programmr. In-systm programming rquirs th ALD1721E application circuit to accommodat ths programming pulss. This can b accomplishd by adding rsistors at crtain appropriat circuit nods. For mor information, s Application Not AN17. In-Systm Programming rfrs to th condition whr th EPAD adjustmnt is mad aftr th ALD1721E has bn insrtd into a circuit board. In this cas, th circuit dsign must provid for th ALD1721E to oprat in normal mod and in programming mod. On of th bnfits of in-systm programming is that not only is th ALD1721E offst voltag from oprating bias conditions accountd for, any rsidual rrors introducd by othr circuit componnts, such as rsistor or snsor inducd voltag rrors, can also b corrctd. In this way, th in-systm circuit output can b adjustd to a dsird lvl, liminating th nd for anothr trimming function. ALD1721E Advancd Linar Dvics 2 of 13
ABSOLUTE MAXIMUM RATINGS Supply voltag, V+ 1.6V Diffrntial input voltag rang -.3V to V+ +.3V Powr dissipation 6 mw Oprating tmpratur rang SAL, PAL packags C to +7 C DA packag -55 C to +125 C Storag tmpratur rang -65 C to +15 C Lad tmpratur, 1 sconds +26 C CAUTION: ESD Snsitiv Dvic. Us static control procdurs in ESD controlld nvironmnt. OPERATING ELECTRICAL CHARACTERISTICS T A = 25 o C V S = ±2.5V unlss othrwis spcifid 1721E Paramtr Symbol Min Typ Max Unit Tst Conditions Supply Voltag VS ±1. ±5. V V+ 2. 1. V Singl Supply Initial Input Offst Voltag 1 VOS i 35 9 µv RS 1KΩ Offst Voltag Program Rang 2 VOS ±1 ±15 mv Programmd Input Offst VOS 5 9 µv At usr spcifid Voltag Error 3 targt offst voltag Total Input Offst Voltag 4 VOST 5 9 µv At usr spcifid targt offst voltag Input Offst Currnt 5 IOS.1 1 pa TA = 25 C 24 pa C TA +7 C Input Bias Currnt 5 IB.1 1 pa TA = 25 C 24 pa C TA +7 C Input Voltag Rang 6 VIR -.3 5.3 V V+ = +5V -2.8 +2.8 V VS = ±2.5V Input Rsistanc RIN 1 14 Ω Input Offst Voltag Drift 7 TCVOS 5 µv/ C RS 1KΩ Initial Powr Supply PSRR i 8 db RS 1KΩ Rjction Ratio 8 Initial Common Mod CMRR i 83 db RS 1KΩ Rjction Ratio 8 Larg Signal Voltag Gain AV 32 1 V/mV RL =1KΩ 2 V/mV C TA +7 C VO low.1.1 V RL =1MΩ V+ = 5V Output Voltag Rang VO high 4.99 4.999 V C TA +7 C VO low -2.48-2.4 V RL =1KΩ VO high 2.4 2.48 V C TA +7 C Output Short Circuit Currnt ISC 1 ma * NOTES 1 through 9, s "Dfinitions and Dsign Nots" on pag 6. ALD1721E Advancd Linar Dvics 3 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd) T A = 25 o C V S = ±2.5V unlss othrwis spcifid 1721E Paramtr Symbol Min Typ Max Unit Tst Conditions Supply Currnt IS 12 2 µa VIN = V No Load Powr Dissipation PD.6 1. mw VS = ±2.5V Input Capacitanc CIN 1 pf Maximum Load Capacitanc CL 5 pf Equivalnt Input Nois Voltag n 55 nv/ Hz f = 1KHz Equivalnt Input Currnt Nois in.6 fa/ Hz f =1Hz Bandwidth BW 4 7 KHz Slw Rat SR.3.7 V/µs AV = +1 RL = 1KΩ Ris tim tr.2 µs RL = 1KΩ Ovrshoot Factor 2 % RL = 1KΩ, CL = 5pF Sttling Tim ts 1 µs.1% AV = 1,RL=1KΩ CL = 5pF T A = 25 o C V S = ±2.5V unlss othrwis spcifid 1721E Paramtr Symbol Min Typ Max Unit Tst Conditions Avrag Long Trm Input Offst VOS.2 µv/ Voltag Stability 9 tim 1 hrs Initial VE Voltag VE1 i, VE2 i 1.2 V Programmabl VE Rang VE1, VE2 1.5 2.5 V Programmd VE Voltag Error (VE1-VE2).1 % VE Pin Lakag Currnt ib -5 µa ALD1721E Advancd Linar Dvics 4 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd) V S = ±2.5V -55 C T A +125 C unlss othrwis spcifid 1721E Paramtr Symbol Min Typ Max Unit Tst Conditions Initial Input offst Voltag VOS i.5 mv RS 1KΩ Input Offst Currnt IOS 2. na Input Bias Currnt IB 2. na Initial Powr Supply PSRR i 75 db RS 1KΩ Rjction Ratio 8 Initial Common Mod CMRR i 83 db RS 1KΩ Rjction Ratio 8 Larg Signal Voltag Gain AV 15 5 V/mV RL = 1KΩ Output Voltag Rang VO low -2.47-2.4 V VO high 2.35 2.45 V RL = 1KΩ T A = 25 o C V S = ±5.V unlss othrwis spcifid 1721E Paramtr Symbol Min Typ Max Unit Tst Conditions Initial Powr Supply PSRR i 83 db RS 1KΩ Rjction Ratio 8 Initial Common Mod CMRRi 83 db RS 1KΩ Rjction Ratio 8 Larg Signal Voltag Gain AV 25 V/mV RL = 1KΩ Output Voltag Rang VO low -4.98-4.9 V RL = 1KΩ VO high 4.9 4.98 Bandwidth BW 1. MHz Slw Rat SR 1. V/µs AV = +1, CL = 5pF ALD1721E Advancd Linar Dvics 5 of 13
DEFINITIONS AND DESIGN NOTES: 1. Initial Input Offst Voltag is th initial offst voltag of th ALD1721E oprational amplifir whn shippd from th factory. Th dvic has bn pr-programmd and tstd for programmability. 2. Offst Voltag Program Rang is th rang of adjustmnt of usr spcifid targt offst voltag. This is typically an adjustmnt in ithr th positiv or th ngativ dirction of th input offst voltag from an initial input offst voltag. Th input offst programming pins, VE1 or VE2, chang th input offst voltag in th ngativ or positiv dirction, rspctivly. Usr spcifid targt offst voltag can b any offst voltag within this programming rang. 3. Programmd Input Offst Voltag Error is th final offst voltag rror aftr programming whn th Input Offst Voltag is at targt Offst Voltag. This paramtr is sampl tstd. 4. Total Input Offst Voltag is th sam as Programmd Input Offst Voltag, corrctd for systm offst voltag rror. Usually this is an all inclusiv systm offst voltag, which also includs offst voltag contributions from input offst voltag, PSRR, CMRR, TCVOS and nois. It can also includ rrors introducd by xtrnal componnts, at a systm lvl. Programmd Input Offst Voltag and Total Input Offst Voltag is not ncssarily zro offst voltag, but an offst voltag st to compnsat for othr systm rrors as wll. This paramtr is sampl tstd. 5. Th Input Offst and Bias Currnts ar ssntially input protction diod rvrs bias lakag currnts. This low input bias currnt assurs that th analog signal from th sourc will not b distortd by it. For applications whr sourc impdanc is vry high, it may b ncssary to limit nois and hum pickup through propr shilding. 6. Input Voltag Rang is dtrmind by two paralll complmntary input stags that ar summd intrnally, ach stag having a sparat input offst voltag. Whil Total Input Offst Voltag can b trimmd to a dsird targt valu, it is ssntial to not that this trimming occurs at only on usr slctd input bias voltag. Dpnding on th slctd input bias voltag rlativ to th powr supply voltags, offst voltag trimming may affct on or both input stags. For th ALD1721E, th switching point btwn th two stags occurs at approximatly 1.5V blow positiv supply voltag. 7. Input Offst Voltag Drift is th avrag chang in Total Input Offst Voltag as a function of ambint tmpratur. This paramtr is sampl tstd. 8. Initial PSRR and initial CMRR spcifications ar providd as rfrnc information. Aftr programming, rror contribution to th offst voltag from PSRR and CMRR is st to zro undr th spcific powr supply and common mod conditions, and bcoms part of th Programmd Input Offst Voltag Error. 9. Avrag Long Trm Input Offst Voltag Stability is basd on input offst voltag shift through oprating lif tst at 125 C xtrapolatd to TA = 25 C, assuming activation nrgy of 1.V. This paramtr is sampl tstd. ADDITIONAL DESIGN NOTES: A. Th ALD1721E is intrnally compnsatd for unity gain stability using a novl schm which producs a singl pol rol off in th gain charactristics whil providing mor than 7 dgrs of phas margin at unity gain frquncy. A unity gain buffr using th ALD1721E will typically driv 5pF of xtrnal load capacitanc. B. Th ALD1721E has complmntary p-channl and n-channl input diffrntial stags connctd in paralll to accomplish railto-rail input common mod voltag rang. Th switching point btwn th two diffrntial stags is 1.5V blow positiv supply voltag. For applications such as invrting amplifirs or noninvrting amplifirs with a gain largr than 2.5 (5V opration), th common mod voltag dos not mak xcursions blow this switching point. Howvr, this switching dos tak plac if th oprational amplifir is connctd as a rail-to-rail unity gain buffr and th dsign must allow for input offst voltag variations. C. Th output stag consists of class AB complmntary output drivrs. Th oscillation rsistant fatur, combind with th railto-rail input and output fatur, maks th ALD1721E an ffctiv analog signal buffr for high sourc impdanc snsors, transducrs, and othr circuit ntworks. D. Th ALD1721E has static discharg protction. Howvr, car must b xrcisd whn handling th dvic to avoid strong static filds that may dgrad a diod junction, causing incrasd input lakag currnts. Th usr is advisd to powr up th circuit bfor, or simultanously with, any input voltags applid and to limit input voltags not to xcd.3v of th powr supply voltag lvls. E. VE1 and VE2 ar high impdanc trminals, as th intrnal bias currnts ar st vry low to a fw microamprs to consrv powr. For som applications, ths trminals may nd to b shildd from xtrnal coupling sourcs. For xampl, digital signals running narby may caus unwantd offst voltag fluctuations. Car during th printd circuit board layout, to plac ground tracs around ths pins and to isolat thm from digital lins, will gnrally liminat such coupling ffcts. In addition, optional dcoupling capacitors of 1pF or gratr valu can b addd to VE1 and VE2 trminals. F. Th ALD1721E is dsignd for us in low voltag, micropowr circuits. Th maximum oprating voltag during normal opration should rmain blow 1V at all tims. Car should b takn to insur that th application in which th dvic is usd dos not xprinc any positiv or ngativ transint voltags that will caus any of th trminal voltags to xcd this limit. G. All inputs or unusd pins xcpt VE1 and VE2 pins should b connctd to a supply voltag such as Ground so that thy do not bcom floating pins, sinc input impdanc at ths pins is vry high. If any of ths pins ar lft undfind, thy may caus unwantd oscillation or intrmittnt xcssiv currnt drain. As ths dvics ar built with CMOS tchnology, normal oprating and storag tmpratur limits, ESD and latchup handling prcautions prtaining to CMOS dvic handling should b obsrvd. ALD1721E Advancd Linar Dvics 6 of 13
TYPICAL PERFORMANCE CHARACTERISTICS OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF SUPPLY VOLTAGE AND TEMPERATURE OUTPUT VOLTAGE SWING AS A FUNCTION OF SUPPLY VOLTAGE OPEN LOOP VOLTAGE GAIN (V/mV) 1 1 1-55 C T A +125 C R L = 1KΩ 1 ±2 ±4 ±6 ±8 SUPPLY VOLTAGE (V) OUTPUT VOLTAGE SWING (V) ±6 ±5 ±4 ±3 ±2-55 C T A +125 C R L = 1KΩ ±1 ±1 ±2 ±3 ±4 ±5 ±6 ±7 SUPPLY VOLTAGE (V) INPUT BIAS CURRENT AS A FUNCTION OF AMBIENT TEMPERATURE SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE INPUT BIAS CURRENT (pa) 1 1 1 1..1 V S = ±2.5V SUPPLY CURRENT (µa) 5 4 3 2 1 INPUTS GROUNDED OUTPUT UNLOADED T A = -55 C -25 C +25 C +7 C +125 C.1-5 -25 25 5 75 1 125 AMBIENT TEMPERATURE ( C) ±1 ±2 ±3 ±4 ±5 ±6 SUPPLY VOLTAGE (V) ADJUSTMENT IN INPUT OFFSET VOLTAGE AS A FUNCTION OF CHANGE IN VE1 AND VE2 OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF FREQUENCY CHANGE IN INPUT OFFSET VOLTAGE VOS (mv) 1 8 6 4 2-2 -4-6 -8-1 VE2 VE1..25.5.75 1. 1.25 1.5 CHANGE IN VE1 AND VE2 (V) OPEN LOOP VOLTAGE GAIN (db) 12 1 8 6 4 2-2 V S = ±2.5V T A = 25 C 18 1 1 1 1K 1K 1K 1M 1M FREQUENCY (Hz) 45 9 135 PHASE SHIFT IN DEGREES ALD1721E Advancd Linar Dvics 7 of 13
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd) ±7 COMMON MODE INPUT VOLTAGE RANGE AS A FUNCTION OF SUPPLY VOLTAGE 1 OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF LOAD RESISTANCE ±6 COMMON MODE INPUT VOLTAGE RANGE (V) ±5 ±4 ±3 ±2 ±1 T A = 25 C ±1 ±2 ±3 ±4 ±5 ±6 ±7 SUPPLY VOLTAGE (V) OPEN LOOP VOLTAGE GAIN (V/mV) 1 1 V S = ±2.5V T A = 25 C 1 1K 1K 1M 1M LOAD RESISTANCE (Ω) LARGE - SIGNAL TRANSIENT RESPONSE LARGE - SIGNAL TRANSIENT RESPONSE 5V/div V S = ±2.5V T A = 25 C R L = 1KΩ C L = 5pF 2V/div V S = ±1.V T A = 25 C R L = 1KΩ C L = 5pF 2V/div 5µs/div 5mV/div 5µs/div SMALL - SIGNAL TRANSIENT RESPONSE 1 DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE BEFORE AND AFTER 1mV/div V S = ±2.5V T A = 25 C R L = 1KΩ C L = 5pF PERCENTAGE OF UNITS (%) 8 6 4 2 EXAMPLE B: V OST AFTER EPAD PROGRAMMING V OST TARGET = -75µV EXAMPLE A: V OST AFTER EPAD PROGRAMMING V OST TARGET =.µv V OST BEFORE EPAD PROGRAMMING 2mV/div 2µs/div -25-2 -15-1 -5 5 1 15 2 25 TOTAL INPUT OFFSET VOLTAGE (µv) ALD1721E Advancd Linar Dvics 8 of 13
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd) EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN SUPPLY VOLTAGE (µv) 5 4 3 2 1 TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE EXAMPLE A: V OS EPAD PROGRAMMED AT V SUPPLY = +5V PSRR = 8 db EXAMPLE B: V OS EPAD PROGRAMMED AT V SUPPLY = +8V 1 2 3 4 5 6 7 8 9 1 SUPPLY VOLTAGE (V) EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE (µv) 5 4 3 2 1 THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE EXAMPLE B: V OS EPAD PROGRAMMED AT V IN = -4.3V EXAMPLE A: V OS EPAD PROGRAMMED AT V IN = V V SUPPLY = ±5V CMRR = 8dB EXAMPLE C: V OS EPAD PROGRAMMED AT V IN = +5V -5-4 -3-2 -1 1 2 3 4 5 COMMON MODE VOLTAGE (V) EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE (µv) 5 4 3 2 1 EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE FOR A COMMON MODE VOLTAGE RANGE OF.5V CMRR = 8dB COMMON MODE VOLTAGE RANGE OF.5V V OS EPAD PROGRAMMED AT COMMON MODE VOLTAGE OF.25V -.5 -.4 -.3 -.2 -.1..1.2.3.4.5 COMMON MODE VOLTAGE (V) ALD1721E Advancd Linar Dvics 9 of 13
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd) APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING Exampls of applications whr accumulatd total input offst voltag from various contributing sourcs is minimizd undr diffrnt sts of usr-spcifid oprating conditions 25 25 TOTAL INPUT OFFSET VOLTAGE (µv) 2 15 1 5-5 -1-15 -2-25 V OS BUDGET AFTER + X V OS BUDGET BEFORE TOTAL INPUT OFFSET VOLTAGE (µv) 2 15 1 5-5 -1-15 -2-25 V OS BUDGET AFTER + X V OS BUDGET BEFORE EXAMPLE A EXAMPLE B 25 25 TOTAL INPUT OFFSET VOLTAGE (µv) 2 15 1 5-5 -1-15 -2-25 V OS BUDGET BEFORE + EXAMPLE C X V OS BUDGET AFTER TOTAL INPUT OFFSET VOLTAGE (µv) 2 15 1 5-5 -1-15 -2-25 V OS BUDGET AFTER + EXAMPLE D X V OS BUDGET BEFORE + X Dvic input V OS PSRR quivalnt V OS CMRR quivalnt V OS T A quivalnt V OS Nois quivalnt V OS Extrnal Error quivalnt V OS Total Input V OS aftr EPAD Programming ALD1721E Advancd Linar Dvics 1 of 13
SOIC-8 PACKAGE DRAWING 8 Pin Plastic SOIC Packag E Millimtrs Inchs S (45 ) D Dim A A 1 b C D-8 E Min Max Min Max 1.35 1.75.53.69.1.25.4.1.35.45.14.18.18.25.7.1 4.69 5..185.196 3.5 4.5.14.16 1.27 BSC.5 BSC H 5.7 6.3.224.248 A A 1 b L ø S.6.25.937 8.5.24.1.37 8.2 S (45 ) H C L ø ALD1721E Advancd Linar Dvics 11 of 13
PDIP-8 PACKAGE DRAWING 8 Pin Plastic DIP Packag E E1 Millimtrs Inchs Dim A Min Max Min Max 3.81 5.8.15.2 A 1.38 1.27.15.5 A 2 1.27 2.3.5.8 b.89 1.65.35.65 S D b 1 c.38.2.51.3.15.8.2.12 D-8 9.4 11.68.37.46 b b 1 A2 A 1 L A E E 1 1 L S-8 ø 5.59 7.62 2.29 7.37 2.79 1.2 7.11 8.26 2.79 7.87 3.81 2.3 15.22.3.9.29.11.4.28.325.11.31.15.8 15 c 1 ø ALD1721E Advancd Linar Dvics 12 of 13
CERDIP-8 PACKAGE DRAWING 8 Pin CERDIP Packag E E 1 Millimtrs Inchs D Dim A A 1 Min Max Min Max 3.55 5.8.14.2 1.27 2.16.5.85 b.97 1.65.38.65 b 1.36.58.14.23 s A 1 C D-8.2 --.38 1.29.8 --.15.45 A E 5.59 7.87.22.31 E 1 7.73 8.26.29.325 L b L 2 b 1 L 1 1 L 2.54 BSC 7.62 BSC 3.81 5.8.1 BSC.3 BSC.15.2 L 1 L 2 3.18.38 -- 1.78.125.15 --.7 S -- 2.49 --.98 Ø 15 15 C 1 ø ALD1721E Advancd Linar Dvics 13 of 13