Lab 9 CMOS Logic Inverter ECE Department University of Colorado, Boulder 1
Prelab Read Section 4.10 (4th edition Section 5.8), and the Lab procedure Do and turn in Exercise 4.41 (page 342) Do PSpice (.dc) simulation to generate the voltage transfer characteristic of the inverter constructed using CD4007 transistors, as requested in Part 1 of the Lab procedure (page 5 of the Lab procedure). Make sure that you use the correct MOS device parameters (the parameters you found in Lab 7 for CD4007 devices). Turn in a plot of the voltage transfer characteristic obtained by simulation, and find VOL, VOH, VIL, VIH, and the noise margins NMH and NML for the CMOS logic inverter. Refer to the textbook Figure 4.56 (4th edition Figure 5.58). 2
Introduction Objectives: v OUT v OUT t PHL t PLH v OUT /2 /2 Test the voltage transfer characteristic of a CMOS inverter (CD4007) Evaluate the gate propagation delays and the power consumption as functions of the supply voltage and the clock frequency f c CMOS inverter circuit, symbol, and definition of propagation delays 3
CD4007 CMOS integrated circuit By shorting pins (8,13), and (1,5), CD4007 can be used to build three CMOS logic inverters as shown here: Power supply for the IC: Pin 14 should be connected to VDD Pin 7 should be connected to ground Do not forget to include power supply decoupling capacitors PSpice models (from 3250.lib library): *---------------------------------------------------------------------------------- * N4007 (NMOS on CD4007 CMOS integrated circuit) *.model N4007 NMOS (Kp=500u Vto=1.5 Lambda=0.01 Gamma=0.6 + Xj=0 Tox=1200n Phi=.6 Rs=0 Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 Cgso=0.1p Cgdo=0.1p Is=16.64p N=1) *---------------------------------------------------------------------------------- * P4007 (PMOS on CD4007 CMOS integrated circuit) *.model P4007 PMOS (Kp=500u Vto=-1.5 Lambda=0.04 Gamma=0.6 + Xj=0 Tox=1200n Phi=.6 Rs=0 Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8 Cgso=0.2p Cgdo=0.2p Is=16.64p N=1) * *---------------------------------------------------------------------------------- For PSpice simulations, do not forget to download the library file 3250.lib to your working folder. You should update the device parameters based on your Lab 7 results. 4
1. Voltage Transfer Characteristic (VTC) 1. Use the bench variable DC source to measure the voltage transfer characteristic of a CD4007 inverter at VDD=5V: V OUT as a function of V IN. 2. Report the experiment (include the circuit schematic and a plot of the measured characteristic. From the experimental VTC, find VOL, VOH, VIL, VIH, and the noise margins NMH and NML. Refer to text Figure 4.56 (4 th edition Figure 5.58). Compare the experimental results for the noise margins NMH and NML to the analytical results given in Section 4.10 (4 th edition section 5.8), and to the PSpice simulation results you obtained in the prelab assignment. Make sure that you use the correct device parameters (the parameters you found in Lab 7). Comment on the results. 5
2. Dynamic operation test circuit Variable DC voltage source R s 1 KΩ I DD + 10 μf 1 KΩ + V R s I DD pin 14 V 10 μf 0.1 μf place the decoupling capacitors close to the chip CD4007 1 v OUT1 v OUT2 pulsating 0-to-5 V signal from the lab function generator 1 2 2 pin 7 3 C load 100 pf ZVN2106 Notes: The propagation delays for the inverters 2 and 3 can be found using two oscilloscope voltage probes. Note that the inverter 3 has a capacitive load (100pF). Propagation delays for this inverter will be longer than for the inverter 2. The power consumption P of the three CMOS inverters on the CD4007 chip can be found as P = *I DD. Note that I DD can be obtained by measuring the voltage drop across R s 6
2. Delay and Power Experiments 1. Measure the propagation delays t PHL (high-to-low) and t PLH (low-to-high) for the inverters 2 and 3 as functions of the supply voltage. In this experiment, use the clock frequency f c of 100 KHz and change the supply voltage from 3V to 10V. 2. Measure the CD4007 power consumption P as a function of the clock frequency f c and the supply voltage. Use = 3 V, 5V, and 10V, and for each sweep f c from 1 KHz to a maximum frequency f cmax such that the output v OUT2 can reach nominal high and low logic levels ( and 0). Because of the voltage drop across R s, which is used to measure I DD, you may need to readjust the lab variable DC voltage source to maintain the desired supply voltage for the CD4007 chip. 3. Report details of the experiment. Include: 1. the circuit schematic 2. a plot of the measured waveforms (t), 1 (t), v OUT1 (t)=2 (t), v OUT2 (t) for one selected operating point (, f c ). 3. Excel plots showing the results of the experiment 1 (propagation delays). Comment on the results. Why are the delays of the two inverters different? Why do delays increase when the supply voltage is reduced? 4. Excel plots showing the results of the experiment 2 (power consumption). Try to fit the measured power data into the expression: P = C const 2 f c Based on the measurement data, what is C const? 5. If the load capacitor C load is removed, how does the power consumption P change? Why? To answer these questions, you do not need to repeat the entire experiment 2, just select a few (, f c ) points to measure what happens to the power consumption P without C load. 6. What is the purpose of the 1K-loaded ZVN2106 MOSFET in the test circuit on page 6? 7