Investigations on Compound Semiconductor High Electron Mobility Transistor (HEMT)

Investigations on Compound Semiconductor High Electron Mobility Transistor (HEMT) Nov. 26, 2004

Outline I. Introduction: Why needs high-frequency devices? Why uses compound semiconductors? How to enable high electron-mobility? Milestones II. Design Fundamentals: Doping Efficiency Carrier Confinement Channel Design Buffer Design Breakdown Considerations P. 2

Outline NDR Characteristics Device Processing Figure of Merits III. Some Practical Designs: (1) High-Temperature Breakdown Characteristics of δ-phemt. (2) Coupled δ-doped InAlAsSb/InP HFET. (3) Symmetric-graded Channel with Metamorphic Buffer (4) Composite-Channel with DIBL Phenomenon IV. Conclusions V. References Q&A P. 3

I. Introduction Why needs high-frequency devices? To provide component recipes for monolithic microwave/millimeter wave integrated circuit (MMIC) applications. Microwave: 0.1 GHz ~ 30 GHz Millimeter wave: 30 GHz ~ 300 GHz Why using compound semiconductors? 1. Intrinsic high-speed property: P. 4

I. Introduction Why using compound semiconductors? (continued) 2. Optical coupling capability: Suitable for opto-electronic integrated circuit (OEIC) implementations. 3. Controllable and composition-dependent material properties: 4. Variety of compound materials: Both provide high degree of design freedom. 5. Mature epitaxy growth technologies: LP-MOCVD, MBE Make possible excellent precision control of layer thickness and cost-effective mass-production. P. 5

I. Introduction How to enable high electron-mobility? By spatially separating electrons from their parent donors to greatly improve the ionized-impurity scattering. By devising an undoped channel compound, with high saturation velocity, where the transferred two-dimensional electron gas (2DEG) are confined and transport along under applied bias. High Speed!! Schematic band diagram of conventional HEMT: E Fm Gate Electrode Carrier Supplier + + + + + Undoped Spacer 2DEG undoped Channel E 1 E 0 E FS P. 6

I. Introduction Milestones: 1951: William Shockley proposed the 1st heterojunction device. A. I. Gubanov developed the 1st heterojunction theory. 1957: H. Kroemer published the 1st HBT. 1960: R. A. Anderson presented experimental of Ge-GaAs heterojuncion. 1969: L. Esaki and R. Tsu pointed out 2D carrier transport parallel to layers of a superlattice. 1970 s: Development of MBE & MOCVD technologies. 1978: R. Dingle et.al. observed the mobility enhancement of 2DEG of AlGaAs/GaAs MODFET. 1979: Wood et.al. realized δ-doping by MBE. 1980: Mirura et.al. & Delagebeaudeuf et.al. applied to FET s. 1983: T. E. Zipperian et.al. fist demonstrated GaAs-based PHEMT with single quantum well. P. 7

I. Introduction HFET SDHT MODFET HEMT TEGFET PHEMT DCFET HFET: Heterostructure Field-Effect Transistor MODFET: Modulation-Doped Field-Effect Transistor SDHT: Selectively-Doped Heterostructure Transistor HEMT: High Electron Mobility Transistor TEGFET: Two-Dimensional Electron Gas Field-Effect Transistor PHEMT: Pseudomorphic High Electron Mobility Transistor DCFET: Doped-Channel Field-Effect Transistor P. 8

II. Design Fundamentals Doping Efficiency: δ-doping technique was introduced to improve the doping efficiency and to increase the 2DEG concentration. Can also greatly improve the gate leakage as compared to the conventional homogeniously-doping technique. Schematic illustration of growing δ-doped GaAs: Si donors are located in an atomic monolayer of (100) GaAs crystal and replace the Ga sites to release electrons. X X X X Ga X As Si X X X X X X X X X X X X (100) Growth direction P. 9

II. Design Fundamentals Doping Efficiency: (continued) The real-space conduction band diagram of Si δ-doped InP layer with 2D doping concentration of 2.5 x 10 12 cm 2 : 1.E+03 Subband Energy (mev) 1.E+02 E F E1 E 0 1.E+01 Z 0 Z 1-56.0-42.7-26.9 0.0 26.9 42.7 56.0 Real-Space Extent ( nm ) P. 10

II. Design Fundamentals Doping Efficiency: (continued) 1. Upper δ-phemt : Gate Schottky Layer 2DEG Channel Buffer E C Φ B + E FM E F P. 11

II. Design Fundamentals Doping Efficiency: (continued) 2. Inverted δ-phemt : Gate Φ B Schottky Layer 2DEG Channel Buffer E C E FM + E F P. 12

II. Design Fundamentals Doping Efficiency: (continued) 3. Double δ-doped PHEMT : Gate Schottky Layer 2DEG Channel Buffer Φ B E C E FM + + E F P. 13

II. Design Fundamentals Carrier Confinement: By designing a narrow-gap and high-velocity quantum well channel, sandwiched by the wide-gap Schottky barrier and buffer layers. Or to design a V-shaped compositionally-graded channel to improve carrier confinement and transport properties at the same time. Channel Design: Fortunately, most narrow-gap compounds have distinguished transport characteristics. Yet, needs to carefully deal with the lattice-mismatch problems within the heterointerface. P. 14

Carrier Confinement Gate Schottky Layer 2DEG Channel Buffer E C Φ B + E FM E F V-Shaped Channel P. 15

Lattice Mismatch GaAs InGaAs Interfacial Strain Needs to be less than the critical layer thickness to prevent dislocation or even cracks. P. 16

Reference Table P. 17

II. Design Fundamentals Buffer Design: Wide-Gap Buffer: To suppress substrate leakages by forming buffer barrier. Superlattice Buffer: Can obtain high-temperature stability by prevent impurity gettering. Metamorphic Buffer: To design a composition-linearly-graded strained buffer on GaAs substrate to approach to the lattice constant of high-in ratio channel. For instance: In 0.53 Ga 0.47 As/In x Ga 1-x P/GaAs Using metamorphic structure on GaAs substrate to replace latticematched InP substrate to provide large size wafers with better transport properties. P. 18

Wide-Gap Buffer Gate Schottky Layer 2DEG Channel Wide-Gap Buffer E C Φ B + E FM E F P. 19

Superlattice Buffer Gate Φ B Schottky Layer 2DEG Channel + Superlattice Buffer E C E FM E F P. 20

II. Design Fundamentals Breakdown Considerations: Off-state breakdown: (Gate engineering) By employing gate recess through device processing. By forming high Schottky barrier height gate structure. On-state breakdown: (Channel engineering) Generally choose channel materials with lower impact ionization threshold field to improve kink effects. P. 21

Off-State Breakdown Thermionic Emission - - 2DEG Channel Buffer E C Φ B + E FM E F Gate Schottky Layer Gate engineering to improve the off-state breakdown. P. 22

On-State Breakdown P. 23

Solutions for On-State Breakdown 1. Channel Quantization: Quantized Channel due to reduced thickness to enhance the threshold energy for impact-ionization. Yet, cause a decrease in the sheet carrier concentration. P. 24

Solutions for On-State Breakdown 2. Composite Channel: InGaAs/InP composite channel with different threshold fields to improve impact ionization at high electric fields. P. 25

Solutions for On-State Breakdown 3. Body contact (BC) technology: Holes carriers in the channel are successfully drained through the body contact. P. 26

II. Design Fundamentals Negative-Differential Resistance (NDR) Characteristics: Applications for oscillator circuit implementation. In HEMT s, the N-shaped NDR characteristics are mostly initiated from the modulation of carrier concentration and velocity product through barrier-lowering, instead of the inter-valley transfer of the material intrinsic property. Needs to identify their initiation mechanisms. I DS N-Shaped NDR V DS P. 27

II. Design Fundamentals Device Processing: 1. Wafer clean and orienting 2. Mesa isolation 3. S/D Metallization & Annealing 4. Schottky Gate Deposition P. 28

Device Photo: II. Design Fundamentals P. 29

II. Design Fundamentals Figure of Merits: DC Characteristics: 1. Extrinsic Transconductance g m = I D V GS 2. Drain-Source Saturation Current Density (I DSS ): usually divided by gate width to provide normalized expression. 3. Breakdown Voltages: 2-terminal off-state BV 3-terminal on state BV criteria: I G = 1 ma/mm 4. Gate-Voltage Swing (GVS): corresponding gate voltage range for an averaged Gm plateau. 5. Pinch-Off Characteristics: prevent leakages problem. P. 30

Off-State BV: II. Design Fundamentals Gate Current Density (ma/mm) 8 4 0-4 BV -60-40 -20 0 Gate-Drain Voltage (V) P. 31

II. Design Fundamentals On-State BV: 0.0 Gate Current Desnity (ua/mm) -0.5-1.0-1.5-2.0 Increased V DS -2.5-2.0-1.5-1.0-0.5 0.0 0.5 Gate-Source Voltage (V) P. 32

I-V characteristics: 250 II. Design Fundamentals Drain Current Density (ma/mm) 200 150 100 50 I DSS g m = I DS / V GS Pinch-off 0 0 2 4 6 Drain-Source Voltage (V) P. 33

II. Design Fundamentals Gate-Voltage Swing (GVS): Saturation Current Density (ma/mm) 250 200 150 100 50 GVS g m, max I DSS 0-3 -2-1 0 1 2 100 80 60 40 20 0 Extrinsic Transconductance (ms/mm) Gate Voltage (V) P. 34

II. Design Fundamentals Figure of Merits: AC Characteristics: 1. Cut-Off Frequency: unity-gain frequency, transition frequency, gain-bandwidth frequency. 2. Max. Oscillation Frequency : where max. power gain is equal to unity. 3. Power Gain: A = P P 4. Power-Added Efficiency (P.A.E.): P out in 5. Noise Figure (NF): Pout Pin P. A. E. = 100% P NO N. F. = = P P NI DC A P P P SI SO P P NI NO P. 35

III. Some Practical Designs: 1. High-Temperature Breakdown Characteristics of δ-doped In 0.49 Ga 0.51 P/GaAs/In 0.25 Ga 0.75 As/AlGaAs HEMT Goal: To provide high power, high-temperature breakdown and good pinchoff characteristics and by using high barrier Schottky In 0.49 Ga 0.51 P contact layer and Al 0.25 Ga 0.75 As buffer layer. Source (AuGe/Ag) Gate (Au) Drain (AuGe/Ag) Schematic cross section: n+ GaAs 800 Å δ(n + ) i-ingap 500 Å i-ingap Spacer 60 Å i-gaas Subspacer 60 Å i-ingaas Channel 100 Å i-algaas Buffer 4μm S.I. GaAs Substrate P. 36

III. Practical Design (1): Calculated band diagram, 2DEG distribution and wave functions, Ψ 0 and Ψ 1. (E 0 = -114 mev, E 1 = -10 mev) : 2 1.5 N 2DEG Conduction Band (ev) 1 0.5 0 Ψ 1 Ψ 0 V GS = -0.19 V -0.5 0 200 400 600 800 1000 Z (Å) P. 37

III. Practical Design (1): I-V characteristics with a gate geometry of 1.5 x 125 µm 2 at 300 K: 250 Drain Current Density (ma/mm) 200 150 100 50 V GS = 0.5 V; -0.5V/step 0 0 2 4 6 Drain-Source Voltage (V) P. 38

III. Practical Design (1): Extrinsic transconductance and saturation current density vs. gate voltage at 300 K: Saturation Current Density (ma/mm) 250 200 150 100 50 0-3 -2-1 0 1 2 Gate Voltage (V) 100 80 60 40 20 0 Extrinsic Transconductance (ms/mm) P. 39

III. Practical Design (1): Two-terminal gate-to-drain breakdown characteristics at 300K. The inset indicates the temperature variation up to 500K. 5 Gate Current Density (mev) 8 4 0 4 3 2 1 0-1 420K 460K 500K -40-30 -20-10 0 10-4 -60-40 -20 0 Gate-Drain Voltage (V) P. 40

III. Practical Design (1): Device superiorities: Excellent two-terminal gate-drain breakdown voltages of 62 V (300 K) and 42 V (500 K) were obtained. as compared to (300 K) : 52 V for InGaP/GaAs/InGaAs camel-like FET 45 V for LTG GaAs MISFET 33 V for buried-gate InGaP/AlGaAs/InGaAs HFET Improved gate-voltage swing (GSW) of 2.3 V and good pinch-off properties by using a carrier-retarding AlGaAs buffer layer. Promising for high power and high temperature ambient operations. P. 41

III. Practical Design (2): A Novel Coupled δ-doped InAlAsSb/InP HFET: Advantages: Fully InP compound HFET structure: (1) high saturation velocity (2) large Γ-L separation (~0.54 ev) (3) better thermal conductivity (4) large bandgap (~1.35 ev) (5) lower impact ionization coefficient. First using quaternary In 0.34 Al 0.66 As 0.85 Sb 0.15 Schottky barrier: High energy gap (~1.8 ev), high Schottky barrier (>0.73 ev) InAlAsSb together with InP and InGaAs, respectively, can form type II heterostructure to achieve better carrier confinement. Fully lattice-matched to InP!! P. 42

III. Practical Design (2): Schematic diagram single/couple δ-doped (SD/CD) HFET s : CD-HFET SD-HFET n + -InP Cap layer 20 nm n + -InP Cap layer 20 nm i- In 0.53 Ga 0.47 As Setback 10 nm i- In 0.53 Ga 0.47 As Setback 10 nm i-in 0.34 Al 0.66 As 0.85 Sb 0.15 Schottky layer 40 nm i-in 0.34 Al 0.66 As 0.85 Sb 0.15 Schottky layer 40 nm i-inp layer 10 nm i-inp layer 15 nm δ-doping i-inp layer 9 nm i-inp layer 0.5 µm i-inp layer 0.5 µm S. I. InP Substrate S. I. InP Substrate P. 43

III. Practical Design (2): Conduction band diagram of the In 0.34 0.34 Al 0.66 As 0.85 Sb 0.15 0.15 /InP CD-HFET: P. 44

III. Practical Design (2): Profile of 2DEG concentration-mobility vs. spacer thickness (Å): 2DEG Concentration-Mobility Product ( V -1 Sec -1 ) 1.2E+14 1.0E+14 8.0E+13 6.0E+13 4.0E+13 2.0E+13 0.0E+00 0 100 200 300 Position (Å) 110 90 70 50 P. 45

III. Practical Design (2): Comparisons of device characteristics for SD-HFET and CD-HFET with the gate dimensions of 1.5 x 125 µm 2 : Device structure Output conductance (ms/mm) Extrinsic transconductance (ms/mm) Two-terminal BV GS (V) Three-terminal on-state BV (V) Three-terminal off-state BV (V) SD-HFET 0.5 37 >20 18.6 36 CD-HFET 1.8 52 >40 16.1 40.8 P. 46

III. Practical Design (2): Current gain (H21) and maximum available gain (MAG) spectrum : Gain (db) f T = 7 GHz f max = 12 GHz Frequency (Hz) P. 47

III. Practical Design (2): Device superiorities: 1. Improved device characteristics of CD-HFET over SD-HFET due to the devised coupling of the subband wave functions between the two δ-doped InP layers. 2. Excellent breakdown characteristics have been achieved by using the high-barrier height quaternary compound In 0.34 Al 0.66 As 0.85 Sb 0.15 Schottky layer. 3. Fully lattice-matched recipe and can provide good potential for high power applications. P. 48

III. Practical Design (3): V-Shaped Symmetric-graded InAlAs/InGaAs Metamorphic HEMT: Schematic cross section: P. 49

III. Practical Design (3): Calculated band diagram and 2DEG distribution : P. 50

III. Practical Design (3): Comparisons of Hall measurement results with other works: P. 51

III. Practical Design (3): Output Characteristics: Gm, max = 185 ms/mm, Idss = 340 ma/mm P. 52

III. Practical Design (3): High-frequency characteristics: f T = 18.9 GHz f max = 48.4 GHz P. 53

Power Characteristics : III. Practical Design (3): P out, max = 15.87 dbm (193.2 mw/mm) PAE = 31.6 % P. 54

III. Practical Design (3): Device superiorities: 1. Superior transport characteristics due to improved interface roughness scattering. 2. Improved carrier confinement due to V-shaped channel. 3. Can grow high-in epitaxial layers on large-size GaAs wafer by using metamorphic buffer. P. 55

III. Practical Design (4): Composite-Channel with Drain-Induced Barrier-Lowering (DIBL) Phenomenon: Thermal Equilibrium Onset of DIBL P. 56

III. Practical Design (4): Observed current step-up due to carrier velocity modulation: P. 57

III. Practical Design (4): Double-Gm plateaus with Gm = 269 & 116 ms/mm : P. 58

III. Practical Design (4): High-frequency characteristics: f T = 15.5 GHz f max = 23 GHz P. 59

III. Practical Design (4): Device superiorities: 1. Increased current drive by current step-up due to carrier velocity modulation phenomenon. 2. Intervally transfer has been excluded due to higher valley separation (0.52 ev) than the conduction discontinuities (0.23 ev). 3. Interesting double-gm-plateau with margin of more than 1.2 V can be applied to high-speed multiple-state quantizer or ADC converters. P. 60

IV. Conclusions Superior device characteristics targeting for various application-specific IC (ASIC) design applications have been research focus through engineering of device structures and materials. Device modeling and theoretical simulation is essential for establishing convenient, efficient and cost-effective design platform. Contemporary high-speed III-V compound-based HFET s has pioneered into GaN-series materials due to its distinguished intrinsic properties, including : (1) wide bandgap: ~ 3.4 ev (2) high saturation velocity: ~ 2.7 x 10 7 cm/s (3) high breakdown electric field: ~ 3 MV/cm (7.5 times of GaAs) Prosperity of academic and industrial achievements on MMIC technologies are promisingly expected in the near future. P. 61

V. References 1. C. S. Lee, W. C. Hsu, J. C. Huang, Y. J. Chen, and H. H. Chen, Monolithic AlAs/InGaAs/InGaP/GaAs Heterostructure Resonant Tunneling Field-Effect Transistors with PVCR of 960 at 300 K, accepted and to be published in IEEE Electron Device Lett., Feb. 2005. (SCI, EI) (NSC 93-2215-E-035-005) 2. C. S. Lee, and W. C. Hsu, Functional characteristics in asymmetric source/drain InAlAsSb/InGaAs/InP δ- doped high electron mobility transistor, revised in Appl. Phys. Lett.. (SCI, EI) (NSC 93-2215-E-035-005) 3. Y. J. Chen, W. C. Hsu, C. S. Lee, T. B. Wang, Y. S. Lin, and C. L. Wu, High-Temperature Thermal Stability Performance in δ-doped In0.425Al0.575As/ In0.65Ga0.35As Metamorphic HEMT, revised in IEEE Electron Device Lett.. (SCI, EI) (NSC 93-2215-E-035-005) 4. Y. J. Chen, W. C. Hsu, C. S. Lee, T. B. Wang, C. H. Tseng, J. C. Huang, D. H. Huang, and C. L. Wu, Gatealloy-related kink effect for metamorphic high electron mobility transistors, Appl. Phys. Lett., vol. 85, no. 21, pp. 5087-5089, May 2004. (SCI, EI) (NSC 93-2215-E-035-005) 5. Y. J. Li, W. C. Hsu, I. L. Chen, C. S. Lee, Y. J. Chen, and I. Lo, Improved Characteristics of Novel Metamorphic InAlAs/InGaAs HEMT with Symmetric Graded InxGa1-xAs Channel, J. Vac. Sci. Technol. B, vol. 22, no. 5, pp. 2429-2433, Sep. 2004. (SCI) (NSC 92-2215-E-006-014) 6. C. S. Lee, and W. C. Hsu, Double-Transconductance-Plateau Characteristics in InGaAs/GaAs Real-Space Transfer High Electron Mobility Transistor, Appl. Phys. Lett., vol. 84, no. 18, pp. 3618-3620, May 2004. (SCI, EI) (NSC 93-2215-E-035-005) 7. C. S. Lee and W. C. Hsu, Off-State Breakdown Modeling for High Schottky Barrier Height δ-doped Heterostructures, Jpn. J. Appl. Phys., Part I, vol. 42, no. 7A, pp. 4253-4256, 2003. (SCI) (NSC 91-2215- E-270-003) 8. W. C. Hsu, C. S. Lee and Y. S. Lin, Characterizations of the δ-doped InP Heterostructures Using In0.34Al0.66As0.85Sb0.15 Schottky Layer, J. Appl. Phys., vol. 91, no.1, pp. 1385-1390, 2002. (SCI) (NSC 89-2215-E-006-033) 9. C. S. Lee, W. C. Hsu and C. L. Wu, Analytic Modeling for Drain-Induced Barrier Lowering Phenomenon of the InGaP/InGaAs/GaAs Pseudomorphic Doped-Channel Field-Effect Transistor, Jpn. J. Appl. Phys., Part I, vol. 41, no. 10, pp. 5919-5923, 2002. (SCI) (NSC 91-2215-E-270-003) 10. C. S. Lee, W. C. Hsu, Y. W. Chen, Y. C. Chen and H. M. Shieh, High-Temperature Breakdown Characteristics of δ-doped In0.49Ga0.51P/GaAs/In0.25Ga0.75As/AlGaAs High Electron Mobility Transistor, Jpn. J. Appl. Phys. Lett., vol. 39, no.10b, pp. L1029-L1031, 2000. (SCI) (NSC 89-2215-E-006-013) P. 62

~ The End ~ Many thanks!! For more discussions, Feel free contact our lab. by Email: cslee@fcu.edu.tw P. 63