EECS 452 Midterm Closed book part Winter 2013

Similar documents
EECS 452 Midterm Exam Winter 2012

EECS 452 Midterm Exam (solns) Fall 2012

EECS 452 Practice Midterm Exam Solutions Fall 2014

Problem Point Value Your score Topic 1 28 Filter Analysis 2 24 Filter Implementation 3 24 Filter Design 4 24 Potpourri Total 100

Problem Point Value Your score Topic 1 28 Discrete-Time Filter Analysis 2 24 Improving Signal Quality 3 24 Filter Bank Design 4 24 Potpourri Total 100

Final Exam. EE313 Signals and Systems. Fall 1999, Prof. Brian L. Evans, Unique No

Team proposals are due tomorrow at 6PM Homework 4 is due next thur. Proposal presentations are next mon in 1311EECS.

The University of Texas at Austin Dept. of Electrical and Computer Engineering Midterm #1

SCUBA-2. Low Pass Filtering

Problem Point Value Your score Topic 1 28 Discrete-Time Filter Analysis 2 24 Upconversion 3 30 Filter Design 4 18 Potpourri Total 100

y(n)= Aa n u(n)+bu(n) b m sin(2πmt)= b 1 sin(2πt)+b 2 sin(4πt)+b 3 sin(6πt)+ m=1 x(t)= x = 2 ( b b b b

Design of Bandpass Delta-Sigma Modulators: Avoiding Common Mistakes

CS3291: Digital Signal Processing

Final Exam Solutions June 7, 2004

The University of Texas at Austin Dept. of Electrical and Computer Engineering Final Exam

PROBLEM SET 6. Note: This version is preliminary in that it does not yet have instructions for uploading the MATLAB problems.

EE 470 Signals and Systems

ASN Filter Designer Professional/Lite Getting Started Guide

The University of Texas at Austin Dept. of Electrical and Computer Engineering Midterm #2

ECE 5650/4650 Exam II November 20, 2018 Name:

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

EEM478-WEEK8 Finite Impulse Response (FIR) Filters

Project 2 - Speech Detection with FIR Filters

DSP Laboratory (EELE 4110) Lab#10 Finite Impulse Response (FIR) Filters

EECS 473 Final Exam. Fall 2017 NOTES: I have neither given nor received aid on this exam nor observed anyone else doing so. Name: unique name:

READ THIS FIRST: *One physical piece of 8.5x11 paper (you may use both sides). Notes must be handwritten.

F I R Filter (Finite Impulse Response)

Part B. Simple Digital Filters. 1. Simple FIR Digital Filters

Performance Analysis of FIR Filter Design Using Reconfigurable Mac Unit

Multirate DSP, part 3: ADC oversampling

Multirate DSP, part 1: Upsampling and downsampling

ECE438 - Laboratory 7a: Digital Filter Design (Week 1) By Prof. Charles Bouman and Prof. Mireille Boutin Fall 2015

Project 2. Project 2: audio equalizer. Fig. 1: Kinter MA-170 stereo amplifier with bass and treble controls.

ijdsp Workshop: Exercise 2012 DSP Exercise Objectives

You CAN Do Digital Filtering with an MCU!

Final Exam Solutions June 14, 2006

(i) Understanding of the characteristics of linear-phase finite impulse response (FIR) filters

AutoBench 1.1. software benchmark data book.

Digital Signal Processing. VO Embedded Systems Engineering Armin Wasicek WS 2009/10

E Final Exam Solutions page 1/ gain / db Imaginary Part

B.Tech III Year II Semester (R13) Regular & Supplementary Examinations May/June 2017 DIGITAL SIGNAL PROCESSING (Common to ECE and EIE)

SMS045 - DSP Systems in Practice. Lab 1 - Filter Design and Evaluation in MATLAB Due date: Thursday Nov 13, 2003

DSP Filter Design for Flexible Alternating Current Transmission Systems

Digital Filters IIR (& Their Corresponding Analog Filters) Week Date Lecture Title

Filter Design, Active Filters & Review. EGR 220, Chapter 14.7, December 14, 2017

(i) Understanding of the characteristics of linear-phase finite impulse response (FIR) filters

Lowpass A low pass filter allows low frequencies to pass through and attenuates high frequencies.

Lab 4 Digital Scope and Spectrum Analyzer

II Year (04 Semester) EE6403 Discrete Time Systems and Signal Processing

Lecture 3 Review of Signals and Systems: Part 2. EE4900/EE6720 Digital Communications

Design of FIR Filters

GEORGIA INSTITUTE OF TECHNOLOGY. SCHOOL of ELECTRICAL and COMPUTER ENGINEERING. ECE 2026 Summer 2018 Lab #8: Filter Design of FIR Filters

EE247 Lecture 26. EE247 Lecture 26

ESE531 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Signal Processing

IIR Filter Design Chapter Intended Learning Outcomes: (i) Ability to design analog Butterworth filters

ECE 429 / 529 Digital Signal Processing

Frequency Response Analysis

RTTY: an FSK decoder program for Linux. Jesús Arias (EB1DIX)

6 Sampling. Sampling. The principles of sampling, especially the benefits of coherent sampling

DSP First Lab 08: Frequency Response: Bandpass and Nulling Filters

2) How fast can we implement these in a system

Application Note, V1.0, March 2008 AP XC2000 Family. DSP Examples for C166S V2 Lib. Microcontrollers


Multirate Digital Signal Processing

Electrical & Computer Engineering Technology

Signal Processing. Naureen Ghani. December 9, 2017

System analysis and signal processing

Signal Processing. Introduction

ECE 4213/5213 Homework 10

THIS work focus on a sector of the hardware to be used

AC : FIR FILTERS FOR TECHNOLOGISTS, SCIENTISTS, AND OTHER NON-PH.D.S

EECS 373 Design of Microprocessor-Based Systems

Digital Signal Processing

Time: 3 hours Max Marks: 70 Answer any FIVE questions All questions carry equal marks *****

Appendix B. Design Implementation Description For The Digital Frequency Demodulator

CHAPTER 14. Introduction to Frequency Selective Circuits

Subtractive Synthesis. Describing a Filter. Filters. CMPT 468: Subtractive Synthesis

LECTURE 3 FILTERING OBJECTIVES CHAPTER 3 3-1

McGraw-Hill Irwin DIGITAL SIGNAL PROCESSING. A Computer-Based Approach. Second Edition. Sanjit K. Mitra

The 29 th Annual ARRL and TAPR Digital Communications Conference. DSP Short Course Session 4: Tricks of the DSP trade. Rick Muething, KN6KB/AAA9WK

Signals and Systems Lecture 6: Fourier Applications

Discrete-Time Signal Processing (DTSP) v14

EECS 373 Design of Microprocessor-Based Systems

Real time digital audio processing with Arduino

Part One. Efficient Digital Filters COPYRIGHTED MATERIAL

DATA INTEGRATION MULTICARRIER REFLECTOMETRY SENSORS

1 PeZ: Introduction. 1.1 Controls for PeZ using pezdemo. Lab 15b: FIR Filter Design and PeZ: The z, n, and O! Domains

Gábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/57

Pre-Lab. Introduction

Advanced Digital Signal Processing Part 5: Digital Filters

Lab 6. Advanced Filter Design in Matlab

GUJARAT TECHNOLOGICAL UNIVERSITY

AC : INTERACTIVE LEARNING DISCRETE TIME SIGNALS AND SYSTEMS WITH MATLAB AND TI DSK6713 DSP KIT

UNIVERSITY OF CALIFORNIA. EECS 145M: Microcomputer Interfacing Lab

INTRODUCTION TO FILTER CIRCUITS

Signals and Filtering

EE 403: Digital Signal Processing

ECE 6560 Multirate Signal Processing Chapter 11

Digital Filters FIR and IIR Systems

Rapid Design of FIR Filters in the SDR- 500 Software Defined Radio Evaluation System using the ASN Filter Designer

Transcription:

EECS 452 Midterm Closed book part Winter 2013 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points Closed book Page 2 /17 Page 3 /10 Open book /73 Total /100 NOTES: There are 3 pages including this one. On the closed book section you may not have books, notes, or calculator. Nothing but a writing utensil. Don t spend too much time on any one problem. You have about 120 minutes for the exam. You probably shouldn t spend much more than 20 minutes on this section. 1

Closed book portion 1. Say you took a 16-point DFT of the following signals with f s =3.2 KHz starting at time t=0. What would the non-zero DFT outputs be (magnitude and phase)? [3 points each] a. 2*sin(2 π *400t+ π/2) X(2)=16 0 ; X(14)=16 0 b. 2*cos(2 π *800t) - 2 X(0)=32 π ; X(4)=16 0 ; X(12)=16 0 ; 2. An FIR filter has the impulse response shown below. Assume f s =1ms. [2 points each] 2 2 0 1 2 3 4 5 a. What is the difference equation for this filter? y(n)=2*x(n-2)+2*x(n-4) b. What is the transfer function for this filter? H(z)=2*z -2 + 2*z -4 c. Is this filter linear? If so, what is the group delay? If not, why not? Yes. 3ms. 3. Write a legal C function named mult16 which takes two 16-bit Q15 numbers as arguments and returns their product as a 16-bit Q15 rounding appropriately. Use short as a 16-bit signed data type. [5 points] short mult16(short a, short b) { int tmp=(int)a*b; //NOTE: cast isn t needed here as //as multiplication defaults to an int. return((short)(tmp+0x4000)>>15)); //cast also not needed } 2

4. Fill in the blank or circle the best answer. Provide all numbers in decimal. [10 points, -1 per wrong or blank answer, minimum 0] a. If we multiply an 8-bit Q6 value by an 8-bit Q6 value the result would be a 16 -bit Q 12 number. b. -4 is the smallest number (closest to negative infinity) that can be exactly represented by a signed 11-bit Q8 number. 1.875 is the largest number (closest to positive infinity) that can be exactly represented by a signed 5-bit Q3 number. c. In signed 5-bit two s complement Q3, what is the value of 10010? -1.75. d. We say a filter has linear phase if the group delay is independent of the input frequency / proportional to the input frequency / greater than the input frequency. e. Say you have an ideal A to D converter which converts values from 4V to -4V to a 5-bit value. In the ideal case, the worst-case quantization error is ±.125 Volts. f. One advantage of IIR filters compared to FIR filters is that IIR filters tend to use fewer total components to implement the same functionality / be easier to make linear phase / be easier to make stable. g. FIR filters can easily / cannot / can with great difficulty implement a typical RC analog filter. h. Most computers don t have a MAC instruction because it would likely cause the clock period to get longer. they don t have an accumulator. it interferes with floating point support. i. DSPs, on the other hand, do tend to have a MAC instruction because they generally do have an accumulator. they commonly can take advantage of MAC instructions. they don t generally have floating point instructions. they have a very slow clock period to begin with. j. An N-point implementation of the FFT algorithm discussed in class requires approximately N 2 / N 1.5 / N*log(N) / N operations. k. A waveform is sampled using a sample rate of 42 KHz. If you desire a frequency spacing of 2 Hz in the DFT of the sample set, you ll need to sample for _500 ms. 3

EECS 452 Midterm Open book part Winter 2013 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points Open book Page 2 /11 Page 3 /11 Page 4 /12 Page 5 /15 Page 6 /11 Page 7 /13 Total /73 NOTES: There are 7 pages including this one. On the open book section you may use calculators, books and notes, but no PDAs, Portables, Cell phones, etc. Don t spend too much time on any one problem. You have about 120 minutes for the entire exam. Some questions are much harder than others When asked to show your work do so. If the question asks you to show your work and you don t you will get no points, even if the answer is correct. If you need to use the back of the exam paper for your answers, you must make it clear that the grader is to look there. 1

Short answer: 1. Say you took a 32-point DFT of the following signals with f s =1.6 KHz starting at time t=0. What would be what the non-zero DFT outputs would be (magnitude and phase)? Briefly justify your answers. [6 points, 3 points each] 2*sin(2 π *1000t) freq spacing=50hz. n=20, so X(20)=32-90 ; X(n-20) is X(12)=32 90 ; 2*cos(2 π *1600t- π/8) This one is probably harder. Can do it the same as above. In that case, X(n)=X(32-n)=X(0). So really taking the two vectors and adding them. Could do that. Another way to tackle this is to note we are sampling 2*cos(π/8) 32 times. So 32*2* cos(π/8) = 59.13 0. 2. Answer the following questions about the ideal digital-to-analog converter shown below. [5 points] a. Assuming Vref=12V and R=1kΩ, if D[3:0]=1001, what is Iout? [3] I in =12mA. 9*12mA/16=6.75mA b. If we were going to make a 12-bit converter using this R/2R ladder scheme, how many resistors would we need? [2] 24 2

3. Say you are building an FIR bandpass filter that will have a passband of 1KHz centered at 8KHz. Further, say that there is a fair bit of signal in the input up to 40KHz. [8 points] Without an anti-aliasing filter, what is the lowest frequency you could sample the data? [3] 48.5KHz. What would happen if you sampled at a lower frequency than that? [2] Some of that signal would end up in the frequency we wanted to sample. Draw the picture, it s pretty easy to see. If you do have a (low-pass) anti-aliasing filter which has a passband that ends at 10KHz and a stopband that starts at 20KHz, what is the lowest frequency you could sample the data? You are to assume the gain of the anti-aliasing filter is 1.0 in the passband, 0 in the stopband, and unknown otherwise. [3] 28.5KHz 4. Draw a block diagram which corresponds to the following difference equation. [3 points] y[n]= x[n-1] +x[n-3] y[n-2] No answer provided 3

5. Consider the following difference equation [6 points] y[n] = x[n] + 0.2 * x[n-2] + 0.4 * y[n-2] Write the transfer function which corresponds to that difference equation. [3] Is that filter stable? Show your work. [3] Yes, it s stable if the poles are in the unit circle. z 2 +0.4 has roots of about +/-0.63, so they are in the unit circle. 6. Answer the following question using the above figures. Assume Vref=4V and that all converters are ideal. [6 points] a. If 2.4V is put into the ADC and D out is connected to D in of of DAC#1, what is the value found on V out of DAC#1? [2] 2.0V b. If 2.4V is put into the ADC and D out is connected to D in of of DAC#2, what is the value found on V out of DAC#2? [2] 2.5V c. If D in of DAC#2 is 01 and the output of that DAC is connected to the V in of the ADC, what is the output of the ADC? [2] 01 4

Longer answer 7. Consider the following filter transfer function: Write a function, int trans(int x, int *w) which takes a single input x, and returns the output of the filter. You may assume that the array w is of any fixed size you find useful. All inputs are in 32-bit Q31 and the output is also to be in 32-bit Q31. If the output is determined to be outside of the range of a 32-bit Q31 you should saturate. You are to write this for a machine where an int is 32 bits and a long is 64 bits. This function will be called iteratively with a new value of x passed in each cycle but with a pointer always to the same w, so your code needs to update w appropriately in addition to returning the output value. [15 points] int trans(int x, int *w) { long y; w[3]=w[2]; w[2]=w[1]; w[1]=w[0]; w[0]=x; y=(long)w[1]-2*w[3]; return((y+0x2)>>2); } The above answer is taking advantage of a lot of characteristics of this FIR filter. For one, overflow is impossible as the largest output at any given time is 0.75. For another, both coefficents are powers of two, making it really easy to write those terms as Q2 numbers. Then we need to round and divide/shift. Done. Most people had more complex answers and thus had more complex errors 5

8. Consider the following pole/zero plot [11 points] a) What type of filter (lowpass, highpass, bandpass, bandstop) is this? [2] Bandpass. b) Draw a rough sketch of the frequency response of this filter assuming f s =10kHz. [3] 0Hz 1.25kHz 5KHz c) Circle the pole-zero combination that you would use for each biquad section to minimize the likelihood of overflow in your fixed-point implementation. Label each combination (1, 2, etc.) corresponding to the order you would cascade the biquad sections (the biquad section closest to the input being 1, the next 2, etc.) [6] No answer provided. There are a lot of correct answers to this one given that a number of poles look equidistant to the unit circle. 6

9. FFTs in the real world: [13 points] On this question we will explore an FFT implementation on a processor and explore the impact interrupts have on our ability to do DSP work. For this entire problem, assume the following: An N-point implementation of the FFT requires N/2 log N complex arithmetic operations, where N must be a power of 2. Was clarified to be log base-2 at the exam. Each complex arithmetic operation consumes 5 clock cycles on a CPU with a clock frequency of 100MHz. We are sampling audio data at a rate of 50 khz. Our application requires us to not miss any of our samples. a) Say we ve written our program such that we grab X samples from our ADC as they come in and then after the last has arrived we need to start and complete our computation of the FFT over those X samples before the next sample arrives. (So we can do real-time spectrum analysis.) What is the largest FFT we ll be able to compute (that is, the largest value of X)? What will be the frequency resolution of that FFT? Clearly show your work! [5] (During exam it was clarified that log was intended to be log base 2!) 100MHz/50kHz=2000 cycles. 5 cycles/op=400 operations. N/2*lg(N)<400 is N=64 (64*6/2)=192. That gives us 50kHz/64=781Hz. b) Now let us assume that: We have a timer that interrupts our processor at a rate of 50 khz and that that interrupt routine grabs a sample for us. The interrupt routine takes 50 cycles to run. i) If we want to do real-time spectrum analysis, what is the largest FFT would be able to compute? Don t worry if your answer seems unrealistic. Clearly show your work. [4] Get 390*N operations total if doing an N point FFT. Need N/2*lg(N) operations. That quickly gives us 390N N*lg(N)/2. 780 lg(n). The greatest N this holds for is 2 780. Not realistic (that would take longer to grab than the age of the universe by a massive amount!), but tells us that the sky is the limit. ii) If all other assumptions remain the same, what is the slowest clock frequency the processor could have and still be able to do a 1024 point FFT in real-time? Clearly show your work! [4] Well, we need to be able to have 1024/2*10*5=25600 cycles over 1024 samples. Those samples take 1024*50=51200 cycles for the interrupt routine to run. So basically 75 cycles per sample. That comes out to 75*50kHz=3.750MHz. 7