Design f the Bst-Buck cnverter with HV9930 Cnsider a bst-buck cnverter with the fllwing parameters (Fig. -. D L C L - VN Q d Cd D D3 C VO cs cs + s VN HV9930 VDD C sa sb GATE CS PWMD CS ref ref GND EF C3 Fig. -: Bst-Buck Cnverter using HV9930 nput Vltage: Vin,min 9V Vin,nm 3.5V Vin, 6V V in, tr 4V (Clamped lad dump rating V in, rev 4V (everse plarity vltage Lad: V 8V 350mA LED 5.6Ω Estimated Efficiencies: ηmin 0.7 (at Vin,min ηnm 0.80 η 0.8 These efficiency values d nt take int accunt the pwer lss in the reverse blcking dide. The dide will dissipate pwer in the range f 0.4 0.6W and will drp abut Vd 0.5V acrss it. This dide drp will be taken in accunt while designing the cnverter.
The efficiency values used in this design are typical values fr the given input vltages and utput pwer level. Higher efficiencies can be btained at lwer input current levels. The efficiency values will depend n the perating cnditins. Except in very high pwer designs, these values can be used as a gd apprximatin. The efficiency drp at lwer input vltages is due t the larger input currents and its assciated cnductin lsses. Nte: Efficiencies higher than 85% can easily be achieved with the HV9930 cntrlled Ĉuk cnverter if the perating frequency is kept belw 50kHz. Hwever, fr purpses f EM cmpliance, the higher efficiencies are traded-ff fr higher switching frequencies (which increase switching lsses in the system. Design f the Pwer Stage Step : Chse a switching frequency at the minimum input vltage Althugh the HV9930 is a variable frequency C, the selectin f the switching frequency is an imprtant criterin, as this will decide the pint arund which the actual frequency will vary. n the case f autmtive cnverters, designing with a switching frequency in the range between 300kHz and 530kHz wuld avid the restricted radi bradcast bands and make it easier t meet the cnducted and radiated EM specificatins. S, chse a minimum switching frequency (which ccurs at minimum input vltage fs, min 300kHz. Step : Cmpute the duty cycle The duty cycle f peratin will have t be cmputed at the minimum input vltage. D ηmin + 0.8 ( V V in,min V d (- Step 3: Cmpute the input current values The input current level at the minimum input vltage needs t be cmputed. The value btained will be used t cmpute the current ratings f the varius cmpnents. in, V η min ( Vin,min Vd (-.60A Step 4: Cmpute the utput inductr The first step is t cmpute the ff-time. The ff-time f the cnverter can be calculated as: Tff D fs,min 598ns (-3 3
Assuming a 5% peak-t-peak ripple in the utput current ( i 87.5mA, and accunting fr the dide drp in the input vltage by substituting Vin,min Vd in place f V in, equatin (7 yields: 598ns 0.887 3 L 3 + 3.5m L +.89µ L µ (-4 Slving fr L using (, (3 and (4 gives: 3 ( 0.05 45 H L µ The clsest standard value inductr is a 50µH, 0.35A rms, 0.4A sat inductr. Since the inductance value is different frm the cmputed value, the actual ff-time will als change as: Tff.777 µ 3 L 66ns + 3.5m L, ac (-5 The actual ripple in the utput current is given by: i V Tff L 0.5 A (-6 Nte that althugh the ripple in the utput current was assumed t be abut 5% (r 87.5mA, the actual ripple is almst duble that value. This increase in the ripple is due t the delays f the cmparatrs. A capacitr will be required at the utput f the cnverter (acrss the LEDs t reduce the ripple t the desired level. This capacitr will be very small as the switching frequencies are large. t is als useful t cmpute the ripple versht and undersht beynd the prgrammed limits. This will help determine hw the average current changes due t the delays. iver V Vin,min Vd K 3 L L V 8.3mA iunder V L K 3 3 L 9mA (-7 (-8 Thus, the average utput current will be reduced frm the set value by abut 0.7mA. n mst cases, due t the inductr values available, the actual ff-time will differ frm the cmputed value significantly. Thus, it is better t use the actual value f the ff-time cmputed in (-5 heren t cmpute the rest f the values. Nte: f the switching frequency is less than 50kHz, equatin (6 can be used t cmpute the utput inductance value, simplifying the prcedure greatly. 4
Step 5: Cmpute the input inductr Assuming a 5% peak-t-peak ripple (this lw input ripple will minimize the input filtering capacitance needed in the input current at minimum input vltage and the ff-time cmputed in (-5, the input inductr can be cmputed as: L V Tff 0.5 in, 7µ H (-9 The clsest standard value inductr is an 8µH inductr. The current rating f this inductr will be decided in the final stages after the input current limit has been set. The peak-t-peak ripple in the input current is: in V Tff L 0.A (-0 Step 6: Cmpute the value f the middle capacitr Assuming a 0% ripple acrss the capacitr at minimum input vltage ( v 0. ( V V + V 3.65V, capacitr C can be cmputed as: c in,min d C in, Tff v c 0.57µ F (- rms,c in, 0.7A ( D + D (- The vltage rating and type f this capacitr have t be chsen carefully. This capacitr carries bth the input current and the utput current. Thus, t prevent excessive lsses and verheating f the capacitr, it must have a very lw ES. Ceramic capacitrs are an ideal chice fr this applicatin due t their lw ES and high transient vltage limit. The imum steady state vltage acrss the capacitr is 44V (8V+6V, and the imum transient vltage acrss the capacitr V is 70V (8V+4V. Ceramic capacitrs can easily withstand up t c,.5 times their vltage rating fr the duratin f the lad dump vltage. Als, the actual capacitance value f these capacitrs reduces based n the bias vltage applied. Ceramic capacitr types X7 and X5 are mre stable and the capacitance drp is nt mre than 0% at full rated vltage. Thus, a 0.µF, 50V X7 ceramic chip capacitr can be chsen. 5
Step 7: Chse the Switching Transistr The peak vltage acrss the MOSFET Q is 70V. Assuming a 30% verhead n the vltage rating t accunt fr leakage inductance spikes, the MOSFET vltage needs t be at least: V FET.3 V 9V c, (-3 The rms current thrugh the FET will be imum at lw input vltage (higher current levels and imum duty cycle. The imum rms current thrugh the FET is: FET, ( + in,.77 A D (-4 A typical chice fr the MOSFET is t pick ne whse current rating is abut three times the imum rms current. Chse FDS369 frm Fairchild Semicnductrs (00V, 4.5A, 50mΩ N-channel MOSFET. Nte: The C iss f the chsen FET is abut 750pF. t is recmmended that the FET input capacitance nt exceed 000pF, as the large switching times will cause increased switching lsses. A FET with an input capacitance arund 500pF wuld be ideal. A higher input capacitance wuld be allwable if the switching frequency can be reduced apprpriately. Step 8: Chse the switching dide The imum vltage rating f the dide D is the same as the FET vltage rating. The average current thrugh the dide equal t the utput current. 350mA (-5 dide Althugh the average current f the dide is nly 360mA, the actual switching current thrugh the dide ges as high as.95a ( in, +. A 500mA dide will be able t carry the.79a current safely, but the vltage drp at such high current levels wuld be extremely large increasing the pwer dissipatin. Thus, we need t chse a dide whse current rating is at least A. Chse B00-3 by Dides, nc. (00V, A schttky dide. Step 9: Chse the nput Dide The input dide serves tw purpses:. t prtects the circuit frm a reverse plarity cnnectin at the input.. t helps in PWM dimming f the circuit by preventing C frm discharging when the HV9930 is turned ff. The current rating f the device shuld be at least equal t in,. The vltage rating f the device shuld be mre than the reverse input vltage rating. Chse B0-3 by Dides, nc. (0V, A schttky dide. 6
Step 0: Designing the input capacitance Sme capacitance is required n the input side t filter the input current. This capacitance is mainly respnsible fr reducing the nd harmnic f the input current ripple (which in this case falls in the AM band. Accrding t the SAE J3 specificatins, the peak limit fr narrwband emissins in this range is 50dBµV t meet Class 3 at an input vltage f 3 +/- 0.5V. Assuming a saw tth wavefrm fr the input current as a cnservative apprximatin, the rms value f the nd harmnic cmpnent f the input current ( in, can be cmputed as: in π in, 0.04 A (-6 The switching frequency f the cnverter at 3V input can be cmputed as: D f nm s,nm η + nm 0.8 + 8 0.73 D T nm ff 44kHz ( V V in,nm V ( 3.5 0.5 d (-7 (-8 C in 4 π f 4.6µ F s,nm in, 50 6 0 0 0 (-9 Chse a parallel cmbinatin f 4.7µF, 5V, X7 ceramic capacitr. Step : Designing the Output Capacitance The value f the utput capacitance required t reduce the LED current ripple frm 5mA t LED 70mA (0% peak t peak ripple can be apprximately cmputed by using nly the first harmnic in the inductr current. A 70mA peak-t-peak ripple in the LED results in a 39mV ( v LED LED peak t peak ripple vltage. Then: v π 8 i L + LED ( π f C s,min LED (-0 7
The utput capacitance required can then be cmputed frm (-0 as: C 8 LED i L π v π f 0.083µ F s,min LED (- Use a 0.0µF, 35V ceramic capacitr. Step : Cmputing the Theretical Switching Frequency variatin The imum and minimum frequencies (using steady state vltage cnditins can be cmputed as: ( V V in,min + η d min V (- fs,min Tff 9kHz f s, + η 506kHz T ( V V in, ff d V (-3 The theretical frequency variatin fr this design is 398kHz ± 7%. Design f the Damping Circuit The values fr the damping netwrk can be cmputed using (0 and (. Cd D 9 D µ F 3 L V (-4 d 3 D ( D 7.6Ω L Cd V (-5 The pwer dissipated in d can be cmputed as: P d v c d (-6 3.65 0.55W 7.6 8
The rms current thrugh the damping capacitr will be: i v c 3 Cd d 0.47 A (-7 Chse a 0µF, 50V electrlytic capacitr, which can allw at least 50mA rms current. An example wuld be EEVFKH00P frm Panasnic (0µF, 50V, Size D. This capacitr has abut a Ω ES, s d can be reduced t abut 6.Ω. Design using the HV9930 Step : nternal Vltage egulatr f the HV9930 The HV9930 includes a built-in 8-00V linear regulatr. This regulatr supplies the pwer t the C. This regulatr can be cnnected at wither ne f tw ndes n the circuit based n the requirement:. n the nrmal case, when the input vltage is always greater than 8V, the V N pin f the C can be cnnected t the input vltage directly r with a series dide (Fig. -a in case reverse plarity prtectin is required.. n cnditins where the cnverter needs t perate at vltages lwer than 8V, nce the cnverter is running (as in the case f cld-crank peratin, the VN pin f the HV9930 can be cnnected as shwn in Fig. -b. n this case, the drain f the FET is at V in+v, and hence even if the input vltage drps belw 8V, the C will still be functining. Hwever, in this case, mre hld-up capacitance will be required at the V DD pin t supply the pwer t the C when the FET is ON. 3. n bth cases, a ceramic capacitance f µf f greater is recmmended at the V DD pin. D L D L VN VN D4 Q D4 Q HV9930 VN VDD C HV9930 VN VDD C GATE PWMD GATE PWMD CS CS CS CS GND EF GND EF (a (b Fig. -. Cnnecting VN pin f the HV9930 9
Step : nternal Vltage eference The HV9930 includes an internal.5v (+/-3% reference. This reference can be used t set the current threshlds fr the input and utput hysteretic cmparatrs. t is recmmended that this pin be bypassed with at least a 0.µF ceramic capacitr. Step 3: Prgramming the Hysteretic Cntrllers and Over Vltage Prtectin The input and utput current levels fr the hysteretic cntrllers are set by means f three resistrs fr each current ne current sense resistr and tw divider resistrs. The equatins gverning the resistrs are the same fr bth the input and utput sides and are given as s ref cs i 0.05 + 0. (-8 i. 0. s. 0.05 ref (-9 These equatins assume that the.5v reference prvided by the HV9930 is used t set the current. n cases where Linear Dimming f the LEDs is required, it is recmmended that the input current threshlds be based n the.5v reference and the utput current threshlds are mdified using the variable input vltage available. n such a case, assuming the imum external vltage V LD as the reference, the abve tw equatins can be mdified as: s ref i 0.05 + 0. i ( V 0.05 0. LD (-30 cs s ( VLD 0.05 0.05 ref (-3 n this design example, it is assumed that Linear Dimming is nt required and the.5v reference is used fr bth the input and utput prgramming. Nte: The HV9930 cannt perate the bst-buck cnverter in the discntinuus cnductin mde. Thus, if the external vltage is reduced belw: ref + s VLD 0., s the LEDs will extinguish. The prgramming f the utput side is als linked t the ver vltage prtectin. The bst-buck cnverter is nt inherently prgrammed against pen LED cnditins. Thus, external prtectin is required. This is dne by adding zener dide D3 and splitting the resistr s int tw parts sa and sb. When there is an pen LED cnditin, the inductr current will flw thrugh dide D3. This will then clamp the utput vltage at the dide vltage. Hwever, since the dide cannt take the LED current, the current level has t be reduced t mre manageable levels. This is dne by the cmbinatin f cs and sa. n nrmal peratin, the inductr current will flw nly thrugh cs. During pen LED cnditins, the current will flw thugh bth cs and sa. Thus, the effective current sense resistr seen by the C is 0
cs + sa. This, in effect, will reduce the current level and thus prevent the high LED currents frm flwing int the zener dide. Design f the utput side resistrs Fr the utput current, 0.36A (t cmpensate fr the 0mA drp due t the delay times and 87.5mA. Nte that we are using the values assumed and nt the actual values cmputed in (-6 fr the ripple current. Using these values in the abve equatins, sa + ref sb 0.534 (-3 P cs cs.64ω 0.35.64 0.W (-33 Befre we cmplete the design f the utput side, we als have t design the ver vltage prtectin. Fr this applicatin, chse a 33V zener dide. This is the vltage at which the utput will clamp in case f an pen LED cnditin. Fr a 350mW dide, the imum current rating at 33V wrks ut t abut 0mA. Using a 5mA current level during pen LED cnditins, and assuming the same s ref rati, s a cs + 0Ω. (-34 Chse the fllwing values fr the resistrs: cs ref sa sb.65ω, / 0kΩ, / 00Ω, / 5.3kΩ, / 4W, % 8W, % 8W, % 8W, % Design f the input side resistrs Fr the input side, we first have t determine the input current level fr limiting. This current level is dictated by the fact the input cmparatr must nt interfere with the peratin f the circuit even at minimum input vltage. The peak f the input current at minimum input vltage will be: in,pk in, +.706 A in (-35 Assuming a 30% peak-t-peak ripple when the cnverter is in input current limit mde, the minimum value f the input current will be: lim, min 0.85 in,lim (-36 We need t ensure that i.e., lim, min > in, pk fr prper peratin f the circuit. Assuming a 5% safely factr,.05 lim, min in,pk, (-37
we can cmpute the input current limit t be in, lim.a. Using equatins (-8 and (-9 and a 30% peak t peak ripple, we can cmpute s ref 0.44 (-38 P cs cs 0.8Ω in,lim cs W (-39 This pwer dissipatin is a imum value, which ccurs nly at minimum input vltage. At a nminal input vltage f 3.5V, we can cmpute the input current using (- and using the nminal values fr the efficiency and the input vltage. in, nm 8 0.35 0.8 0.94 A ( 3.5 0.5 (-40 P cs 0.94 0.8 0.W (-4 Thus, at nminal input vltage, the pwer dissipatin reduces by abut 5 times t a reasnable 0.W. Chse the fllwing values fr the resistrs: cs ref s parallel cmbinatin f 0kΩ, / 4.4kΩ, / 8W, % 8W, % three 0.68Ω, / W, 5% resistrs Step 4: nput nductr Current ating The imum current thrugh the input inductr is lim,.5 in, lim.4a. Thus, the saturatin current rating f the inductr has t be at least.5a. f the cnverter is ging t be in input current limit fr extended perids f time, the rms current rating needs t be A, else a.5a rms current rating will suffice. Meeting Cnducted and adiated EM Due t the nature f the bst-buck cnverter, it is easy t meet cnducted and radiated EM specificatins. A few precautins need t be taken during design and PCB layut t be able t meet the EM standards.. n sme cases, when the input current ripple is t large r the switching frequency f the cnverter is in the EM band, it might nt be pssible t meet the cnducted EM standards using nly capacitrs at the input. n such cases, an input P filter might be required t filter the lw frequency harmnics.. Shielded inductrs r tridal inductrs shuld always be preferred ver unshielded inductrs. These inductrs will minimize radiated magnetic fields.