Dual/Quad Low Power, High Speed JFET Operational Amplifiers OP22/OP42 FEATURES High slew rate: 9 V/µs Wide bandwidth: 4 MHz Low supply current: 2 µa/amplifier max Low offset voltage: 3 mv max Low bias current: pa max Fast settling time Common-mode range includes V+ Unity-gain stable APPLICATIONS Active filters Fast amplifiers Integrators Supply current monitoring OUT A IN A +IN A PIN CONNECTIONS 2 3 OP22 V 4 OP-42 7 6 V+ OUT B IN B +IN B Figure. -Lead Narrow-Body SOIC (S-Suffix) [R-] OUT A IN A 2 +IN A 3 V 4 OP22 TOP VIEW (Not to Scale) 7 6 V+ OUT B IN B +IN B Figure 2. -Lead MSOP [RM-] 3-3-2 GENERAL DESCRIPTION The OP22/OP42 dual and quad operational amplifiers feature excellent speed at exceptionally low supply currents. The slew rate is typically 9 V/µs with a supply current under 2 µa per amplifier. These unity-gain stable amplifiers have a typical gain bandwidth of 4 MHz. The JFET input stage of the OP22/OP42 ensures bias current is typically a few picoamps and below pa over the full temperature range. Offset voltage is under 3 mv for the dual and under 4 mv for the quad. With a wide output swing, within. V of each supply, low power consumption, and high slew rate, the OP22/OP42 are ideal for battery-powered systems or power restricted applications. An input common-mode range that includes the positive supply makes the OP22/OP42 an excellent choice for high-side signal conditioning. The OP22/OP42 are specified over the extended industrial temperature range. The OP22 is available in the standard -lead narrow SOIC and MSOP packages. The OP42 is available in PDIP and narrow SOIC packages. OUT A IN A +IN A 2 3 + + V+ +IN B 4 OP42 IN B OUT B 6 7 + + 4 OUT D 3 IN D 2 +IN D V +IN C 9 IN C OUT C Figure 3. 4-Lead PDIP (P-Suffix) [N-4] OUT A IN A 2 4 3 OUT D IN D +IN A 3 2 +IN D OP42 V+ +IN B IN B OUT B 4 6 7 9 V +IN C IN C OUT C Figure 4. 4-Lead Narrow-Body SOIC (S-Suffix) [R-4] 3-4 3-3 Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 262-96, U.S.A. Tel: 7.329.47 www.analog.com Fax: 7.326.73 24 Analog Devices, Inc. All rights reserved.
TABLE OF CONTENTS Specifications... 3 Electrical Characteristics... 3 Absolute Maximum Ratings... 4 ESD Caution... 4 Typical Performance Characteristics... Applications Information... 2 High-Side Signal Conditioning... 2 Phase Inversion... 2 Active Filters... 2 Programmable State-Variable Filter... 3 Outline Dimensions... 4 Ordering Guide... 6 REVISION HISTORY /4 Data Sheet Changed from Rev. E to Rev. F Deleted -Lead PDIP...Universal Added -Lead MSOP...Universal Changes to Format and Layout...Universal Changes to Features... Changes to Pin Configurations... Changes to General Description... Changes to Specifications... 3 Changes to Absolute Maximum Ratings... 4 Changes to Table 3... 4 Added Figure through Figure 2; Renumbered Successive Figures... Updated Figure 2 and Figure 22... 7 Updated Figure 23 and Figure 27... Updated Figure 29... 9 Updated Figure 3 and Figure 36... Updated Figure 43... Changes to Applications Information... 2 Changes to Figure 44... 2 Deleted OP22/OP42 Spice Macro Model Section... 9 Deleted Figure 4... 9 Deleted OP22 Spice Marco Model... Updated Outline Dimensions... 4 Changes to Ordering Guide... 4 /2 Data Sheet Changed from Rev. D to Rev. E Edits to -Lead Epoxy DIP (P-Suffix) Pin... Edits to Ordering Guide...3 Edits to Outline Dimensions... 9/2 Data Sheet Changed from Rev. C to Rev. D Edits to 4-Lead SOIC (S-Suffix) Pin... Replaced -Lead SOIC (S-Suffix)... 4/2 Data Sheet changed from Rev. B to Rev. C Wafer Test Limits Deleted...2 Edits to Absolute Maximum Ratings...3 Dice Characteristics Deleted...3 Edits to Ordering Guide...3 Edits to Figure...7 Edits to Figure 3... 2-Position Chip Carrier (RC Suffix) Deleted... Rev. F Page 2 of 6
SPECIFICATIONS ELECTRICAL CHARACTERISTICS At VS = ±. V, TA = 2 C, unless otherwise noted; applies to both A and G grade. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS OP22.2 3 mv OP22, 4 C TA + C 4. mv VOS OP42.2 4 mv OP42, 4 C TA + C 6 mv Input Bias Current IB VCM = V 3 pa VCM = V pa Input Offset Current IOS VCM = V pa VCM = V 2 pa Input Voltage Range + V Common-Mode Rejection Ratio CMRR V VCM + V, 4 C TA + C 7 9 db Large Signal Voltage Gain AVO RL = kω 2 V/mV RL = kω, 4 C TA + C V/mV Offset Voltage Drift VOS/ T µv/ C Bias Current Drift IB/ T pa/ C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = kω +3. +3.9 V Output Voltage Low VOL RL = kω 3.9 3. V Short-Circuit Limit ISC Source 3 ma Sink 2 ma Open-Loop Output Impedance ZOUT f = MHz 2 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±4. V to ± V, 4 C TA + C 2 36 µv/v Supply Current/Amplifier ISY VO = V, 4 C TA C 2 2 µa Supply Voltage Range VS ±4. ± V DYNAMIC PERFORMANCE Slew Rate SR RL = kω 7 9 V/µs Full-Power Bandwidth BWP % distortion 2 khz Settling Time ts To.%.6 µs Gain Bandwidth Product GBP 4 MHz Phase Margin ØO Degrees NOISE PERFORMANCE Voltage Noise en p-p. Hz to Hz.3 µv p-p Voltage Noise Density en f = khz 36 nv/ Hz Current Noise Density in. pa/ Hz The input bias and offset currents are characterized at TA = TJ = C. Bias and offset currents are guaranteed but not tested at 4 C. Rev. F Page 3 of 6
ABSOLUTE MAXIMUM RATINGS Table 2. Parameters Ratings Supply Voltage ± V Input Voltage ± V Differential Input Voltage 36 V Output Short-Circuit Duration Indefinite Storage Temperature Range P-Suffix (N), S-Suffix (R), RM Packages 6 C to + C Operating Temperature Range OP22G, OP22A, OP42G 4 C to + C Junction Temperature Range P-Suffix (N), S-Suffix (R), RM Packages 6 C to + C Lead Temperature Range (Soldering 6 sec) 3 C For supply voltages less than ± V, the absolute maximum input voltage is equal to the supply voltage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Package Type θja θjc Unit -Lead MSOP [RM] 26 44 C/W -Lead SOIC (S-Suffix) [R] 7 6 C/W 4-Lead PDIP (P-Suffix) [N] 3 39 C/W 4-Lead SOIC (S-Suffix) [R] 4 36 C/W θja is specified for the worst-case conditions; i.e., θja is specified for device in socket for CERDIP, PDIP; θja is specified for device soldered in circuit board for SOIC or MSOP package. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F Page 4 of 6
TYPICAL PERFORMANCE CHARACTERISTICS OPEN-LOOP GAIN (db) 6 4 2 2 4 k 3 4 9 k k M M 9 4 PHASE (Degree) 3- CLOSED-LOOP GAIN (db) 7 6 4 3 2 2 3 k A VCL = A VCL = A VCL = k k M M 3- Figure. OP22 Open-Loop Gain and Phase vs. Frequency Figure. OP22 Closed-Loop Gain vs. Frequency 4 4 3 R L = kω 3 2 SR R L = kω C L = pf OPEN-LOOP GAIN (V/mV) 3 2 2 7 2 2 7 2 3-6 SLEW RATE (V/µs) 2 7 +SR 2 2 7 2 3-9 Figure 6. OP22 Open-Loop Gain vs. Temperature Figure 9. OP22 Slew Rate vs. Temperature OVERSHOOT (%) 7 6 4 3 2 R L = 2kΩ V IN = mv p-p A VCL = +OS OS INPUT BIAS CURRENT (pa) V CM = V 2 3 4 LOAD CAPACITANCE (pf) Figure 7. OP22 Small Signal Overshoot vs. Load Capacitance 3-7. 7 2 2 7 2 Figure. OP22 Input Bias Current vs. Temperature 3- Rev. F Page of 6
VOLTAGE NOISE DENSITY (nv/ Hz) k k 3- OUTPUT VOLTAGE SWING (V) 2 2 R L = kω ± V OH V OL ± SUPPLY VOLTAGE (V) ± 3-4 ±2 Figure. OP22 Voltage Noise Density vs. Frequency Figure 4. OP22 Output Voltage Swing vs. Supply Voltage INPUT BIAS CURRENT (pa). COMMON-MODE VOLTAGE (V) Figure 2. OP22 Input Bias Current vs. Common-Mode Voltage 3-2 OUTPUT IMPEDANCE (Ω) A VCL = A VCL = A VCL =. k k k M Figure. OP22 Closed-Loop Output Impedance vs. Frequency 3-4 4 47 47 SUPPLY CURRENT (µa) 47 46 46 SUPPLY CURRENT (µa) 47 46 46 4 4 4 ± ± SUPPLY VOLTAGE (V) ± 3-3 ±2 4 2 2 7 3-6 2 Figure 3. OP22 Supply Current vs. Supply Voltage Figure 6. OP22 Supply Current vs. Temperature Rev. F Page 6 of 6
ABSOLUTE OUTPUT VOLTAGE (V) 6 4 2 6 4 2 V OL V OH k LOAD RESISTANCE (Ω) 3-7 k MAXIMUM OUTPUT SWING (V p-p) 3 2 2 R L = kω A VCL = k k k M 3-2 Figure 7. OP22 Absolute Output Voltage vs. Load Resistance Figure 2. OP22 Maximum Output Swing vs. Frequency 4 2 4 2 +PSRR PSRR (db) 6 4 2 PSRR CMRR (db) 6 4 2 2 2 4 6 k k k M 3-4 6 k k k M 3-2 Figure. OP22 PSRR vs. Frequency Figure 2. OP22 CMRR vs. Frequency SHORT-CIRCUIT CURRENT (ma) 4 2 6 4 2 SINK SOURCE 2 2 7 3-9 2 UNITS 2 6 2 4 2 2 4 V OS (µv) 3 OP22 (6 OP AMPS) 4 2 2 3-22 Figure 9. OP22 Short-Circuit Current vs. Temperature Figure 22. OP22 VOS Distribution SOIC Package Rev. F Page 7 of 6
4 36 32 3 OP22 (6 OP AMPS) 7 6 R L = 2kΩ V IN = mv p-p A VCL = NEGATIVE EDGE UNITS 2 24 2 6 2 OVERSHOOT (%) 4 3 2 A VCL = POSITIVE EDGE 4 4 2 6 2 TCV OS (µv/ C) 24 2 32 36 3-23 2 3 4 LOAD CAPACITANCE (pf) 3-26 Figure 23. OP22 TCVOS Distribution SOIC Package Figure 26. OP42 Small Signal Overshoot vs. Load Capacitance OPEN-LOOP GAIN (db) 6 4 2 4 9 3 PHASE (Degrees) CLOSED-LOOP GAIN (db) 6 4 3 2 A VCL = A VCL = A VCL = k k k M M M Figure 24. OP42 Open-Loop Gain, Phase vs. Frequency 3-24 2 k k k M M M Figure 27. OP42 Closed-Loop Gain vs. Frequency 3-27 3 3 R L = kω 2 SR OPEN-LOOP GAIN (V/mV) 2 2 SLEW RATE (V/µs) 2 +SR R L = kω C L = pf 7 2 2 7 3-2 2 7 2 2 7 2 3-2 Figure 2. OP42 Open-Loop Gain (V/mV) Figure 2. OP42 Slew Rate vs. Temperature Rev. F Page of 6
V CM = V INPUT BIAS CURRENT (pa). INPUT BIAS CURRENT (pa). 2 2 7 3-29 2. COMMON-MODE VOLTAGE (V) 3-32 Figure 29. OP42 Input Bias Current vs. Temperature Figure 32. OP42 Input Bias Current vs. Common-Mode Voltage 6 R L = kω.. PHASE MARGIN (Degrees) 4 GBW 4. 4. 3. GAIN BANDWIDTH PRODUCT (MHz) RELATIVE SUPPLY CURRENT (ISY)....9.9 4 3. 7 2 2 7 2 Figure 3. OP42 Phase Margin and Gain Bandwidth Product vs. Temperature 3-3. ± ± ± ± 2 SUPPLY VOLTAGE (V) Figure 33. OP42 Relative Supply Current vs. Supply Voltage 3-33 VOLTAGE NOISE DENSITY (nv/ Hz) 7 6 4 3 2 OUTPUT VOLTAGE SWING (V) 2 R L = kω k k Figure 3. OP42 Voltage Noise Density vs. Frequency 3-3 2 ± ± ± ±2 SUPPLY VOLTAGE (V) Figure 34. OP42 Output Voltage Swing vs. Supply Voltage 3-34 Rev. F Page 9 of 6
6 +PSRR V = mv IMPEDANCE (Ω) 4 3 2 PSRR (db) 6 4 2 PSRR A VCL = A VCL = A VCL = k k k M Figure 3. OP42 Closed-Loop Output Impedance vs. Frequency 3-3 2 k k k M Figure 3. OP42 Power Supply Rejection Ratio (PSRR) vs. Frequency 3-3 RELATIVE SUPPLY CURRENT (ISY).2.....9.9.. 7 2 2 7 2 Figure 36. OP42 Relative Supply Current vs. Temperature 3-36 SHORT-CIRCUIT CURRENT (ma) 2 SINK SOURCE 7 2 2 7 2 Figure 39. OP42 Short-Circuit Current vs. Temperature 3-39 ABSOLUTE OUTPUT VOLTAGE (V) 6 4 2 6 4 2 POSITIVE SWING k LOAD RESISTANCE (Ω) NEGATIVE SWING Figure 37. OP42 Maximum Output Voltage vs. Load Resistance 3-37 k MAXIMUM OUTPUT SWING (V) 3 2 2 K K K A VCL = R L = kω Figure 4. OP42 Maximum Output Swing vs. Frequency M 3-4 Rev. F Page of 6
32 2 24 CMRR (db) 6 4 2 UNITS 2 6 2 V CM = mv 2 k k k M 3-4 4 4 2 6 2 24 2 32 3-43 TCV OS (µv/ C) Figure 4. OP42 Common-Mode Rejection Ratio (CMRR) vs. Frequency Figure 43. OP42 TCVOS Distribution P Package 7 6 3 OP42 (2 OP AMPS) UNITS 4 3 2 2 6 2 4 4 2 6 V OS (µv) 3-4 2 Figure 42. OP42 VOS Distribution P Package Rev. F Page of 6
APPLICATIONS INFORMATION The OP22 and OP42 are dual and quad JFET op amps that are optimized for high speed at low power. This combination makes these amplifiers excellent choices for battery-powered or low power applications that require above average performance. Applications benefiting from this performance combination include telecommunications, geophysical exploration, portable medical equipment, and navigational instrumentation. HIGH-SIDE SIGNAL CONDITIONING There are many applications that require the sensing of signals near the positive rail. OP22s and OP42s were tested and are guaranteed over a common-mode range ( V VCM + V) that includes the positive supply. One application where this is commonly used is in the sensing of power supply currents. This enables it to be used in current sensing applications, such as the partial circuit shown in Figure 44. In this circuit, the voltage drop across a low value resistor, such as the. Ω shown here, is amplified and compared to 7. V. The output can then be used for current limiting. PHASE INVERSION Most JFET-input amplifiers invert the phase of the input signal if either input exceeds the input common-mode range. For the OP22/OP42, negative signals in excess of approximately 4 V cause phase inversion. The cause of this effect is saturation of the input stage leading to the forward-biasing of a drain-gate diode. A simple fix for this in noninverting applications is to place a resistor in series with the noninverting input. This limits the amount of current through the forward-biased diode and prevents the shutting down of the output stage. For the OP22/OP42, a value of 2 kω has been found to work; however, this adds a significant amount of noise. V OUT V.Ω kω kω kω R L /2 OP22 V IN 3-47 kω Figure 44. High-Side Signal Conditioning 3-46 ACTIVE FILTERS Figure 4. OP22 Phase Reversal The wide bandwidth and high slew rates of the OP22/OP42 make either an excellent choice for many filter applications. There are many active filter configurations, but the four most popular configurations are Butterworth, Elliptical, Bessel, and Chebyshev. Each type has a response that is optimized for a given characteristic as shown in Table 4. Table 4. Type Selectivity Overshoot Phase Amplitude (Pass Band) Amplitude (Stop Band) Butterworth Moderate Good Maximum Flat Chebyshev Good Moderate Nonlinear Equal Ripple Elliptical Best Poor Equal Ripple Equal Ripple Bessel (Thompson) Poor Best Linear Rev. F Page 2 of 6
PROGRAMMABLE STATE-VARIABLE FILTER The circuit shown in Figure 46 can be used to accurately program the Q, the cutoff frequency fc, and gain of a 2-pole state variable filter. OP42s have been used in this design because of their high bandwidths, low power, and low noise. This circuit takes only three packages to build because of the quad configuration of the op amps and DACs. The DACs shown are used in the voltage mode; therefore, many values are dependent on the accuracy of the DAC only and not on the absolute values of the DAC s resistive ladders. This makes this circuit unusually accurate for a programmable filter. Adjusting DAC changes the signal amplitude across R; therefore, the DAC attenuation times R determines the amount of signal current that charges the integrating capacitor, C. This cutoff frequency can now be expressed as D fc = 2πRC 26 where D is the digital code for the DAC. The gain of this circuit is set by adjusting D3. The gain equation is Gain = R4 R D3 26 DAC 2 is used to set the Q of the circuit. Adjusting this DAC controls the amount of feedback from the band-pass node to the input summing node. Note that the digital value of the DAC is in the numerator; therefore, zero code is not a valid operating point. R2 26 Q = R3 D2 R7 2kΩ R4 2kΩ V IN /4 DAC4 /4 OP42 R 2kΩ /4 OP42 HIGH PASS C pf R /4 /4 2kΩ DAC4 OP42 /4 OP42 C pf R /4 /4 2kΩ DAC4 OP42 /4 OP42 LOW PASS R6 2kΩ BAND PASS R3 2kΩ /4 OP42 R2 2kΩ /4 OP42 /4 DAC4 3-4 Figure 46. Rev. F Page 3 of 6
OUTLINE DIMENSIONS. (.96) 4. (.9) 4. (.74) 3. (.497) 4 6.2 (.244). (.224).2 (.9). (.4) COPLANARITY..27 (.) BSC SEATING PLANE.7 (.6).3 (.32). (.2).3 (.22).2 (.9).7 (.67). (.96).2 (.99) 4.27 (.).4 (.7) COMPLIANT TO JEDEC STANDARDS MS-2AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 47. -Lead Standard Small Outline Package [SOIC] Narrow-Body S-Suffix (R-) Dimensions shown in millimeters and (inches) 3. BSC 3. BSC 4 4.9 BSC PIN.6 BSC...3.22 COPLANARITY.. MAX SEATING PLANE.23. COMPLIANT TO JEDEC STANDARDS MO-7AA..6.4 Figure 4. -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters Rev. F Page 4 of 6
.7 (.344). (.3366) 4. (.7) 3. (.496) 4 7 6.2 (.244). (.223).2 (.9). (.39) COPLANARITY..27 (.) BSC. (.2).3 (.22).7 (.69).3 (.3) SEATING PLANE.2 (.9).7 (.67). (.97) 4.2 (.9).27 (.).4 (.7) COMPLIANT TO JEDEC STANDARDS MS-2AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 49. 4-Lead Standard Small Outline Package [SOIC] Narrow-Body S-Suffix (R-4) Dimensions shown in millimeters and (inches) 4.6 (7.4).66 (6.9).64 (6.3) 7.29 (7.49).2 (7.24).27 (6.99). (4.7) MAX. (2.4) BSC. (.3) MIN. (3.).3 (3.3). (2.79).22 (.6). (.46).4 (.36).6 (.2). (.27).4 (.4) SEATING PLANE.32 (.26).3 (7.7).3 (7.62). (.3). (.2). (.2). (3.).3 (3.43).2 (3.) COMPLIANT TO JEDEC STANDARDS MO-9-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure. 4-Lead Plastic Dual-in-Line Package [PDIP] P-Suffix (N-4) Dimension shown in inches and (millimeters) Rev. F Page of 6
ORDERING GUIDE Model Temperature Range Package Description Package Option Branding OP22ARMZ-R2 4 C to + C -Lead MSOP RM- AB OP22ARMZ-REEL 4 C to + C -Lead MSOP RM- AB OP22GS 4 C to + C -Lead SOIC S-Suffix (R-) OP22GS-REEL 4 C to + C -Lead SOIC S-Suffix (R-) OP22GS-REEL7 4 C to + C -Lead SOIC S-Suffix (R-) OP22GSZ 4 C to + C -Lead SOIC S-Suffix (R-) OP22GSZ-REEL 4 C to + C -Lead SOIC S-Suffix (R-) OP22GSZ-REEL7 4 C to + C -Lead SOIC S-Suffix (R-) OP42GP 4 C to + C 4-Lead PDIP P-Suffix (N-4) OP42GS 4 C to + C 4-Lead SOIC S-Suffix (R-4) OP42GS-REEL 4 C to + C 4-Lead SOIC S-Suffix (R-4) OP42GS-REEL7 4 C to + C 4-Lead SOIC S-Suffix (R-4) OP42GSZ 4 C to + C 4-Lead SOIC S-Suffix (R-4) OP42GSZ-REEL 4 C to + C 4-Lead SOIC S-Suffix (R-4) OP42GSZ-REEL7 4 C to + C 4-Lead SOIC S-Suffix (R-4) Z = Pb-free part. 24 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C3 /4(F) Rev. F Page 6 of 6