Metal-Semiconductor and Semiconductor Heterojunctions The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of two major types of transistors. The MOSFET is used in digital circuit, because of its small size, millions of devices can be fabricated in a single integrated circuit. Semiconductor Physics and Devices Chapter 10. Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor Two complementary configurations of MOS transistors can be fabricated. The n-channel MOSFET & the p-channel MOSFET Seong Jun Kang Department of Advanced Materials Engineering for Information and Electronics Laboratory for Advanced Nano Technologies The two-terminal MOS structure The MOS capacitor is shown. The parameter t ox is the thickness of the oxide and is the permittivity of the oxide. The metal may be aluminum or some other type of metal, but in many case, it is actually a high conductivity polycrystalline silicon that has been deposited on the oxide. The MOS structure can be easily explained with the simple parallel-plate capacitor. The figure shows a parallel-plate capacitor with the top plate at a negative voltage with respect to the bottom plate. An insulator separates the two plates. The capacitance per unit area is, The magnitude of the charge per unit area on either plate is, The magnitude of the electric field is, The basic MOS capacitor structure The figure shows a MOS capacitor with a p-type semiconductor substrate. An electric field induced with the direction as shown. The majority carrier holes (p-type semiconductor) would experience a force toward the oxidesemiconductor interface. An accumulation layer of holes at the oxide-semiconductor junction corresponds to the positive charge on the bottom plate of the MOS capacitor. The figure shows the same MOS capacitor in which the polarity of the applied voltage is reversed. A positive charge exists on the top metal plate, and the induced electric field is in the opposite direction as shown. Majority carrier holes will experience a force away from the oxide-semiconductor interface. A negative charge region is created at the interface. The negative charge in the induced depletion region correspond to the negative charge on the bottom plate of the MOS capacitor.
The energy-band diagrams of the MOS capacitor with a p-type substrate for various gate biases are shown. Figure (a) shows ideal case when zero bias is applied. (flat band) Figure (b) shows the case with a negative bias to the gate. Figure (c) shows the case with a positive bias to the gate. Figure (b) shows the case with a negative bias to the gate. The valence band edge is closer to the Fermi level at the oxide-semiconductor interface than in the bulk material. There is an accumulation of holes at the valence band edge. The semiconductor surface (interface with oxide) appears to be more p-type. The Fermi level is a constant in the semiconductor since the MOS system is in thermal equilibrium, and there is no current through the oxide. Figure (c) shows the case with a positive bias to the gate. The conduction and valence band edges bend as shown in the figure. Similar to the pn-junction, a space charge region induced (depletion of holes) as shown. The induced space charge width is x d. (electron accumulates at the interface) Consider a larger positive voltage is applied to the top metal gate of the MOS capacitor. A large negative charge at the interface implies a larger induced space charge region and more band bending. The intrinsic Fermi level (E Fi ) at the surface is now below the Fermi level (E F ). The conduction band at the surface is now close to the Fermi level, while the valence band at the bulk semiconductor is closed to the Fermi level. The surface in the semiconductor adjacent to the interface is n-type. By applying sufficient large positive gate voltage, an inversion layer of electrons at the interface can create. Figures shows the MOS capacitor structure with an n-type semiconductor substrate. The MOS capacitor with a p-type substrate and large positive gate voltage. A positive space charge region is induced in the n-type semiconductor in this case. The MOS capacitor with an n-type substrate and large negative gate voltage.
Depletion Layer Thickness Figure shows the space charge region in a p-type semiconductor substrate. The potential is the difference (in V) between E Fi and E F. N a is the acceptor doping concentration and n i is the intrinsic carrier concentration. The potential is the surface potential; the difference (in V) betweene Fi measured in the bulk semiconductor and E Fi measured at the surface. The surface potential is the potential difference across the space charge layer. Depletion Layer Thickness In the case of 2, the Fermi level at the surface is far above the intrinsic Fermi level. The electron concentration at the surface is same as the hole concentration in the bulk. This condition is the threshold inversion point, and the applied gate voltage creating this condition is the threshold voltage. The maximum space charge width at the inversion transition point is below. For p-type substrate For n-type substrate The space charge width canbewrittenina similar form of a one-sided pn junction. The potential charge width. For p-type substrate and the maximum space For n-type substrate Depletion Layer Thickness The plot of x dt at T = 300 K as a function of doping concentration in silicon. Surface Charge Density The electron concentration in the conduction band is, (from chapter 4) For p-type substrate For a p-type semiconductor substrate, the electron inversion charge density is, For n-type substrate is the surface potential greater than 2. The electron inversion charge density is, Surface charge density at the threshold inversion point Work Function Difference Left figure shows the energy level in the metal, silicon dioxide (SiO 2 ), and silicon relative to the vacuum level prior to contact. The metal work function is and the electron affinity is. Theparameter is the oxide electron affinity (0.9 V for SiO 2 ). Work Function Difference After contact with zero gate voltage, the Fermi level is a constant through the entire system at thermal equilibrium. : modified metal work function. the potential required to inject an electron from the metal into the conduction band of the oxide. : modified electron affinity. V ox0 : the potential drop across the oxide for zero applied gate voltage. : is the surface potential.
Work Function Difference Sum the energies from the Fermi level on the metal to the Fermi level on the semiconductor. Work Function Difference Degenerately doped polysilicon deposited on the oxide can be used as the metal gate. n + polysilicon gate and p-type substrate p + polysilicon gate and p-type substrate We can define a potential as the metalsemiconductor work function difference. Work Function Difference MOS capacitor with an n-type semiconductor substrate Flat-Band Voltage The flat-band voltage is the applied gate voltage such that there is no band bending in the semiconductor and zero net space charge in this region. Q ss : Trapped charge per unit area at the oxide The metal-semiconductor work function difference Q m : Charge density on the metal The flat-band voltage for the MOS device. Threshold Voltage The threshold voltage is defined as the applied gate voltage required to achieve the threshold inversion point. 2 : Threshold inversion condition for p-type semiconductor 2 : Threshold inversion condition for n- type semiconductor Capacitance-Voltage Characteristics Three operating conditions of interest in the MOS capacitor: Accumulation, Depletion, Inversion Accumulation mode The energy band diagram of a MOS capacitor with a p-type substrate for the case when a negative voltage is applied to the gate. Accumulation of holes in the semiconductor/oxide interface induced. Differential charge distribution at accumulation for a differential change in gate voltage. Capacitance of the MOS capacitor at the accumulation mode The maximum space charge density per unit area of the depletion region The threshold voltage for the MOS device.
Capacitance-Voltage Characteristics Depletion mode The energy band diagram of a MOS capacitor when a small positive voltage is applied to the gate. Capacitance-Voltage Characteristics Inversion mode The energy band diagram of a MOS capacitor when a high positive voltage is applied to the gate. A space charge region in the semiconductor induced. The oxide capacitance and the capacitance of the depletion region are in series. Capacitance of the MOS capacitor at the inversion mode Capacitance of the MOS capacitor at the depletion mode The Basic MOSFET Operation The Basic MOSFET Operation MOSFET structure (n channel) Upper figure shows an n-channel enhancement mode MOSFET. A positive gate voltage induces the electron inversion layer, which connects the n-type source and drain. Electrons flow from the source to the drain. MOSFET structure (p channel) Upper figure shows an p-channel enhancement mode MOSFET. A negative gate voltage induces the hole inversion layer, which connects the p-type source and drain. Holes flow from the source to the drain. Lower figure shows an n-channel depletion mode MOSFET. An n-channel region exists under the oxide with 0 V applied to the gate. The n-channel can be an electron inversion layer or an intentionally doped n region. Lower figure shows an p-channel depletion mode MOSFET. An p-channel region exists under the oxide with 0 V applied to the gate. The p-channel can be an hole inversion layer or an intentionally doped p region. Figure (a) shows an n-channel enhancement mode MOSFET with a gate-to-source voltage that is less than the threshold voltage and with only a very small drain-to-source voltage. Figure (b) shows an n-channel enhancement mode MOSFET with an applied gate voltage higher than threshold voltage. The source and substrate terminals are held at ground potential. There is no electron inversion layer, the drain-to-substrate pn junction is reverse biased, and the drain current is zero. An electron inversion layer has been created so that when a small drain voltage is applied, the electrons in the inversion layer will flow from the source to the positive drain terminal. The conventional current enters the drain terminal and leaves source terminal.
For small V DS values, the channel region has the characteristics of a resistor, so we can write, For small V DS values, the I D versus V DS are shown. Here, g d is the channel conductance. n is the mobility of the electrons in the inversion layer, and is the magnitude of the inversion layer charge per unit area. The inversion layer charge is a function of the gate voltage. Therefore, the basic MOS transistor action is the modulation of the channel conductance by the gate voltage. When, the drain current is zero. As V GS becomes larger than V T, channel inversion charge density increases, which increases the channel conductance. A larger value of g d produces a larger initial slope of the I D versus V DS characteristics. The conductance determines the drain current. Figure (a) shows the basic MOS structure for the case when, and the applied V DS is small. The thickness of the inversion channel layer in the figure indicates the relative charge density. The corresponding I D versus V DS curve is shown. When V DS increases to the point where the potential drop across the oxide at the drain terminal is equal to V T, The induced inversion charge density is zero at the drain terminal. The slope of the I D versus V DS curve is zero. Figure (b) shows when the V DS increases. As the drain voltage increases, the voltage drop across the oxide near the drain terminal decreases. The induced inversion charged density is decreased. The slope of the I D versus V DS curve decrease. + + V DS (sat) is the drain-to-source voltage producing zero inversion charge density at the drain terminal. When V DS becomes larger than the V DS (sat), the point in the channel at which the inversion charge is zero moves toward the source terminal. The saturation region. When V GS changes, the I D versus V DS curve will change. If V GS increases, the initial slope of I D versus V DS increases. The value V DS (sat) is a function of V GS. V DS (sat) is also increases. Figure shows an n-channel depletion mode MOSFET. A negative gate voltage will induce a space charge region under the oxide, reducing the thickness of the n-channel region. The reduced thickness decreases the channel conductance, which reduce the drain current. A positive gate voltage will create an electron accumulation layer, which increases the drain current.
The ideal current-voltage relation for the n-channel MOSFET In the nonsaturation region, Transconductance The MOSFET transconductance is defined as the change in drain current with respect to the change in gate voltage. The transconducance is referred to as the transistor gain. In the saturation region, If we consider an n-channel MOSFET operating in the nonsaturation region, The ideal current-voltage relation for the p-channel MOSFET In the nonsaturation region In the saturation region The transconductance increases linearly with V DS but is independent of V GS in the nonsaturation region. The transconductance in the saturation region, The transconductance is a linear function of V GS and is independent of V DS. Basic n-channel & p-channel MOSFET operation The CMOS Technology The properties of semiconductors make it possible to produce an entire electronic circuit within one single crystal. Such an integrated circuit miniaturizes electronic networks and also reduces the number of individual components in complex electronic circuits. The basis for the integrated circuit development is that many electronic components, such as transistors, diodes, and resistors, can be made of silicon having suitably disposed n-type and p- type regions. The CMOS Technology Photolithography Photolithography process 1. A thin layer of photoresist should be coated on a substrate by using spinner. 2. UV should be exposed to the photoresist through the photo mask. 3. Developer can develop the photoresist and make a three dimensional pattern on the surface. 4. We can etch the substrate or evaporate a materials through the pattern. 5. Typically, we can remove the pattern of photoresist using acetone.
Fabrication processes Silicon integrated circuits are fabricated by process of photolithography and etching processes. Gaseous diffusion of n-type and p-type impurities can be used to form n-type and p-type regions. Fabrication processes Fabrication processes The procedure results in the circuit diagrammed in figure(f). Note how the resistors and diodes are isolated from the p-type substrate in each instance by a pn junction. 1. A p-type single crystal chip is exposed to silicon vapor containing n-type impurity atoms. 2. The result is an n-type epitaxial layer. Epitaxial means that the n-type layer has the same crystal structure as the p-type substrate. 3. The surface is oxidized, masked, and etched, and a p-type diffusion isolates several n region. 4. These steps are repeated.