Digital to Analog Conversion (DAC) Digital to Analog Conversion Data Acquisition DACs or D/A converters are used to convert digital signals representing binary numbers into proportional analog voltages. Prof. Dr. M. Zahurul Haq http://teacher.buet.ac.bd/zahurul/ Department of Mechanical Engineering Bangladesh University of Engineering & Technology ME 6401: Advanced Mechatronics e566.eps A 4-bit input Binary-weighted D/A converter c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 1 / 24 Digital to Analog Conversion (DAC) c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 2 / 24 Digital to Analog Conversion (DAC) A DAC converts a digital word consisting of a number of bits into a voltage or current that represents the binary number value of the digital word. An 8-bit DAC, for example, may produce an output signal of 0 V when the binary word applied to its digital input is 00000000 2, and 2.55 V when the digital inputs see a word of 11111111 2. Similar to analog input configuration, a common DAC is shared among multiplexed output signals. Standard analog output ranges are essentially same as analog inputs: 5 V dc, 10 V dc, 0-10 V dc, and 4-20 ma dc. I E ref N M 1 E o IR r c m 2 m 1 R C m 0 or 1: depending on the mth bit value of the register that controls the switch setting. e570.eps c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 3 / 24 M-bit DAC c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 4 / 24
Digital to Analog Conversion (DAC) The binary weighted resistor ladder suffers from a series drawback in actual practice. The values of input resistors tend to become very large and very small at the ends of the range as the bit length of the input word becomes larger. If R is set to 10 kå, then R 8 will be 1.28 MÅ. If we assume a reference potential E of 5.0 V, then I 8 will be only 3.9 A which is too small to be resolved because of the noise problems. In commercial DACs, all the resistors have a value of either R or 2R. The gain of the amplifier is unity, so E o can be expressed as: Digital to Analog Conversion (DAC) DAC0808 and 741 op amp connected to form a DAC E o E n i 1 (provided that R L R, so that the voltage divider effect between the ladder and R L can be safely neglected). a i 2 i e602.eps c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 5 / 24 Analog to Digital Conversion c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 6 / 24 A/D Conversion Compromises In A/D conversion process continuous electrical signals are converted to the digital language of computers. If a 8-bit ADC has a 0-to-2.55 V input signal range, then a 0 V input could produce an output word of 00000000 2, while the +2.55 V level seen at the input would produce an output word of 11111111 2. e048.eps V τ Numbers 01010101 01010111 01100110 01111001...... c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 7 / 24 e054.eps A/D conversion processes pose two primary challenges: 1 Quantization - refers to uncertainty introduced upon conversion of an analog voltage to a digital number. 2 Sampling - refers to acquiring data only at discrete intervals, with no informations in between. c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 8 / 24
Analog to Digital Conversion Amplitude 10.00 111 8.75 110 7.50 101 6.25 100 5.00 3.75 2.50 1.25 0 011 010 001 000 0 20 40 60 80 100 120 140 e055.eps Digitized Sine Wave with a Hypothetical 3-Bit ADC e573.eps c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 9 / 24 Resolution & Quantization c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 10 / 24 Range of Values of Digital Quantities Resolution refers to the smallest signal that can be detected by a measurement system. It can be expressed in bits, in proportions, on in percentage of full scale. Resolution Q E Full Scale 2Number of Bits A system may have 12-bit resolution, one part in 4096 resolution, and 0.0244% of full scale. Quantization error is the inherent uncertainty in an A/D conversion due to the finite resolution of the system. An 8-bit ADC with E FS of 10 V could detect a minimum of 10/256 = 0.0391 V. The higher the resolution, the smaller the detectable voltage change. How many bits are needed to obtain a resolution of 0.01%? No of bits Number of States Resolution (%) 1 2 1 = 2 50 2 2 2 = 4 25 3 2 3 = 8 12.5 4 2 4 = 16 6.25 8 2 8 = 256 0.391 10 2 10 = 1024 0.098 12 2 12 = 4096 0.024 16 2 16 = 65536 0.001526 20 2 20 = 1048576 0.000095 c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 11 / 24 c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 12 / 24
Sampling Analog Signal & Sampled Equivalent Shanon s Sampling Theorem Sampling To faithfully represent the analog signal, sampling frequency f s such that must be greater than Nyquist frequency, f N : f s f N 2f max e571.eps Time interval between the digital samples is t 1 f s If f s f N, aliasing can result and totally non-existent frequencies may be indicated. Adequately Sampled Aliased Due to Undersampling e572.eps c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 13 / 24 e056.eps c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 14 / 24 Sampling Example: Effect of Sampling Rate Types of A/D Converters 1 Successive Approximation (SA) ADC 2 Flash/Parallel ADC 3 Dual-slope Integrating ADC 4 Servo/Binary-counter/Ramp ADC Type Speed Resolution Noise Immunity Cost 1. Medium 10-16 bits Poor Low 2. Fast 4-8 bits None High 3. Slow 12-18 bits Good Low 4. Slow 14-24 bits Good Medium e574.eps c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 15 / 24 c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 16 / 24
Successive Approximation ADC e575.eps c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 17 / 24 e569.eps c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 18 / 24 Block diagram of the ADC0804 ADC A SA register(sar) contains the control logic, a shift register, and a set of output latches, one for each register section. The outputs of the latches drive a DAC. A start pulse sets D7 (first bit of the shift register, MSB) high. DAC sees the word 10000000 2 & generates the output voltage, V out 1 2E FS. If V IN V out, then the D7 latch is set high, else it is set low. On the next clock pulse, D6 latch is set high. The process is continued through to LSB. If, on any trial, it is found that V IN V out, then the corresponding bit is reset low. The process is continued until the voltages match within the least significant bit. c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 19 / 24 e603.eps c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 20 / 24
Dual-slope Integrating ADC Parallel or Flash ADC e579.eps e568.eps Output represents the integral or average of an input voltage over a fixed period of time. Hence, it smooths out signal noise. c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 21 / 24 e578.eps c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 22 / 24 Ramp ADC ADC Speed Parameters e577.eps E ref, initially at zero, is increased at a set time steps & the ramp level is compared with the input voltage. The comparison is continued until the two are equal. The comparator output then goes to zero. It flips a flip-flop and the register count value will then indicate the digital binary equivalent of the input voltage. c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 23 / 24 1 Acquisition: is the time required by the front-end analog circuitry to acquire a signal. Also called aperture time, it is the time for which the converter must see the analog voltage in order to complete a conversion. 2 Conversion: is the time needed to produce a digital value corresponding to the analog value. 3 Transfer: is the time needed to send the digital value to the host computer s memory. Throughput, then, equals the number of channels being served divided by the time required to do all three functions. c Dr. M. Zahurul Haq (BUET) Data Acquisition ME 6401 24 / 24