22 CHAPTER 2 FIR ARCHITECTURE FOR THE FILTER BANK OF SPEECH PROCESSOR 2.1 INTRODUCTION A CI is a device that can provide a sense of sound to people who are deaf or profoundly hearing-impaired. Filters are used in many aspects of audiology and psychoacoustics including the peripheral auditory system. A filter is a device which boosts certain frequencies while attenuating others. In particular, a band-pass filter allows a range of frequencies within the bandwidth to pass through while stopping those which are outside the cut-off frequencies. The speech processor splits the auditory signal into bands of different frequencies and converts them into suitable codes for stimulating the electrodes implanted in the cochlea of the ear. The electrode activates auditory nerve fibres to provide hearing sensation. The cost of the CI alone goes to around 100,000 US dollars. For the economical less affluent people with hearing ailment, it may be too costly to afford for this equipment to recover from the hearing loss. It becomes necessary to bring down the cost. The cost reduction may be achieved with reduced area, low power and high speed operation of the CI. This objective intuited both the analog and the digital based CI designers to research their methods to provide people with cheaper and highly intelligible Cochlear implant.
26 approach of CIS is implemented here. It consists of filtering the input speech signals using a digital band-pass filter bank. A nonuniform filter bank strategy based on perceptual studies are chosen such that equal contribution to speech articulation is achieved. One such arrangement is the critical band scale, which has filter properties of human cochlea (Rabiner 1993). The scale is linear for frequencies below 1000Hz and is close to logarithmic for frequencies above 1000Hz. Using critical bandwidth phenomenon, human speech frequency ranging from 100 to 3500 Hz, is allocated to filter bands as in the work of Rekha et al (2008). This frequency range is covered by sixteen critical bands, which is shown in Table 2.1. Generally the numbers of filters in the filter bank depends on the number of channels which in turn depends on the number of stimulating electrodes as stated by Mahalakshmi and Reddy (2010). Table 2.1 Critical bandwidth as a function of centre frequency Channel number Frequency range of bandpass (3dB-points) Filter (Hz) Center Frequency (Hz) 1 150 125-175 2 250 225-275 3 350 325-375 4 450 420-480 5 570 530-605 6 700 655-745 7 840 790-890 8 1000 940-1060 9 1170 1105-1235 10 1370 1285-1455 11 1600 1505-1695 12 1850 1745-1955 13 2150 2005-2295 14 2500 2345-2655 15 2900 2705-3095 16 3400 3145-3655
27 2.3 REALISATION OF FILTER BANKS The speech processor of the cochlear implant consisting of filter banks, imitates the cochlea of human ear. Design methods for digital filters fall into two broad classes such as finite impulse response (FIR) filter or infinite impulse response (IIR) filter. For IIR filters, the straight forward and the efficient implementation is to realize each individual band pass filter as a cascade or parallel structure which is implemented in the next following chapters. Even though the characteristic of cochlea filter is nonlinear, the linear phase FIR filter is used here to overcome the disadvantages of IIR filter due to interaction of speech signal from different channels. FIR has several advantages over IIR filters. FIR filters do not have poles and are unconditionally stable. FIR does not accumulate errors since they depend on only a finite number of past input samples. The general definition of an FIR filter is given by Equation (2.1) M y[n] c kx[n k] (2.1) k 0 where y[n] is the FIR filter output, x [n-k] is the input data, M the finite length and c k represents the filter coefficients. The structure of direct form FIR which the equation 2.1 is shown in Figure 2.2.
28 Figure 2.2 Direct form structure of FIR filter FIR filters have only zeros (no poles). Hence known as all-zero filters. The speech signal is passed through a bank of band pass filters, which covers the entire speech spectrum range as depicted in Figure 2.3. Speech signal s(n) Band pass filter 1 Band pass filter 2 125-175 Hz 225-275 Hz Band pass filter 16 3145-3655 Hz Figure 2.3 Model of filter bank for speech processor
29 2.4 FIR FILTER DESIGN The specifications chosen for the FIR filter bank design are the number of channels as 16, stop band attenuation as 60 db and the pass band spacings for the filterbanks are as critical bands given in Table 2.1. 2.4.1 Windowing Method for FIR Filter The desired frequency response H(e ) of a filter using Fourier series is given by Equation (2.2) and known as Fourier coefficients having infinite length. H(e ) h e (2.2) n d FIR filter is obtained by truncating the infinite Fourier series at n = ±, where N is the length of the desired sequence. Abrupt truncation of the Fourier series results in oscillations in pass band and stop band regions of the filter. An optimal way to reduce these oscillations is to use an appropriate finite length window w(n), which controls the overall filter in order to yield a smooth frequency response. Therefore, a window should possess some of the following spectral characteristics. 1. The main lobe width (w m ) of the frequency response of the window should be narrow. 2. The ripple ratio (R) should be small 3. The side-lobes should decrease in energy rapidly as tends to. 4. To adequately block the stop band frequencies, it is necessary to have good stop band attenuation.
30 The symmetrical frequency spectrum of an odd length window w(nt) is given in Equation (2.3). N 1 2 w(e ) w(0) 2 w(nt) cos ( nt) (2.3) n 1 Standard windows such as Rectangular, Hamming, and Hanning have only one independent parameter, namely the window length N, which controls the transition width of the filter. But the minimum stop band attenuation of the filter is independent of N. In order to overcome this, a Kaiser window is used, which has an adjustable parameter that controls stop band attenuation and an independent parameter N that controls the transition width. Kaiser window is widely used for the spectral analysis and FIR filter design applications. 2.4.2 Algorithm for Filter Design using Kaiser Window The design of band pass filter using Kaiser Window (Sanjit 2008) is done based on the following steps. Step 1 Equation (2.4). The ideal frequency response of a bandpass filter is given by H(e ) = 0 for 1 for 0 for 2 (2.4) The design is based on the narrower of the two transition bandwidths, given by B t = min [( ), ( )], where (, ) and (, ) are the initial and final transition edge frequencies of the band
31 pass filter. The cut-off frequencies are given by = B 2 and = + B 2 with as sampling frequency. Step 2 Assuming that the pass band ripple is approximately equal to the stop band ripple given by =, and on basis of = min,, the length N is computed using Equation (2.5).. (2.5) Step 3 Kaiser Window sequence is given by Equation (2.6) w(n) = I [ ( )] ( ), ( 1) 2 n ( 1) 2 (2.6) where is an adjustable parameter, and I 0 (x) is the modified zeroth order Bessel function, which can be expanded into the following series given by Equation (2.7). I (x) = ( )! (2.7) which is seen to have a positive value for all real values of x. Step 4 The desired minimum stop band attenuation is calculated by = 20 log. Parameter is computed from Equation (2.8).
32 = 0.1102( 8.7), for > 50, 0.5842( 21). + ( 21) for 20 50, 0 for < 21. (2.8) Step 5 The coefficients of linear phase filter with delay = are computed using Equation (2.9) h (n) = ( ) ( ) ( ), for n = 0, for 0 (2.9) Step 6 The impulse response h(n) is obtained by multiplying the desired impulse response h d (n) of the ideal filter and the window coefficient generated in step 3 to yield the coefficients of FIR filter as given in Equation (2.10). h(n) = h d (n).w(n) (2.10) Step 7 Equation (2.11). The magnitude function of FIR filter when N is odd is generated by H( ) = h + 2h n cos( n) (2.11) Using these algorithm steps the order of the FIR filter with Kaiser window is calculated to be 877 for the given specification of the filter with stop band attenuation approximately equal to -60 db.
33 2.5 PROPOSED ARCHITECTURE FOR THE FIR FILTER BANKS There is an FIR filter block in the System Generator library that employs Distributed Arithmetic (DA) to map the computation into the FPGA and filter block is referred as DA FIR. This block provides a highly parameterizable, optimized multiplier less architecture for the FIR filter. This work proposes the XSG block level structure for the implementation of filter banks using the DA FIR for CI. 2.5.1 FIR Filter using Distributed Arithmetic DA is a different approach for implementing digital filters. The basic idea is to replace all multiplications and additions by a look up table, barrel shifter and accumulator. DA relies on the fact that the filter coefficients are known, so multiplying c[n]x[n] becomes a multiplication with a constant. This is an important difference and a prerequisite for a DA design. DA is used to compute sum of products. Many DSP algorithms like convolution and correlation are formulated in a sum of products (SOP) fashion. Consider the following sum of products in Equation (2.12). N 1 y c, x c[n] x [n] c[0] x [0] c[1] x[1]... c[n 1] x [N 1] (2.12) n 0 Further assume that the coefficients c[n] are known values and that the variable x[n] is represented by Equation (2.13). x[n] B 1 b x b [n] 2 with x b[n] [0,1] (2.13) b 0
34 where x [n] represents the b th bit position of the number s binary representation. The SOP is represented as Equation (2.14) N 1 N 1 b y c, x c[n] x b[n] 2 (2.14) n o b o Expanding the above summations yields Equation (2.15) y = c, x = c[0] (x [0]2 + x [0]2 x [0]2 ) + c[1] (x [1]2 + x [1]2 x [1]2 ) + c[ 1] (x [ 1]2 + x [ 1]2 x [ 1]2 ) (2.15) Redistributing the terms of Equation (2.15) yields Equation (2.16). y = c, x = (c[0]x [0] + c[1]x [1] + c[ 1]x [ 1]) 2 + (c[0]x [0] + c[1]x [1] + c[ 1]x [ 1]) 2 + (c[0]x [0] + c[1]x [1] + c[ 1]x [ 1]) 2 (2.16) This equation is further simplified as Equation (2.17). B 1 N 1 b y c, x 2 c[n] x [n] (2.17) b o b o b The key is to realize that the second summation can be mapped to a Look Up Table (LUT). The coefficients c[n] are known and the x [n] values are either 1 or 0 then each SOP is just a combination of the c[n] s for which LUT can be constructed. Multiplication by a power of 2 is not only a bit shift, it is needed to slice and concatenate the bits of the different x[n] in order to build a table given that the c[n] are all known. For signed
35 implementations of DA, minor modification needs to be introduced when working with signed two s complement numbers. In two s complement, the MSB is used to determine the sign of the number. Hence, the output y[n] is defined by Equation (2.18) y [n] c,x B 2 1 x N n 1 c[n] o X B [n] 1 B b 2 o b 2 N n 1 c[n] o x [n] b (2.18) Finally, a block diagram for the DA implementation of a FIR filter is shown in Figure 2.4. Bit shift register Arith. Table Scaling Accumulator... X B-1 [0] X 1 [0] X 0 [0] X B-1 [1]... X 1 [1]...... X B-1 [N-1]... X 1 [N-1] X 0 [1]... X 0 [N-1] L U T +/- Register Figure 2.4 The block diagram for the DA implementation of a FIR filter 2.5.2 Generation of Filter Coefficients Each DA FIR block used in the filter banks requires the coefficients to generate the filter response which is exported from the FDA tool particular to that DA FIR block. Filter design and analysis tool (FDATool) of MATLAB is a Graphical User Interface (GUI) that allows designing, importing and analysing digital filters. FDA tool is enabled to generate the required coefficients by providing input parameters like length N
36 of Kaiser window equal to 877, upper and lower cut-off and parameter of value equal to 6 in order to obtain stop band attenuation approximately equal to -60dB. Figure 2.5 shows the magnitude response of the narrow pass band FIR filter having = 3655 Hz and =3145Hz which helps to analyse the design for the required specification. Figure 2.5 Magnitude response of a single band pass FIR filter using FDA tool 2.6 IMPLEMENTATION OF PROPOSED 16 CHANNEL FIR FILTER BANK The block processing work flow of XSG is used in the implementation of FIR filter; since it reduces the time of writing, coding and debugging. The advantage of block processing is that the software itself will convert the processing block to its equivalent HDL code. This is called hardware software co-simulation and hence implementing a complex cochlea FIR filter seems to be easier by this work flow. System Generator tool of
37 Xilinx includes a FIR Compiler block that represents the single FIR band pass filter of order 877 that targets the dedicated hardware resources in the FPGA devices to create highly optimized implementations. The block diagram using XSG blocksets for the single FIR band pass filter is shown in Figure 2.6. Each channel consists of 878 tap DA FIR filter and the corresponding FDA Tool generates 878 numbers of coefficients according to the input parameters provided to produce the magnitude response. The input parameters, for each of the 16 channels are obtained from the corresponding critical bands of frequencies as given by Table 2.1. In the similar way the other filters in the filterbanks are designed for the sixteen critical bands of frequencies shown in table 2.1 and are implemented using the XSG blocks as shown in the Figure 2.7 Figure 2.6 A single DA FIR filter with critical band frequency range of 3145-3655 Hz
38 Figure 2.7 The block diagram of sixteen channel filter bank using DA FIR filter 2.7 RESULTS AND DISCUSSIONS Input audio signal is fed to the designed DA FIR filter block designed for critical band frequency of 3145 to 3655 Hz as shown in Figure 2.6 and the input speech spectrum is as shown in Figure 2.8. Figure 2.9 shows the filtered output from the single channel of filter bank. In the similar way the other filters in the filterbanks are designed for the sixteen critical bands of frequencies shown in table 2.1 and are implemented using the XSG blocks as shown in the Figure 2.7. A random signal source is used for verifying the functionality of the filter bank. FIR filter in each channel splits the signal into critical bands of frequencies as the basilar membrane in the biological cochlea shown in Figure 2.1. Filtered output signal from all the 16 channels using random signal source as input is shown in Figure 2.10 The filter bank is again tested with the recorded signal from the audio video input file. The input audio spectrum is shown in Figure 2.11 The filtered output of the filter bank as shown in Figure 2.12.
39 Figure 2.8 Input speech spectrum for single channel DA FIR filter Figure 2.9 Filtered output for the single channel with critical band frequency of 3145-3655 Hz
40 Figure 2.10 Filtered output from 16 channel filter bank for random source signal Figure 2.11 Input speech spectrum for the 16 channel filter bank
41 Figure 2.12 Filtered output from the 16 channel of filter bank 2.7.1 Resource Utilization and Power Consumption The sixteen channel filter bank implemented by highly parameterised and optimised XSG blocks generates the synthesizable HDL code which is downloaded as the bitstream into FPGA board through Joint Test Association Group (JTAG) cable. System Generator generates a hardware block known as JTAG Co-sim that represents FPGA hardware model of filter bank design. Simulink transmits sample to FPGA for processing via Simulink sources such as the microphone and unbuffered block in Figure 2.8. FPGA transmits the filtered signal to Simulink. The filtered signal is viewed simulink sink block such as Fast Fourier Transform (FFT) scope. The hardware generated simulation and the software generated simulation are similar. XSG block of DA FIR is the software model and JTAG Co-sim is the FPGA hardware model. Both these models are shown in Figure 2.13.
42 Figure 2.13 The single channel filter with JTAG Co-sim block The synthesizable HDL code generated from the XSG blocks of filter banks are exported to Integrated Sytem Editor (ISE) tool to synthesize and download the designed filter banks on Virtex 7 FPGA board. The synthesised report of the designed filter gives the hardware resources utilization as tabulated in Table 2.2. Table 2.2 Resource utilization of 16 channel filter bank on Virtex 7 FPGA board Resources Numbers Available on the board % used for implementation Slices 43, 804 305,400 14 LUTs 71, 109 74,755 95 Flip flops 71, 109 74,755 95 IOB 65 1200 5 2.8 CONCLUSION The results of the implemented 16 channel DA FIR based filter bank are validated by experimenting the designed filter bank with real time input speech signal fed through the microphone in the Simulink signal source
43 block as shown in Figure 2.13 and the corresponding filtered output signal showed the splitting of input speech spectrum to sixteen different critical bands of frequency components. According to CIS algorithm of speech processor the signal energy extracted from the output of these filter banks is converted to stimulating pulse that excites the micro electrodes inside the ear to stimulate the auditory nerve. XSG based DA FIR filter proves that design, analysis and testing of the filter with real time signal is possible in minimal duration of time. FIR realisation for the filter bank occupies 50 % more area and also more power consumption than IIR realisation of filter bank. Hence the following third and fourth chapters deal with low area, low power and high speed architectures for the IIR realisation of filter bank.