Lab #10: Finite State Machine Design Zack Mattis Lab: 3/2/17 Report: 3/14/17 Partner: Brendan Schuster
Purpose In this lab, a finite state machine was designed and fully implemented onto a protoboard utilizing 2 inputs to create a unique output sequence over a series of 8 clock cycles. The design was built and simulated using Altera Quartus 9.1. The utilization of this software enabled a simulation of the output waveform based on simulated inputs. With the confirmation of the design from the Quartus simulation, the design was implemented on a breadboard using the following ICs: 2 D Flip-Flops (74LS74), 1 AND (74LS08), 1 OR (74LS32), 1 XOR (74LS86), 1 8:1 Multiplexer (74LS151), and 1 555 timer. Additionally, 4 resistors, 2 capacitors, and 1 8-pronged SPST switch. Finally, the finished design was tested using LogicPort software to ensure proper operation. The design constraints for the output can be seen in Figure 1. AB Z 00 01 10 11 0000000100000001... 0000011100000111... 0001111100011111... 0111111101111111... Figure 1 Procedure The original design for the finite state machine was initially created from the state transition diagram that can be seen in Figure 2 below. Our design utilized a Mealy Machine design to reduce the number of necessary states. This diagram was then utilized to create a state transition table to determine the next state based on inputs and previous states. This table can be seen in Figure 3 below. Using the state transition table, we designed a synchronous 3-bit counter to store states 0-7. This design uses D flip flops (74LS74 IC) and can be seen in Figure 4 below. In order to generate the output of the design, an 8:1 multiplexer was utilized that uses the flip flop states Q2-Q0 as select lines and combinational logic of inputs A and B for the MUX inputs. This design can be seen in Figure 5 below. The final design of the finite state machine utilizes 2 XOR gates, 2 AND gates, 1 OR gate, as well as 3 D flip-flops, 1 555 timer, and 1 8:1 MUX. This design can be seen in Figure 6 below.
Figure 2 Figure 3 Figure 4 Figure 5
Figure 6 After completion of the design, the circuit was created using Altera Quartus 9.1 to analyze its behavior. The completed design can be seen in Figure 7 (see attached). The Quartus software includes a waveform simulation that can be used to see the output of the created circuit. Using the NodeFinder function, Quartus was able to take all of the input and output signals and translate them into the waveform simulation. This simulation allows for user inputted data for each of the inputs. For our design implementation, we utilized a high signal for both the preset and clear inputs combined with an oscillating square-wave input for the clock. After running the simulation, the output of the Q signals can be observed. Additionally, the output sequence for inputs A=0, B=0 can be seen in Figure 8 (see attached). Inputs A=1, B=1 are visible in Figure 9 (see attached). After verification of the circuit operation from the Quartus software, the design was physically implemented on the protoboard through the use of IC chips and wires. The finished circuit implementation can be seen in Figure 10 below. In order to test the functionality of the protoboard circuit, the oscilloscope was used to observe the output waveform of the finite state machine. The output of the circuit for inputs 00, 01, 10, and 11 can be seen in Figures 11, 12, 13, and 14, respectively.
Figure 10
Figure 11 Figure 13 Figure 12 Figure 14
Finally, our design was tested using the LogicPort Logic Analyzer. This devices converts the analog signal of the circuit into a digital form of 0s and 1s. This tool enables effective observation of the circuit s inputs and outputs. In our testing, we connected the device to our clock as well as 6 inputs. Inputs D0-D5 were: input A, input B, Q0, Q1, Q2, and output. The generated waveforms for inputs 00, 01, 10, and 11 can be observed in Figures 15, 16, 17, and 18, respectively (see attached). Results The schematic of the design for the finite state machine can be seen in Figures 6 and 7. By using combinational logic, we were able to successfully create a 3-bit synchronous counter to store states 0-7. This was achieved using XOR gates with the lower bit Q value(s) as well as the previous Q state. For example, input D1 = Q0 Q1 and input D2 = Q0Q1 Q2. With each state stored in the flip-flops, the Q values can be used as the select lines for an 8:1 MUX to get the correct output for the specified state. Combinational logic of the inputs A and B were used to get inputs M0 M7 for the MUX. These inputs were 0, AB, AB, A, A, A+B, A+B, and 1, respectively. The 555 timer, as seen in Figure 19 below, was designed using a capacitance of 10.8 nf and a resistance of 500 Ω. This output timing was calculated using the equations from the ECE 501 Lab Manual. This device implementation led to a calculated period T was 10.397 μ s. The output of this timing circuit was used as the input for the clocking signal of each D flip-flop. Figure 19
The Quartus implementation of the finite state machine verified the operation of the design, providing the necessary output waveform as specified in the design constraints. After physical implementation on the protoboard, both the oscilloscope and the LogicPort Logic Analyzer further verified proper operation of the circuit. As the inputs A and B increased from 00 to 11, the time high (th) of the output waveform increased as well. This can be seen in Figures 11-14 for the oscilloscope and Figures 1518 for the Logic Analyzer. The resultant duty cycles of the output waveform for inputs 00, 01, 10, and 11 were ~ 12.5%, 37.5%, 62.5%, and 87.5%, respectively. These duty cycles are consistent with the expected outputs of the finite state machine. Conclusion Our original design (Figure 6) proved to be a successful implementation of the finite state machine. With the design constraint of the circuit switching to the proper output sequence at any point based on the inputs A and B, the design was greatly simplified to a Mealy Machine with only 8 states. These 8 states were stored using a 3bit synchronous counter, which shared a common clock from a 555 timer. The ability to use a MUX further simplified the design as the use of the Q states of the flip-flops as the select lines allowed for MUX inputs dependent only upon A and B. These inputs were implemented through the use of simple combinational logic. Both the oscilloscope and LogicPort Logic Analyzer verified proper operation of the finite state machine by providing the output waveform with the corresponding duty cycles. The use of circuit simulation software, specifically LogicPort, provided an effective and efficient technique of converting the analog signals of the circuit into digital waveforms for easy viewing. References 1. ECE 0501 Digital Systems Laboratory Custom Course Materials. Laboratory Notebook. University of Pittsburgh.