WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 Low Skew for Clock-Distribution and Clock-Generation pplicatio TTL-Compatible Inputs and s Distributes One Clock Input to Six Clock s Polarity Control Selects True or Complementary s Distributed V CC and Pi Reduce Switching Noise High-Drive s ( 48-m I OH, 48-m I OL ) State-of-the-rt EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Packaged in Plastic Small-Outline Package Y Y Y Y Y D PCKGE (TOP VIEW) 4 6 7 8 6 4 0 9 Y T/C V CC T/C V CC T/C description The CDC9 contai a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. Through the use of the polarity-control (T/C) inputs, various combinatio of true and complementary outputs can be obtained. The output-enable () input is provided to disable the outputs to a high-impedance state. The CDC9 is characterized for operation from 40 C to 8 C. FUNCTION TBLE INPUTS OUTPUT T/C Y H X X Z L L L L L L H H L H L H L H H L Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Itruments Incorporated. PRODUCTION DT information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Itruments Incorporated POST OFFICE BOX 60 DLLS, TEXS 76
WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 logic symbol 9 EN T/C T/C T/C 0 N N N 6 6 8 Y Y Y Y Y Y This symbol is in accordance with NSI/IEEE Std 9-984 and IEC Publication 67-. logic diagram (positive logic) 9 T/C 6 Y Y Y Y T/C 6 Y T/C 0 8 Y POST OFFICE BOX 60 DLLS, TEXS 76
WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC.......................................................... 0. V to 7 V Input voltage range, V I (see Note ).................................................. 0. V to 7 V Voltage range applied to any output in the high state or power-off state, V O....... 0. V to V CC + 0. V Current into any output in the low state, I O.................................................. 96 m Input clamp current, I IK (V I < 0)........................................................... 8 m clamp current, I OK (V O < 0)....................................................... 0 m Maximum power dissipation at T = C (in still air) (see Note ).............................. 0.77 W Storage temperature range, T stg.................................................. 6 C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.. The maximum package power dissipation is calculated using a junction temperature of 0 C and a board trace length of 00 mils. For more information, refer to the Package Thermal Coideratio application note in the 994 BT dvanced BiCMOS Technology Data Book, literature number SCBD00B. recommended operating conditio (see Note ) MIN NOM MX UNIT VCC Supply voltage 4.7. V VIH High-level input voltage V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V IOH High-level output current 48 m IOL Low-level output current 48 m t/ v Input traition rise or fall rate / V fclock Input clock frequency 00 MHz T Operating free-air temperature 40 8 C NOTE : Unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PRMETER TEST CONDITIONS MIN TYP MX UNIT VIK VCC = 4.7 V, II = 8 m. V VOH VCC = 4.7 V, IOH = 48 m V VOL VCC = 4.7 V, IOL = 48 m 0. V II VCC =. V, VI = VCC or ± µ IOZ VCC =. V, VO = VCC or ±0 µ IO VCC =. V, VO =. V 00 m ICC VCC =. V, IO = 0, VI =VCC or s high 0 s low 40 m s disabled 0 Ci VI =. V or 0. V pf Co VO =. V or 0. V pf ll typical values are at VCC = V, T = C. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. POST OFFICE BOX 60 DLLS, TEXS 76
WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures and ) PRMETER tplh tphl tplh tphl tpzh tpzl tphz tplz tsk(o) FROM (INPUT) T/C TO (OUTPUT) ny Y ny Y ny Y ny Y MIN MX UNIT..... 7 ny Y (same phase) 0. ny Y (any phase) tsk(p) ny Y tr. tf. 4 POST OFFICE BOX 60 DLLS, TEXS 76
WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 PRMETER MESUREMENT INFORMTION From Under Test CL = 0 pf (see Note ) 00 Ω 00 Ω S 7 V Open TEST tplh/tphl tplz/tpzl tphz/tpzh S Open 7 V Open Input tplh tr LOD CIRCUIT FOR OUTPUTS. V. V 0.8 V V. V VOLTGE WVEFORMS PROPGTION DELY TIMES tf V tphl 0.8 V V 0 V VOH VOL Control (low-level enabling) Waveform S at 7 V (see Note B) Waveform S at Open (see Note B) tpzl tpzh. V tplz. V tphz. V. V VOLTGE WVEFORMS ENBLE ND DISBLE TIMES V 0 V. V VOL + 0. V VOL VOH VOH 0. V 0 V NOTES:. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform is for an output with internal conditio such that the output is high except when disabled by the output control. C. ll input pulses are supplied by generators having the following characteristics: PRR 0 MHz, ZO = 0 Ω, tr., tf.. D. The outputs are measured one at a time with one traition per measurement. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX 60 DLLS, TEXS 76
WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 PRMETER MESUREMENT INFORMTION T/C Y tplh tphl tplh tphl Y tplh tphl tplh6 tphl6 T/C Y tplh tphl tphl7 tplh7 Y tplh4 tphl4 tphl8 tplh8 NOTES:. skew, tsk(o), from to any Y (same phase), can be measured only between outputs for which the respective polarity-control inputs (T/C) are at the same logic level. It is calculated as the greater of: The difference between the fastest and slowest of tplh from to any Y (e.g., tplhn, n = to 4; or tplhn, n = to 6) The difference between the fastest and slowest of tphl from to any Y (e.g., tphln, n = to 4; or tphln, n = to 6) The difference between the fastest and slowest of tplh from to any Y (e.g., tplhn, n = 7 to 8) The difference between the fastest and slowest of tphl from to any Y (e.g., tphln, n = 7 to 8) B. skew, tsk(o), from to any Y (any phase), can be measured between outputs for which the respective polarity-control inputs (T/C) are at the same or different logic levels. It is calculated as the greater of: The difference between the fastest and slowest of tplh from to any Y or tphl from to any Y (e.g., tplhn, n = to 4; or tplhn, n = to 6, and tphln, n = 7 to 8) The difference between the fastest and slowest of tphl from to any Y or tplh from to any Y (e.g., tphln, n = to 4; or tphln, n = to 6, and tplhn, n = 7 to 8) Figure. Waveforms for Calculation of t sk(o) 6 POST OFFICE BOX 60 DLLS, TEXS 76
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