ATF-531P8 9 MHz High Linearity Amplifier Application Note 1372 Introduction This application note describes the design and construction of a single stage 85 MHz to 9 MHz High Linearity Amplifier using Enhancement Mode phemt ATF-531P8. The amplifier has a typical gain of 22 db and an output third order intercept point (OIP3) of 38 dbm when biased at 4V,135 ma. The Avago Technologies EDA software, ADS 22, is used in the design of the input and output matching networks. The complete amplifier is shown in Figure 1. ATF-531P8 The ATF-531P8 E-pHEMT FET features a combination of industry-leading performance features, including.6 db noise figure with +38 dbm third-order output intercept point (OIP3) at 9 MHz. It is ideal for first and second stage front-end LNAs and for use in radio cards. Its +24.5 dbm linear output power capability (at 1 db gain compression) is the right level for pre-driver amplifiers. The ATF 531P8 datasheet contains specifications at 2 GHz and 4V, 135 ma. The ATF-531P8 is ideally suited to meet the needs of nextgeneration 2.5G and 3G base stations, which demand very high linearity for accurate signal transmission and high transmission power levels with minimum electrical power consumption and component heat generation. The Avago Technologies ATF-531P8 E phemt FET offers performance optimized for the first and second stages of front-end low noise amplifiers (LNAs) and driver or predriver amplifiers in cellular base stations in the 9 MHz, 1.9 GHz, and 2.1 GHz frequency bands. It is also ideal for fixed wireless, WLAN, and other applications calling for high performance in the 5 MHz to 6 GHz frequency range. The ATF-531P8 is housed in the compact and thermally efficient 2. mm x 2. mm x.75 mm 8 pad plastic package (see Figure 1). It conforms to the industry-standard leadless plastic chip carrier JEDEC DRP-N LPCC package. (JEDEC Solid State Technology Association is the semiconductor engineering standardization body of the Electronic Industries Alliance). The miniature LPCC surface mount plastic package occupies significantly less board space than conventional SOT-89 devices. All the new FETs feature very high reliability with a predicted point MTTF (single-point mean time to failure) of over 3 years at a mounting temperature of +85 C. The ATF-531P8 is one of a family of high dynamic range, low noise enhancement mode PHEMT devices designed for use in low cost commercial applications in the VHF through 6 GHz frequency range. Description This paper describes the design of a high linearity amplifier for 85 to 9 MHz applications. The focus is on the design considerations as well as the expected and actual performance. The original design draft was a low noise amplifier with an output third order intercept point (OIP3) of 38 dbm with a noise figure close to 3. db at 9 MHz and gain above 21 db, while biased at a Vds of 4.V and a Ids of 135 ma. This would enable the amplifier to be biased from a supply voltage range of 5. 6. volts.
Design Method A linear simulation of the 4V, 135 ma S-parameters shows that the ATF-531P8 is conditionally stable below 2 GHz. The ATF 531P8 has over 22 db gain between 85 MHz to 9 MHz. This makes the first priority for the design to stabilize the FET so that the stability factor K>1 within the design frequency. The final amplifier design is unconditionally stable both in and out of band. Any resistive loading on the output of the ATF-531P8 would affect P-1dB and OIP3 performance, while loading on the input would R2 Q1 degrade noise figure performance. Consideration was also given to input and output return loss with a target minimum VSWR of 2:1. A high pass filter structure was adopted on the input consisting of L1, C1, and L2. The stability circuit was then added in the form of a shunt capacitor C2 and R7. The linear S- parameter simulation also revealed that L3 was a fundamental part of the stabilization circuit as well as being part of the matching network. The output circuit was optimized on the test bench for IP3 and the results checked with the linear simu- VE R1 Vdd lation. It was found that the output IP3 could be increased to over 4 dbm with resulting poor output return loss, typically 5 db. The linear simulation showed that by slightly reducing the values of both L1 and L3, the output return loss was improved at the cost of degraded OIP3 performance. These adjustments reduced the IP3 performance to typically 38 39 dbm, and the target VSWR spec was met. Biasing Options and Source Grounding In order to meet the design goals for noise figure, intercept point, and gain, the drain source current (Ids) was chosen to be 135 ma. As indicated by the characterization data shown in the device data sheet, at bias of 4 Vds, 135 ma gives a typical IP3 of 37 dbm at 9 MHz. RFin L1 C1 C4 C3 C2 R7 R4 Figure 1. ATF-531P83 85 9 MHz HLA Active Bias Circuit Schematic. R5 L2 Vg L3 Q2 2 7 3PL ATF-531P8 R3 Vds R6 L4 C5 C6 C7 C8 L5 RF out Active Bias For high volume applications, it is recommended that the ATF- 531P8 use active biasing. The main advantage of an active biasing scheme is the ability to hold the drain to source current constant over a wide range of temperature variations. A very inexpensive method of accomplishing this is to use two PNP bipolar transistors arranged in a current mirror configuration as shown in Figure 1. Due to resistors R1 and R3, this circuit is not acting as a true current mirror. However, if the voltage drop across R1 and R3 is kept identical, then it still displays some of the more useful characteristics of a current mirror. 2
For example, transistor Q1 is configured with its base and collector tied together. This acts as a simple PN junction, which helps temperature compensate the emitter-base junction of Q2. To calculate the values of R1, R2, R3, and R4, the following parameters must be known or chosen first: I ds is the device drain-to-source current. I R is the reference current for active bias. V dd is the power supply voltage available. V ds is the device drain-to-source voltage. V g is the typical gate bias. V be1 is the typical base-emitter turn on voltage for Q1 & Q2. Table 1. Component Parts List. C1=2.2 pf 42 Chip Capacitor C2=3.3 pf 42 Chip Capacitor C3=15 pf 42 Chip Capacitor C4, C6=.1 µf 42 Chip Capacitor C5=1 µf 85 Chip Capacitor C7=22 pf 42 Chip Capacitor C8=82 pf 42 Chip Capacitor L1, L2=1 nh TOKO LL15-FH1N L3, L5=8.2 nh TOKO LL15-FH8N2 L4=18 nh TOKO LL168-FSR18 R1=6.4Ω R2=374Ω R3=4.32Ω R4=68.1Ω R5=1Ω R6=1.2Ω R7=5Ω Q1, Q2 BCV62C FET ATF-531P8 Therefore, resistor R3, which sets the desired device drain current, is calculated as follows: R3 = V dd V ds I ds + I c2 (1) where, I C2 is chosen for stability to be 1 ma and also equal to the reference current I R. Ic2 = Ie2 assuming the hfe of the PNP transistors is high. The next three equations are used to calculate the rest of the biasing resistors for Figure 1. R1 = V dd V ds (2) I R Note that the voltage drop across R1 must be set equal to the voltage drop across R3, but with a current of I R. R2 = V ds V be1 I R (3) R2 sets the bias current through Q1. R4 = V g I C2 (4) R4 sets the gate voltage for the ATF 531P8. Thus, by forcing the emitter voltage (V E ) of transistor Q1 equal to V ds, this circuit regulates the drain current similar to a current mirror. As long as Q2 operates in the forward active mode, this holds true. In other words, the collector-base junction of Q2 must be kept reverse biased. ATF-531P8 High Linearity Amplifier Design Using Avago Technologies EEsof Advanced Design System Software, the amplifier circuit can be simulated in both linear and non-linear modes of operation. Linear Analysis For the linear analysis the transistors can be modeled with a two port S-parameter file using the Touchstone format. The ATF531P83.s2p file can be downloaded from the Avago Technologies Wireless Design Center website. Non-Linear Analysis For the non-linear analysis, a harmonic balance (HB) simulation was used. HB is preferred over other non-linear methods because it is computationally fast, handles both distributed and lumped element circuitry, and can easily include higher order harmonics and intermodulation products. [2] In this application, HB was used for simulation of the1 db compression point (P-1dB) and the output third order intercept point (OPI3). The non-linear transistor model for the ATF-531P8 is based on the work of Curtice. [1] The model can be downloaded from Avago Technologies website. 3
An important feature of the nonlinear model is the use of a quadratic expression for the drain current versus gate voltage. Although this model closely predicts the DC and small signal behavior (including noise), it does not predict the intercept point correctly. For example, the amplifier OIP3 was simulated at +3.8 dbm and the P-1dB at +2.5 dbm. The simulated performance for P-1dB was very close to the measured results, however, the simulated OIP3 was too low. To properly model the exceptionally high linearity of the E-pHEMT transistor, a better model is needed. This model, however, can still be used to predict the relative importance of output matching, bias, and P-1dB. Circuit Stability Besides providing important information regarding gain, P-1dB, noise figure, input and output return loss, the computer simulation provides very important information regarding circuit stability. Unless a circuit is actually oscillating on the bench, it may be difficult to predict instabilities without actually presenting various VSWR loads at various phase angles to the amplifier. Calculating the Rollett stability factor, K, and generating stability circles are two methods made considerably easier with computer simulations. PCB Layout A recommended PCB pad layout for the leadless plastic chip carrier (LPCC) package used by the ATF- 531P8 is shown in Figure 2. This layout provides plenty of plated through-hole vias for good thermal and RF grounding. It also provides a good transition from a microstrip to the device package. For more detailed dimensions refer to pages 13 and 14 of the ATF 531P8 data sheet. Figure 2. Microstripline Layout. RF Grounding Unlike SOT packages, the ATF-531P8 is housed in a leadless package with the die mounted directly to the lead frame or the belly of the package shown in Figure 3. Pin 8 Drain 7 Pin 6 Pin 5 Bottom View Source 1 Gate 2 Pin 3 Source 4 Figure 3. LPCC Package for ATF-531P8. This simplifies RF grounding by reducing the amount of inductance from the source to ground. It is also recommended to ground pins 1 and 4 since they are also connected to the device source. Pins 3, 5, 6, and 8 are not connected, but may be used to help dissipate heat from the package or for better alignment when soldering the device. This three-layer board contains a 1 mil layer and a 52 mil layer separated by a ground plane. The first layer is Getek RG2D material with a dielectric constant of 3.8. The second layer is for mechanical rigidity and consists of FR4 with a dielectric constant of 4.2. Results Results from the simulation of gain and noise figure are shown in Figure 6. Simulation results for input and output return loss are shown in Figure 7. 4
+Vg +Vd Avago J2 J1 IN OUT SE 9/22 DEMO-ATF-5x1P8 Figure 4. RF Layout for Demo Board. +Vg +Vd C5 Avago R2 R4 BCV62B R1 R3 J2 J1 IN OUT SE 9/22 DEMO-ATF-5x1P8 Figure 5. Assembly Drawing for Active Bias Circuit. 5
25 1 2 15 8 GAIN, db 1 5-5 6 4 NOISE FIGURE, db -1-15 -2 Gain Noise Figure.45.9 1.35 1.8 2.25 Figure 6. Simulation Results for Gain and Noise Figure. FREQUENCY, GHz 2 INPUT AND OUTPUT RETURN LOSS, db -2-4 -6-8 -1-12 Input RL Output RL -14.45.9 1.35 1.8 2.25 FREQUENCY, GHz Figure 7. Simulation Results for Input and Output Return Loss. 6
Summary The results obtained from the demoboard described in this note show the potential use of the ATF-531P8 as a linear amplifier for 8 9 MHz applications. A summary of the measured results is shown in Table 2. Results from the measured gain and noise figure are shown in Figure 8. Measured results for input and output return loss are shown in Figure 9. The stability network on the input is responsible for the 3. db noise figure. Table 2. Measured Results Frequency, MHz 9 Gain, db 22.3 Noise Figure, db 3. Input Return Loss, db 1.8 Output Return Loss, db 9.6 P-1dB, dbm 2.7 Output IP3, dbm 38. 25 2 15 1 8 GAIN, db 1 5-5 -1 2 Gain -15 Noise Figure -2.45.9 1.35 1.8 2.25 FREQUENCY, GHz 6 4 NOISE FIGURE, db Figure 8. Measured Results for Gain and Noise Figure. INPUT AND OUTPUT RETURN LOSS, db -2-4 -6-8 -1-12 -14-16.45.9 1.35 1.8 2.25 Figure 9. Measured Results for Input and Output Return Loss. FREQUENCY, GHz Input RL Output RL 7
References 1. Application Note AN-1222: A Low Noise High Intercept Point Amplifier for 193 to 199 MHz using the ATF- 54143 PHEMT A.J. Ward. 2. Stephan Maas, Nonlinear Microwave Circuits, IEEE Press, New York, 1997. 3. W. R. Curtice, A MESFET model for use in the design of GaAs integrated circuits, IEEE Trans Microwave Theory Tech, vol. MTT-28, pp. 448-456, May 198. 4. Application Note AN-1281: A High IIP3 Balanced Low Noise Amplifier for Cellular Base Station Applications Using the Avago Technologies Enhancement Mode PHEMT ATF- 54143 Transistor and Anaren Pico Xinger 3 db Hybrid Couplers I.R. Piper/S. Seward/A.J. Ward 5. Application Note AN- 132: Low Noise and High Linearity Applications using the Avago Technologies ATF-531P8 Saul Espino. Avago Technologies Eesof Advanced Design System (ADS) electronic design automation (EDA) software for system, RF, and DSP designers who develop communications products. More information about Avago Technologies EDA software may be found on http://www. Avagotech.com/eesof-eda Performance data for Avago Technologies ATF-531P8 may be found on http://www.avagotech.com/ view/rf For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright 26-21 Avago Technologies, Limited. All rights reserved. 5988-9546EN August 3, 21