STP5NK80Z - STP5NK80ZFP N-CHANNEL 800V - 1.9Ω - 4.3A TO-220/TO-220FP Zener-Protected SuperMESH Power MOSFET

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N-CHANNEL 800V - 1.9Ω - 4.3A TO-220/TO-220FP Zener-Protected SuperMESH Power MOSFET TYPE V DSS R DS(on) I D Pw STP5NK80Z STP5NK80ZFP 800 V 800 V TYPICAL R DS (on) = 1.9 Ω <2.4Ω <2.4Ω 4.3 A 4.3 A EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY 110 W 30 W TO-220 TO-220FP 1 2 3 DESCRIPTION The SuperMESH series is obtained through an extreme optimization of ST s well established stripbased PowerMESH layout. In addition to pushing on-resistance significantly down, special care is taken to eure a very good dv/dt capability for the most demanding applicatio. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh products. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC LIGHTING ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STP5NK80Z P5NK80Z TO-220 TUBE STP5NK80ZFP P5NK80ZFP TO-220FP TUBE April 2004 1/10

ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit ( ) Pulse width limited by safe operating area (1) I SD 4.3A, di/dt 200A/µs, V DD V (BR)DSS,T j T JMAX. (*) Limited only by maximum temperature allowed THERMAL DATA AVALANCHE CHARACTERISTICS STP5NK80Z STP5NK80ZFP V DS Drain-source Voltage (V GS =0) 800 V V DGR Drain-gate Voltage (R GS =20kΩ) 800 V V GS Gate- source Voltage ± 30 V I D Drain Current (continuous) at T C =25 C 4.3 4.3 (*) A I D Drain Current (continuous) at T C = 100 C 2.7 2.7 (*) A I DM ( ) Drain Current (pulsed) 17.2 17.2 (*) A P TOT Total Dissipation at T C =25 C 110 30 W Derating Factor 0.88 0.24 W/ C V ESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5KΩ) 3500 V dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ V ISO Iulation Withstand Voltage (DC) - 2500 V T j T stg Operating Junction Temperature Storage Temperature -55to150-55to150 TO-220 TO-220FP Rthj-case Thermal Resistance Junction-case Max 1.14 4.2 C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 C/W T l Maximum Lead Temperature For Soldering Purpose 300 C Symbol Parameter Max Value Unit I AR Avalanche Current, Repetitive or Not-Repetitive 4.3 A (pulse width limited by T j max) E AS Single Pulse Avalanche Energy (starting T j =25 C, I D =I AR,V DD =50V) 190 mj C C GATE-SOURCE ZENER DIODE Symbol Parameter Test Conditio Min. Typ. Max. Unit BV GSO Gate-Source Breakdown Igs=± 1mA (Open Drain) 30 V Voltage (#) When mounted on minimum Footprint PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device s ESD capability, but also to make them safely absorb possible voltage traients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/10

ELECTRICAL CHARACTERISTICS (TCASE =25 C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Parameter Test Conditio Min. Typ. Max. Unit V (BR)DSS Drain-source I D =1mA,V GS = 0 800 V Breakdown Voltage I DSS I GSS DYNAMIC SWITCHING ON SWITCHING OFF Zero Gate Voltage Drain Current (V GS =0) Gate-body Leakage Current (V DS =0) V DS =MaxRating V DS =MaxRating,T C = 125 C 1 50 V GS = ± 20V ±10 µa V GS(th) Gate Threshold Voltage V DS =V GS,I D = 100µA 3 3.75 4.5 V R DS(on) Static Drain-source On V GS =10V,I D = 2.15 A 1.9 2.4 Ω Resistance Symbol Parameter Test Conditio Min. Typ. Max. Unit g fs (1) Forward Traconductance V DS =15V, I D = 2.15 A 4.25 S C iss C oss C rss C oss eq. (3) Input Capacitance Output Capacitance Reverse Trafer Capacitance Equivalent Output Capacitance V DS =25V,f=1MHz,V GS = 0 910 98 20 V GS =0V,V DS = 0V to 400V 40 pf Symbol Parameter Test Conditio Min. Typ. Max. Unit t d(on) t r Turn-on Delay Time Rise Time V DD =400V,I D =2A R G =4.7ΩV GS =10V (Resistive Load see, Figure 3) 18 25 Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD =640V,I D =4.3A, V GS =10V 32.4 5 18.5 µa µa pf pf pf 45.5 nc nc nc Symbol Parameter Test Conditio Min. Typ. Max. Unit t d(off) t f Turn-off Delay Time Fall Time V DD =400V,I D =2A R G =4.7Ω V GS =10V (Resistive Load see, Figure 3) 45 30 t r(voff) t f t c Off-voltage Rise Time Fall Time Cross-over Time V DD =640V,I D =4.3A, R G =4.7Ω, V GS = 10V (Inductive Load see, Figure 5) 22 10 32 SOURCE DRAIN DIODE Symbol Parameter Test Conditio Min. Typ. Max. Unit I SD Source-drain Current 4.3 A I SDM (2) Source-drain Current (pulsed) 17.2 A V SD (1) ForwardOnVoltage I SD =4.3A,V GS =0 1.6 V t rr Q rr I RRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 4.3 A, di/dt = 100A/µs V DD =40V,T j = 150 C (see test circuit, Figure 5) Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. C oss eq. is defined as a cotant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS. 500 3 12 µc A 3/10

Safe Operating Area For TO-220 Safe Operating Area For TO-220FP Thermal Impedance For TO-220 Thermal Impedance For TO-220FP Output Characteristics Trafer Characteristics 4/10

Traconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variatio Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature 5/10

Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature Maximum Avalanche Energy vs Temperature 6/10

Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 7/10

TO-220 MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 L4 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C F G H2 D A E L2 G1 F1 Dia. L5 L7 L9 F2 L6 L4 P011C 8/10

TO-220FP MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.5 0.045 0.067 F2 1.15 1.5 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6.0385 0.417 L5 2.9 3.6 0.114 0.141 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 H G B D A E L6 L7 L3 G1 F1 F L2 L5 F2 L4 1 2 3 9/10

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no respoibility for the coequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licee is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificatio mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 10/10