April 26, 2018 Wendem Beyene UIUC ECE 546 Statistical Link Modeling Review of Basic Techniques
What is a High-Speed Link? 1011...001 TX Channel RX 1011...001 Clock Clock Three basic building blocks: Transmitter, Receiver, and Channel Channel accurately characterized in frequency domain Transmitter and receiver are circuit blocks and defined in time domain The transmitter and receiver require clock ticks (correlated) 2
Statistical Link Modeling / Analysis Statistical link analysis is not Monte Carlo analysis of high-speed link It is a technique of analytically solving of the signal amplitude probability of high-speed link Thus the method allows the result to be computed in a matter of seconds for inconceivably low BER p(t) C 0 C 1 C -1 C 2 C 3 C 4 C 5 C 6 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 time A convenient tool to explore link architecture and channel variations 3
Key Contributors to Statistical Link Modeling Bryan K. Casper, et. al, An accurate and efficient analysis method for multi-gb/s chip-to-chip signaling scheme, in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June 2002, pp. 54 57. Introduced Peak Distortion Analysis to the community Vladimir Stojanovic, et. al, Modeling and analysis of high speed links, in IEEE Custom Integrated Circuits Conf. Dig. Tech. Papers, Sept 2003, pp. 589 594. introduced improved Jitter, Noise and CDR models Anthony Sanders, Channel Compliance Testing Utilizing Novel Statistical Eye Methodology, Euro DesignCon 2004. Wrote Wendem Beyene StatEye, the first complete link analysis tool for the public: http://www.stateye.org/ 4
Today s High-Speed Links 1011...001 Channel Clock tracking loop vv 1011...001 TX RX Current high-speed links are very complex : transmitter and receiver equalization circuitries and clock recovery and tracking blocks Complex analogy front ends : Support high-modulation, transmitter and receiver implement bandwidth extension techniques Finding optimum timing and equalization setting requires repeated link simulation over long simulation time 5
Circuit Simulation Techniques Developed in late 60 s and released as public domain program in early 1970 Few modification/variants added since then to address new challenges There are frequency and time domain, large and small-signal signal and noise analysis techniques that are well researched and widely used S-parameter analysis for large and small-signal analysis : passive or linearized systems Transient analysis for baseband circuits and startup transient : SPICE and it variants Shooting Newton for strongly nonlinear RF circuits : PLL, oscillators, power convertors Harmonic Balance for nonlinear RF circuits : mixer, filters Envelope analysis for complex modulated RF waveforms 6
Standard Circuit Simulation Techniques 1. Use nodal analysis technique to construct a system of differential equation from the circuit topology 2. Use stable implicit integration methods to convert the differential equation into a sequence of nonlinear algebraic equations 3. Use modified newton methods to solve the algebraic equations by solving a sequence of linear equations 4. Use sparse Gaussian elimination to solve the systems of linear equations generated by the Newton method The Sparse-matrix solution time grows super linearly with the size of the problem 7
Modified Nodal Formulation G 1 C 1 ϕ L =h L (i L ) v 1 v 2 v 3 v 4 The modified nodal analysis matrix (MNA) of the linearized circuit results in 6x6 matrix E + - i E G 2 i D =g D (v D ) i L G 3 q 3 =f C (v C ) Variables : v 1, v 2, v 3, v 4, i E, and i L The asterisked linearized circuit variables are the solution at an iteration point during the analysis and h = t n -t n-1, is the time step 8
Circuit Blocks in High-Speed Links Data in 32:4 Serializer Phase Rotator 4-Tap FIR FIFO CML to CMOS 4:2 Serializer Clock Generator Pre- Driver Output- Driver Rterm & T-coil, Network ESD TX out Channel RX in T-coil & Rterm Network ESD VGA CTLE CTLE Phase Detector Banks Multi-Tap DFE CML to CMOS 2:16 DMUX DFE Weights Phase Rotators Integrator Calibration Logic DFE Adaptation CDR Data out PLL PLL Ref Clock There are more than 100,000 transistors and other components The MNA matrix to be solved at each time point is very large The circuit simulation of a complete link using FAST SPICE can take more than a week to complete over a very short simulation time BER > 10-6 Much faster link simulation technique is a necessity 9 Ref Clock
High-Speed Link Simulation Challenges Interconnect systems consist of a large number of linear (distributed) networks that are accurately characterized in frequency domain Transistor-level circuit simulators are not efficient or adequate to estimate the performances of high-speed links The simulation of large systems with mixed-signal design using nonlinear time-domain simulators is too expensive Different circuit variables are changing at very different rates Large circuit variables can be inactive or latent for interconnect system It is computationally prohibitive to calculate link performance to low BER 10
Channel Frequency or Time-Domain Response Channel characteristics : frequency or time-domain responses Channel including packages as well as on-die termination, tcoil, and parasitic Extract the pulse responses for a given data rate from frequency or time domain responses H(f) h(t) TX Circuit Blocks TX: Rterm, Tcoil, C,... Pkg Channel Pkg RX: Rterm, Tcoil, C,... RX Circuit Blocks H(f) or h(t) Frequency time 11
Passive Sub blocks in a High-Speed Link 1011...001 Channel 1011...001 vv TX RX 12
Channel Frequency and Time-Domain Responses Pulse response is obtained from link frequency and/or timedomain responses of the passive system H(f) p(t) C 0 C 1 h(t) Frequency C -1 C 2 C 3 C 4 C 5 C 6 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 time Cursors, c(t), of pulse response waveform are determined time 13
C -1 C2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 Peak Distortion Analysis 1 C 3 C 6 t 6 C 0 C 1 C -1 C 2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 C 3 C 6 t 6 14
Peak Distortion Analysis 1 PDA can estimate worst-case eye height and data pattern from pulse response Worst-case 1 is summation of a 1 pulse with all negative residual pulse responses (except for C 0 ) Worst-case 0 is summation of a 0 pulse with all positive residual pulse responses (except for C 0 ) The worst case pattern : 1: [-(sign(c 6 ), -(sign(c 5 ), -(sign(c 4 ), -(sign(c 3 ), -(sign(c 2 ),-(sign(c 1 ), 1, -(sign(c -1 )]] 0: [ (sign(c 6 ), (sign(c 5 ), (sign(c 4 ), (sign(c 3 ), (sign(c 2 ), (sign(c 1 ), 1, (sign(c -1 )]] The worst-case eye height at s 1 (t)-s 0 (t) : C 0 C 1 C -1 C 2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 C 6 C 3 t 6 s 1 t = y 1 t + k= k 0 y(t kt) y(t kt)<0 s 0 t = y 0 t + k= k 0 y(t kt) y(t kt)>0 Wendem Beyene 14
Peak Distortion Analysis Algorithm C 0 Divide the pulse response into UI sections τ i = i UI C 1 C -1 C 2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 C 6 C 3 Mark all non-zero cursors 1 Finding the Worst Case 1 Find all the cursors with voltage < 0 at t i and sum them up The worst case high side eye voltage at t 0 = C 0 - (C 3 +C 6 ) For example: The Worst Case Pattern is 10010010 2 Finding the Worst Case 0 Find all the UI s with voltage > 0 at T1 and sum up The worst case low side eye voltage t 0 = C 1 + C 1 +C 2 +C 4 +C 5 The worst case pattern : 01101101 15
Peak Distortion Analysis Algorithm Cont d C 0 Repeat 1 & 2 for t 1 t 2 t N to find the C 1 worst case eye For every sampling time t 0, the worst case patterns C -1 C 2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 are different C 0 C 3 C 6 C 1 Voltage C -1 C 2 C 4 C5 t -1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 Time C 3 C 6 16
Determining ISI PDF of Link from Pulse Response Non zero cursor values, C(t), are determined from pulse response PDF is built by summing the number of bit sequences which produce each amplitude value given C(t) and dividing by the total number of bit sequences p(t) C 0 Probability 0.125 C 1 C -1 C 2 t -1 t 0 t 1 t 2 time ISI (V) 17
0.25 Probability 0.125 Forming ISI PDF p(t) C 0 C 1 C -1 C 2 p(t) t -1 t 0 t 1 t 2 time ISI (V) Probability time ISI (V) 18
ISI pdf of High-Speed Link from Pulse Response Each possible amplitude is determined by convolution of the bit sequence with C(t): with N non-zero cursors, the ISI combination is 2 N ISI PDF can be generated using progressive convolution of ISI Probability Probability = Probability ISI (Voltage) ISI (Voltage) ISI (Voltage) Probability Probability = Probability ISI (Voltage) ISI (Voltage) ISI (Voltage) 0 Probability 1 ISI (Voltage) 19
Voltage Constructing Eye Diagram From The ISI PDF Probability Probability ISI (Voltage) ISI (Voltage) ISI (Voltage) Time 20
Transmitter and receiver Jitter and Noise 2,3 1011...001 TX Channel RX 1011...001 Tx jitter Rx jitter Receiver noise v v Tx Jitter (time) Rx Jitter (time) Rx noise (voltage) The transceiver jitter and noise can be added in the analysis Spectrum and correlation are not considered Transmitter jitter are not enhanced or colored by the channel 21
Voltage Next Steps in Statistical Modeling or Analysis 4 The transmitter adds jitter and nonlinearity to the signal Assume the jitter is independent of the data pattern and channel response Ä v v ISI (voltage) Jitter (time) The receiver adds jitter, noise and nonlinearity to the signal Assume the jitter and noise are independent of the data pattern and channel response time RX aperture 22
Summary of Statistical Channel ISI Modeling 1-4 1. Obtain pulse (bit) response p(t) C 0 C 1 C -1 C 2 2. Compute ISI PDF of passive channel t -1 t 0 t 1 t 2 time 3. Convolve with the transmitter jitter 4. Convolve with the receiver jitter and noise ISI (voltage) Ä v v Jitter (time) 5. Compute BER with RX sampling distribution. 23
Transceiver Nonlinearity in High-Speed Link 1011...001 Vout (Voltage) Vout (Voltage) Vin (Voltage) Vin (Voltage) TX Channel RX 1011...001 Receiver Tx Rx noise jitter jitter High data rate Reduced slew rate (bandwidth limitation) High channel loss More complex transmitter and receiver equalization Low-power signaling Circuit topology Reduced parasitic Technology scaling Reduced supply (Headroom) On-chip AC coupling Circuit blocks to control baseline wandering 24
Typical Transceiver Nonlinearities 7 Linearity assumptions do not hold for current high-speed link analysis Nonlinearities in transmitter and receivers get worst with PVT Receiver nonlinearities significantly affect link performance The impact of nonlinearities in high-speed links can be captured via Volterra series expansion Nonlinearities are approximated by polynomial functions Nonlinearities represented using Hammerstein and Wiener models Probability distribution function (pdf) at the output as the function of pdf at the input 25
A High-Speed Link with Receiver Nonlinearity Consider a high-speed link with receiver nonlinearity y t = g R o x + n T h TCR + n R t where the LTI response : h TCR t = h T t *h C t *h R t 26
Transformation of Random Variable The random variable X with known pdf can be mapped to a random variable Y by function g 27
Hammerstein and Wiener Models LTI System : Let X denote the output of linear system f X X = f Y1 X Äf X2 X Ä f Y3 X f X3 X f Y3 Y Let Y denote the output of nonlinear transmitter Given Y = a 0 X + a 1 X 2 + a 1 X 3, f Y Y = dx dy f X X f X X g X f Y Y ο = 28
Receiver Nonlinearity : PAM4 0-200 -150-100 -50 0 50 100 150 200 Voltage (mv) Probability Density 1.5 1 0.5 Eye diagram from linear receiver 2 2.5 x 10-3 Eye diagram from nonlinear receiver Higher Modulation signaling suffers more from nonlinearity Voltage margin is significantly reduced Optimal reference voltage is shifted 29
Statistical Signal-Flow Based Link Analysis 5,6 Statistical link analysis Assumes linear-time invariant transmitter and receiver Assumes independent random bits : coded bit sequence is too complicated Time-domain response is not available It is not possible to handle time-dependent jitter and noise Impact of channel loss (jitter amplification and jitter coloring)not captured Signal-flow (bit-by-bit, waveform, convolution-based) time-domain analysis Eye diagrams are efficiently calculated from given bit patterns Provide time-domain waveforms and frequency-domain responses (FFT) Provide flexibility to use training and encoded patterns Straight forward to add jitter and noise Need extrapolation to go down to low BER levels (Long simulation time) Computationally still inefficient for low BER 30
Convolution-Based Link Analysis Time-domain jitter and voltage noise can be introduced b i : digital bit sequence, either 1 or 0 and V 0 : output voltage t TX : Transmitter jitter and V TX : Transmitter voltage noise V TX (t) = b i (V 0 + V TX (t+ t TX )) is the jittery and noisy transmitter waveform V RX : Receiver voltage noise b i V TX Tx (t) V CH (t) V Channel : h C (t) h ctle (t) CTLE (t) DFE y(t) 31
Summary Statistical : Public, in-house or commercial tools with widely different capabilities Signal flow : Commercial system simulators, consulting groups and in-house tools Transistor-level : Commercial tools Statistical Signal-Flow Transistor-Level Seconds to minutes minutes to hours days to weeks 32
References 1. Bryan K. Casper, et. al, An accurate and efficient analysis method for multi-gb/s chip-to-chip signaling scheme, in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June 2002, pp. 54 57. 1. 2. Vladimir Stojanovic, et. al, Modeling and analysis of high speed links, in IEEE Custom Integrated Circuits Conf. Dig. Tech. Papers, Sept 2003, pp. 589 594. 3. A Sanders, et. al, Channel Compliance Testing Utilizing Novel Statistical Eye Methodology, DesignCon 2004. 4. G. Balamurugan, et. al, "Modeling and Analysis of High-Speed I/O Links," IEEE Transactions on Advanced Packaging, vol. 32, no. 2, 237 247, 2009 5. G. Balamurugan, et. al, Modeling and mitigation of jitter in multi-gbps source-synchronous I/O links, in Int. Conf. Comput. Design, Oct. 2003, pp. 254 260. 6. N. Blitvic, et. al, Channel coding for high-speed links: A systematic look at code performance and system simulation, IEEE Transactions on Advanced Packaging, 2009 7. W. Beyene, et. al, Statistical simulation of high-speed links with transmitter and receiver nonlinearities, in IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, Oct. 2014, pp 35-38. 8. J. Vlach and K. Singhal. Computer Methods for Circuit Analysis and Design. Van Nostrand Reinhold Co., New York, NY, second edition, 1994. 33
Questions & Discussion