High-Voltage Power MOSFET & IGBT Driver Driver Characteristics Parameter Rating Units V OFFSET 6 V I O +/- (Source/Sink) 25/5 ma V th 25 mv t ON / t OFF (Typical) 1 ns Features Floating Channel Designed for Bootstrap Operation up to 6V Tolerant to Negative Transient Voltages; dv/dt Immune Undervoltage Lockout 3.3V, 5V, and 12V Input Logic Compatible Open-Drain FAULT Indicator Pin Shows Over-Current Shutdown Output in Phase with the Input Applications High-Speed Gate Driver Motor Drive Inverter Description The is a high-voltage, high-speed power MOSFET and IGBT driver. High-voltage level-shift circuitry enables this device to operate up to 6V. IXYS Integrated Circuits Division s proprietary common-mode design techniques provide stable operation in high dv/dt noise environments. An on-board comparator can be used to detect an over-current condition in the driven MOSFET or IGBT device, and then shut down drive to that device. An open-drain output, FAULT, indicates that an over-current shutdown has occurred. The gate driver output typically can source 25mA and sink 5mA, which is suitable for fluorescent lamp ballast, motor control, SMPS, and other converter drive topologies. The is provided in 8-pin DIP and 8-pin SOIC packages, and is available in Tape & Reel versions. See ordering information below. Ordering Information Pb e3 Part G Description 8-Pin DIP (5/Tube) N 8-Pin SOIC (1/Tube) NTR 8-Pin SOIC (2/Reel) Block Diagram Low Side High Side Undervoltage Lockout V B IN Data Latch Enable Transmitter Low-High Level Shift Receiver Buffer V S FAULT Blanking Signal Delay COM Q R S Receiver High-Low Level Shift Transmitter Enable Data Latch Comparator + _ DS--R3 www.ixysic.com 1
1. Specifications.............................................................................................. 3 1.1 Package Pinout......................................................................................... 3 1.2 Pin Description.......................................................................................... 3 1.3 Absolute Maximum Ratings................................................................................ 3 1.4 Recommended Operating Conditions........................................................................ 4 1.5 General Conditions...................................................................................... 4 1.6 Electrical Characteristics.................................................................................. 5 1.7 Timing Characteristics.................................................................................... 6 2. Performance Data........................................................................................... 8 3. Manufacturing Information................................................................................... 11 3.1 Moisture Sensitivity..................................................................................... 11 3.2 ESD Sensitivity........................................................................................ 11 3.3 Reflow Profile.......................................................................................... 11 3.4 Board Wash........................................................................................... 11 3.5 Mechanical Dimensions.................................................................................. 12 2 www.ixysic.com R3
1 Specifications 1.1 Package Pinout 1.2 Pin Description Pin# Name Description IN FAULT COM 1 8 2 7 3 6 4 5 V B V S 1 Logic Supply Voltage 2 IN Logic Input 3 FAULT Fault Indicator Output 4 COM Logic Ground 5 V S High Side Return 6 Comparator Input, Over-Current Detect 7 High Side Gate Drive Output 8 V B High Side Supply Voltage 1.3 Absolute Maximum Ratings Unless otherwise specified, ratings are provided at T A =25 C and all bias levels are with respect to COM. Parameter Symbol Minimum Maximum Units Logic Supply Voltage -.3 15 High Side Floating Supply Voltage V B -.3 625 High Side Floating Offset Voltage V S V B -12 V B +.3 Logic Input Voltage V IN -.3 +.3 High Side Floating Output Voltage V V S -.3 V B +.3 Current Sense Voltage V V S -.3 V B +.3 FAULT Output Voltage V FLT -.3 +.3 Allowable Offset Supply Voltage Transient dv S /dt - 5 V/ns Package Power Dissipation 8-Lead DIP - 1 P D 8-Lead SOIC -.625 Junction Temperature T J - 15 C Storage Temperature T S -55 15 Absolute maximum electrical ratings are at 25 C Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. V W R3 www.ixysic.com 3
1.4 Recommended Operating Conditions Parameter Symbol Minimum Maximum Units Logic Supply 9 12 High Side Floating Supply V B V S +9 V S +12 High Side Offset Voltage V S -5 6 Logic Input Voltage V IN V High Side Floating Output V V S V B Current Sense Signal Voltage V V S V S +5 FAULT Output Voltage V FLT Ambient Temperature T A -4 +125 C 1.5 General Conditions Typical values are characteristic of the device at 25 C and are the result of engineering evaluations. They are provided for information purposes only and are not part of the manufacturing testing requirements. Unless otherwise noted, all electrical specifications are listed for T A =25 C. 4 www.ixysic.com R3
1.6 Electrical Characteristics Unless otherwise specified, the test conditions are: =12V;, IN, FAULT, and Leakage voltages and currents are referenced to COM; V B,, and voltages and currents are referenced to V S. 1.6.1 Power Supply Specifications Parameter Conditions Symbol Minimum Typical Maximum Units Quiescent Supply Current V IN =V I QCC - 28 4 A Quiescent V BS Supply Current V IN =V I QBS - 5 1 V BS UVLO Positive-Going Threshold - V BS_UV+ 6.8 7.7 8.6 V V BS UVLO Negative-Going Threshold - V BS_UV- 6.3 7.2 8.1 Offset Supply Leakage Current V B =V S =6V I LKG - - 2 A 1.6.2 Gate Drive and Shutdown Specifications Parameter Conditions Symbol Minimum Typical Maximum Units High Level Output Voltage, V B -V I =A V OH - - 1 mv Low Level Output Voltage, V I =A V OL - - 1 Output Short Circuit Pulsed Current V =V, V IN =5V, PW<1 s, I R GATE =2 * (see Figure 1) + -2-25 - ma V =12V, V IN =V, PW<1 s, I R GATE =2 * (see Figure 1) - 42 5 - Input, Positive-Going Threshold =9V to 12V V _TH+ 18 26 32 mv High Bias Current V =3V I + - - 1 V =V I - - - -1 * R GATE value must be 2 or greater. 1.6.3 Logic I/O Specifications Parameter Conditions Symbol Minimum Typical Maximum Units A Logic 1 Input Voltage =9V to 12V V IH 3. - - Logic Input Voltage =9V to 12V V IL - -.8 Logic 1 Input Bias Current V IN =5V I IN+ - 2.6 15 Logic Input Bias Current V IN =V I IN- - - -1 V A FAULT On-Resistance - FLT, R ON - 72-1.6.4 Thermal Specifications Parameter Conditions Symbol Minimum Typical Maximum Units Thermal Resistance, Junction to Ambient: 8-Lead DIP - - 125 - R JA 8-Lead SOIC - - 2 C/W R3 www.ixysic.com 5
1.7 Timing Characteristics Parameter Conditions Symbol Minimum Typical Maximum Units Turn-On Propagation Delay t on - 1 2 Turn-Off Propagation Delay t off - 73 2 Turn-On Rise Time =12V, t r - 23 13 Turn-Off Fall Time C L =1nF, t f - 2 65 Start-Up Blanking Delay T A =25 C t blk 55 766 95 ns Shutdown Propagation Delay t - 22 36 to FLT Propagation Delay t FLT - 236 51 Figure 1. Typical Connection Diagram IN FAULT 1 2 IN 3 FAULT V B V S 8 7 6 4 COM 5 R GATE 6 www.ixysic.com R3
1.7.1 I/O Timing Diagram 1.7.4 Shutdown Waveforms IN V _TH+ FAULT t cs 9% 1.7.2 Switching Time Waveforms IN 5% 1.7.5 to FLT Waveforms 9% V _TH+ 1% t on t r t off t f FAULT t flt 9% 1.7.3 Startup Blanking Time Waveforms 5% IN t blk 9% FAULT R3 www.ixysic.com 7
2 Performance Data 25 Quiescent Supply Current I QCC vs. Voltage 5 Quiescent V BS Supply Current I QBS vs. Voltage 1 VBS Undervoltage Lockout Positive-Going Threshold UVLO+ I QCC (μa) 2 15 1 5 I QBS (μa) 4 3 2 1 Threshold UVLO+ (V) 8 6 4 2 9. 9.5 1. 1.5 11. 11.5 12. 9. 9.5 1. 1.5 11. 11.5 12. V BS -5-25 25 5 75 1 125 3 Quiescent Supply Current I QCC 5 Quiescent V BS Supply Current I QBS 1 VBS Undervoltage Lockout Negative-Going Threshold UVLOvs. Temperature I QCC (μa) 25 2 15 1 5 I QBS (μa) 4 3 2 1 Threshold UVLO- (V) 8 6 4 2-5 -25 25 5 75 1 125-5 -25 25 5 75 1 125-5 -25 25 5 75 1 125 Input Voltage (V) 3. 2.5 2. 1.5 1..5 Logic "1" Input Threshold Voltage vs.. 9. 9.5 1. 1.5 11. 11.5 12. Supply (V) Input Voltage (V) 3. 2.5 2. 1.5 1..5 Logic "" Input Threshold Voltage vs.. 9. 9.5 1. 1.5 11. 11.5 12. Threshold (mv) 35 3 25 2 15 1 5 Input Positive Going Threshold vs. 9. 9.5 1. 1.5 11. 11.5 12. Input Voltage (V) 3. 2.5 2. 1.5 1..5 Logic "1" Input Threshold Voltage. -5-25 25 5 75 1 125 Input Voltage (V) 3. 2.5 2. 1.5 1..5 Logic "" Input Threshold Voltage. -5-25 25 5 75 1 125 Threshold (mv) 35 3 25 2 15 1 5 Input Positive Going Threshold -5-25 25 5 75 1 125 8 www.ixysic.com R3
Input Current (μa) 5 4 3 2 1 Logic "1" Input Current I IN + vs. Voltage 9. 9.5 1. 1.5 11. 11.5 12. Voltage (V) Turn-On Delay Time (ns) 2 175 15 125 1 75 5 25 Turn-On Time vs. Supply Voltage 9. 9.5 1. 1.5 11. 11.5 12. V BIAS Rise Time (ns) 2 175 15 125 1 75 5 25 Turn-On Rise Time vs. Supply Voltage 9. 9.5 1. 1.5 11. 11.5 12. Input Current (μa) 4. 3.5 3. 2.5 2. 1.5 1..5 Logic "1" Input Current I IN +. -5-25 25 5 75 1 125 Turn-On Time (ns) 2 175 15 125 1 75 5 25 Turn-On Time -5-25 25 5 75 1 125 Rise Time (ns) 2 15 1 5 Turn-On Rise Time -5-25 25 5 75 1 125 Input Current (μa) 1..5. -.5 Logic "" Input Current I IN - vs. Voltage -1. 9. 9.5 1. 1.5 11. 11.5 12. Voltage (V) Turn-Off Delay Time (ns) 2 175 15 125 1 75 5 25 Turn-Off Time vs. Supply Voltage 9. 9.5 1. 1.5 11. 11.5 12. V BIAS Turn-Off Fall Time (ns) 25 2 15 1 5 Turn-Off Fall Time vs. Supply Voltage 9. 9.5 1. 1.5 11. 11.5 12. Input Current (μa) 1..5. -.5 Logic "" Input Current I IN - -1. -5-25 25 5 75 1 125 Turn-Off Delay Time (ns) Turn-Off Time 2 175 15 125 1 75 5 25-5 -25 25 5 75 1 125 Turn-Off Fall Time (ns) 5 4 3 2 1 Turn-Off Fall Time -5-25 25 5 75 1 125 R3 www.ixysic.com 9
Output Voltage (mv) High-Level Output Voltage V OH (V B -V ) 1 9 8 7 6 5 4 3 2 1-1 -5-25 25 5 75 1 125 Output Source Current (ma) 3 25 2 15 1 5 Output Source Current vs. Voltage =V BIAS, V IN =5V, PW 1μs) Ref. Fig. 1: R GATE =2Ω 1. 1.5 11. 11.5 12. V BIAS Voltage (V) Output Sink Current (ma) 6 5 4 3 2 1 Output Sink Current vs. V Bias Voltage =V BIAS, V IN =V, PW 1μs) Ref. Fig. 1: R GATE =2Ω 1. 1.5 11. 11.5 12. V BIAS Voltage (V) Output Voltage (mv) 1 9 8 7 6 5 4 3 2 1-1 Low-Level Output Voltage V OL -5-25 25 5 75 1 125 Output Source Current (ma) 35 3 25 2 15 1 5 Output Source Current =12V, V IN =5V, PW 1μs) Ref. Fig. 1: R GATE =2Ω -5-25 25 5 75 1 125 Output Sink Current (ma) 6 5 4 3 2 1 Output Sink Current =12V, V IN =V, PW 1μs) Ref. Fig. 1: R GATE =2Ω -5-25 25 5 75 1 125 Delay (ns) 7 6 5 4 3 2 1 Start-Up Blanking Delay vs. Input Voltage 9. 9.5 1. 1.5 11. 11.5 12. Input Voltage (V) Delay (ns) 25 2 15 1 5 Shutdown Propagation Delay vs. Input Voltage 9. 9.5 1. 1.5 11. 11.5 12. Input Voltage (V) Delay (ns) 35 3 25 2 15 1 5 to FLT Propagation Delay vs. Supply Voltage 9. 9.5 1. 1.5 11. 11.5 12. Delay (ns) 8 7 6 5 4 3 2 1 Start-Up Blanking Delay -5-25 25 5 75 1 125 Delay (ns) 3 25 2 15 1 5 Shutdown Propogation Delay -5-25 25 5 75 1 125 Delay (ns) 35 3 25 2 15 1 5 to FLT Propagation Delay -5-25 25 5 75 1 125 1 www.ixysic.com R3
3 Manufacturing Information 3.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-2, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-33. Device Moisture Sensitivity Level (MSL) Rating G / N MSL 1 3.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 3.3 Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-2 must be observed. Device G N Maximum Temperature x Time 25 C for 3 seconds 26 C for 3 seconds 3.4 Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used. Pb e3 R3 www.ixysic.com 11
3.5 Mechanical Dimensions 3.5.1 8-Pin DIP Through-Hole Package 2.54 ±.127 (.1 ±.5) 6.35 ±.127 (.25 ±.5) Pin 1.457 ±.76 (.18 ±.3) 4.64 TYP (.16) 9.652 ±.381 (.38 ±.15) 3.32 ±.51 (.13 ±.2) 7.62 ±.254 (.3 ±.1) 9.144 ±.58 (.36 ±.2) 7.239 TYP. (.285).254 ±.127 (.1 ±.5) 8-.8 DIA. (8-.31 DIA.) 6.35 ±.127 (.25 ±.5) 7.62 ±.127 (.3 ±.5) PCB Hole Pattern 2.54 ±.127 (.1 ±.5) 7.62 ±.127 (.3 ±.5).813 ±.12 (.32 ±.4) Dimensions mm (inches) 3.5.2 8-Pin SOIC Package Pin 8 5.994 ±.254 (.236 ±.1) 1.27 REF (.5) 3.937 ±.254 (.155 ±.1).762 ±.254 (.3 ±.1) PCB Land Pattern.6 (.24) Pin 1.46 ±.76 (.16 ±.3) 5.4 (.213) 1.55 (.61) 4.928 ±.254 (.194 ±.1).559 ±.254 (.22 ±.1) 1.346 ±.76 (.53 ±.3).51 MIN -.254 MAX (.2 MIN -.1 MAX) 1.27 (.5) Dimensions mm (inches) 12 www.ixysic.com R3
3.5.3 Tape & Reel Packaging for 8-Pin SOIC Package 33.2 DIA. (13. DIA.) Top Cover Tape Thickness.12 MAX. (.4 MAX.) B =5.3 (.29) W=12. (.472) K = 2.1 (.83) A =6.5 (.256) P=8. (.315) Embossed Carrier User Direction of Feed Dimensions mm (inches) Embossment NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 For additional information please visit our website at: www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS--R3 Copyright 212, IXYS Integrated Circuits Division All rights reserved. Printed in USA. 12/19/212 R3 www.ixysic.com 13