Summary Last Lecture

EE47 Lecture 5 Pipelined ADCs (continued) How many bits per stage? Algorithmic ADCs utilizing pipeline structure Advanced background calibration techniques Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 1 Summary Last Lecture Pipelined ADCs (continued) Effect gain stage, sub-dac non-idealities on overall ADC performance Digital calibration (continued) Correction for inter-stage gain nonlinearity Implementation Practical circuits Combining the digital bits Stage implementation Circuits Noise budgeting EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page

How Many Bits Per Stage? Many possible architectures E.g. B 1eff =3, B eff =1,... vs. B 1eff =1, B eff =1, B 3eff =1,... Complex optimization problem, fortunately optimum tends to be shallow... Qualitative answer: Maximum speed for given technology Use small resolution-per-stage (large feedback factor) Maximum power efficiency for fixed, "low" speed Try higher resolution stages Can help alleviate matching & noise requirements in stages following the 1 st stage Ref: Singer VLSI 96, Yang, JSSC 1/01 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 3 14 & 1-Bit State-of-the-Art Implementations Reference Bits Architecture SNR/SFDR Speed Power Yang (JSSC 1/001) 0.35μ/3V 14 3-1-1-1-1-1-1-1-1-3 ~73dB/88dB 75MS/s 340mW Loloee (ESSIRC 00) 0.18μ/3V 1 1-1-1-1-1-1-1-1-1-1- ~66dB/75dB 80MS/s 60mW EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 4

10 & 8-Bit State-of-the-Art Implementations Reference Bits Architecture SNR/SFDR Speed Power Yoshioko et al (ISSCC 005) 0.18μ/1.8V 10 1.5bit/stage ~55dB/66dB 15MS/s 40mW Kim et al (ISSCC 005) 0.18μ/1.8V 8.8 -.8-4 ~48dB/56dB 00MS/s 30mW EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 5 Algorithmic ADC Digital Output start of conversion Shift Register & Correction Logic Residue V IN T/H sub-adc (1.6 Bit) DAC B Essentially same as pipeline, but a single stage is reused for all partial conversions For overall B overall bits need B overall /B stage clock cycles per conversion Small area, slow EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 6

Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters Slow, but accurate ADC operates in parallel with pipelined (main) ADC Slow ADC samples input signal at a lower sampling rate (f s /n) Difference between corresponding samples for two ADCs (e) used to correct fast ADC digital output via an adaptive digital filter (ADF) based on minimizing the Least-Mean-Squared error Ref: Y. Chiu, et al, Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters, IEEE TRANS. CAS, VOL. 51, NO. 1, JANUARY 004 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 7 Example: "A 1-bit 0-MS/s pipelined analog-to-digital converter with nested digital background calibration" Pipelined ADC operates at 0Ms/s @ has 1.5bit/stage Slow ADC Algorithmic type operating at 0Ms/3=65ks/s Digital correction accounts for bit redundancy Digital error estimator minimizes the mean-squared-error Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 1-bit 0-Msample/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 004 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 8

Algorithmic ADC Used for Calibration of Pipelined ADC (continued from previous page) Uses replica of pipelined ADC stage Requires extra SHA in front to hold residue Undergoes a calibration cycle periodically prior to being used to calibrate pipelined ADC Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 1-bit 0-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 004 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 9 1-bit 0-MS/s Pipelined ADC with Digital Background Calibration Sampling capacitors scaled: Input SHA: 6pF Pipelined ADC: pf,0.9,0.4,0., 0.1,0.1 Algorithmic ADC: 0.pF Chip area: 13.mm Area of Algorithmic ADC <0% Does not include digital calibration circuitry estimated ~1.7mm Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 1-bit 0-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 004 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 10

Measurement Results 1-bit 0-MS/s Pipelined ADC with Digital Background Calibration Without Calibration INL <4.LSB With Calibration INL <0.5LSB Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 1-bit 0-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 004 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 11 Measurement Results 1-bit 0-MS/s Pipelined ADC with Digital Background Calibration Nyquist rate Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 1-bit 0-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 004 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 1

Measurement Results 1-bit 0-MS/s Pipelined ADC with Digital Background Calibration Does not include digital calibration circuitry estimated ~1.7mm Alg. ADC SNDR dominated by noise Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 1-bit 0-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp. 1799-1808, Nov. 004 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 13 Oversampled ADCs EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 14

Analog-to-Digital Converters Two categories: Nyquist rate ADCs f sig max ~ 0.5xf sampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to max. 1-14bits Oversampled ADCs f sig max << 0.5xf sampling Maximum possible signal bandwidth lower compared to nyquist Maximum achievable resolution high (18 to 0bits!) EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 15 The Case for Oversampling Nyquist sampling: Signal f s B Freq narrow transition AA-Filter f s >B +δ Sampler Nyquist ADC DSP Oversampling: Signal f s >> f N?? B Freq wide transition AA-Filter f s = Mf N Sampler Oversampled ADC DSP Nyquist rate f N = B Oversampling rate M = f s /f N >> 1 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 16

Nyquist v.s. Oversampled Converters Antialiasing X(f) Input Signal f B frequency Nyquist Sampling f B f s f S ~f B Anti-aliasing Filter f s Oversampling frequency f B f S >> f B f s frequency EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 17 Oversampling Benefits No stringent requirements imposed on analog building blocks Takes advantage of the availability of low cost, low power digital filtering Relaxed transition band requirements for analog anti-aliasing filters Reduced baseband quantization noise power Allows trading speed for resolution EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 18

ADC Converters Baseband Noise For a quantizer with step size Δ and sampling rate f s : Quantization noise power distributed uniformly across Nyquist bandwidth ( f s /) N e (f) N B -f B f s / -f s / f B Power spectral density: e Δ 1 N(f) e = = fs 1 fs Noise is distributed over the Nyquist band f s / to f s / EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 19 Oversampled Converters Baseband Noise fb fb Δ 1 SB = N e( f )df = df fb fb 1 fs N e (f) Δ fb = 1 f N B s where for fb = f s/ Δ SB0 = -f s / -f B f B f s / 1 fb SB0 SB = SB0 = f s M fs where M = = oversampling ratio f B EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 0

B Oversampled Converters Baseband Noise fb SB0 SB = SB0 = f s M fs where M = = oversampling ratio f X increase in M 3dB reduction in S B ½ bit increase in resolution/octave oversampling To increase the improvement in resolution: Embed quantizer in a feedback loop Noise shaping (sigma delta modulation) EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 1 Pulse-Count Modulation V in (kt) Nyquist ADC 0 1 t/t V in (kt) Oversampled ADC, M = 8 0 1 t/t Mean of pulse-count signal approximates analog input! EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page

Magnitude Pulse-Count Spectrum f Signal: low frequencies, f < B << f s Quantization error: high frequency, B f s / Separate with low-pass filter! EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 3 Oversampled ADC Predictive Coding v IN + _ ADC To Digital Filter D OUT Predictor Quantize the difference signal rather than the signal itself Smaller input to ADC Buy dynamic range Only works if combined with oversampling 1-Bit digital output Digital filter computes average N-Bit output EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 4

Oversampled ADC Signal B Freq wide transition Analog AA-Filter f s = Mf N Sampler E.g. Pulse-Count Modulator Modulator 1-Bit Digital f s1 = M f N Decimator narrow transition Digital AA-Filter N-Bit Digital f s = f N + δ DSP Decimator: Digital (low-pass) filter Removes quantization error for f > B Provides anti-alias filtering for DSP Narrow transition band, high-order 1-Bit input, N-Bit output (essentially computes average ) EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 5 Modulator (AFE) Objectives: Convert analog input to 1-Bit pulse density stream Move quantization error to high frequencies f >>B Operates at high frequency f s >> f N M = 8 56 (typical).104 Since modulator operated at high frequencies need to keep circuitry simple ΣΔ = ΔΣ Modulator EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 6

Sigma- Delta Modulators Analog 1-Bit ΣΔ modulators convert a continuous time analog input v IN into a 1-Bit sequence D OUT f s V IN + _ H(z) D OUT DAC Loop filter 1b Quantizer (comparator) EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 7 Sigma-Delta Modulators The loop filter H can be either switched-capacitor or continuous time Switched-capacitor filters are easier to implement + frequency characteristics scale with clock rate Continuous time filters provide anti-aliasing protection Loop filter can also be realized with passive LC s at very high frequencies f s V IN + _ H(z) D OUT DAC EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 8

Oversampling A/D Conversion f s f s /M Input Signal Bandwidth B=f s /M Oversampling Modulator (AFE) 1-bit @ f s Decimation Filter n-bit @ f s /M f s = sampling rate M= oversampling ratio Analog front-end oversampled noise-shaping modulator Converts original signal to a 1-bit digital output at the high rate of (MXB) Digital back-end digital filter (decimation) Removes out-of-band quantization noise Provides anti-aliasing to allow re-sampling @ lower sampling rate EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 9 1 st Order ΣΔ Modulator In a 1 st order modulator, simplest loop filter an integrator H(z) = z -1 1 z -1 V IN + _ D OUT DAC EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 30

1 st Order ΣΔ Modulator Switched-capacitor implementation V IN φ 1 φ φ - + 1,0 D OUT +Δ/ -Δ/ Full-scale input range Δ Note that Δ here is different from Nyquist rate ADC Δ (1LSB) EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 31 1 st Order ΔΣ Modulator V IN -Δ/ V IN +Δ/ + _ D OUT -Δ/ or +Δ/ DAC Properties of the 1 st order modulator: Maximum analog input range is equal to the DAC reference The average value of D OUT must equal the average value of V IN +1 s (or 1 s) density in D OUT is an inherently monotonic function of V IN To 1 st order, linearity is not dependent on component matching Alternative multi-bit DAC (and ADCs) solutions reduce the quantization error but loose this inherent monotonicity & relaxed matching requirements EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 3

Analog input -Δ/ V in +Δ/ 1 st Order ΣΔ Modulator Sine Wave Tally of quantization error 1 X z -1-1 1-z Integrator Q Comparator 1-Bit quantizer 3 Y 1-Bit digital output stream, -1, +1 Instantaneous quantization error Implicit 1-Bit DAC +Δ/, -Δ/ (Δ = ) M chosen to be 8 (low) to ease observability EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 33 1 st Order Modulator Signals 1.5 1 1st Order Sigma-Delta X Q Y X analog input Q tally of q-error Y digital/dac output Amplitude 0.5 0-0.5 Mean of Y approximates X That is exactly what the digital filter does -1-1.5 0 10 0 30 40 50 60 Time [ t/t ] T = 1/f s = 1/ (M f N ) EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 34

ΣΔ Modulator Characteristics Inherently linear for 1-Bit DAC Quantization noise and thermal noise (KT/C) distributed over f s / to +f s / Total noise within signal bandwidth reduced by 1/M Required capacitor sizes x1/m compared to nyquist rate ADCs Very high SQNR achievable (> 0 Bits!) To first order, quantization error independent of component matching Limited to moderate & low speed EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 35 Output Spectrum Amplitude [ dbwn ] 30 0 10 0-10 -0-30 -40 Input -50 0 0.1 0. 0.3 0.4 0.5 Frequency [ f /f s ] Definitely not white! Skewed towards higher frequencies Notice the distinct tones dbwn (db White Noise) scale sets the 0dB line at the noise per bin of a random -1, +1 sequence EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 36

Quantization Noise Analysis Integrator Quantization Error e(kt) x(kt) Σ 1 z H( z) = 1 z 1 Σ Quantizer Model y(kt) Sigma-Delta modulators are nonlinear systems with memory difficult to analyze directly Representing the quantizer as an additive noise source linearizes the system EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 37 Signal Transfer Function 1 z H( z) = 1 z ω0 H( jω ) = jω 1 x(kt) Σ - Integrator H(z) y(kt) Signal transfer function low pass function: 1 HSig ( jω ) = 1 + s ω0 Y( z) H( z) 1 HSig ( z) = = = z X( z) 1 + H( z) Delay Magnitude f 0 Frequency EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 38

v i Σ - v i Σ - ω 0 jω v f n f 0 Noise Transfer Function Qualitative Analysis ω0 jω v n v o v o v eq = f f 0 eq vn v = f f 0 eq vn v Σ v i - ω0 jω v o f 0 Frequency Input referred-noise zero @ DC (s-plane) EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 39 STF and NTF Integrator Quantization Error e(kt) x(kt) Σ 1 1 z H( z) = 1 z Σ Quantizer Model y(kt) Signal transfer function: Y( z) H( z) 1 STF = = = z X( z) 1 + H( z) Delay Noise transfer function: Y ( z) 1 NTF = = = 1 z E( z) 1+ H ( z) 1 Differentiator EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 40

Noise Transfer Function Y() z 1 1 jωt NTF = = = 1 z set z = e Ez () 1 + Hz () jωt/ jωt/ jωt jωt/ e e NTF( jω) = (1 e )=e jωt/ = e jsin T/ jωt/ / ( ω ) jπ ( ω ) = e e sin T/ j( ωt π) / = sin ( ωt/) e where T = 1/ fs Thus: ( ω ) ( ) NTF( f )=sin T / =sin π f / fs Ny( f) = NTF( f) Ne( f) EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 41 First Order ΣΔ Modulator Noise Transfer Characteristics Noise Shaping Function Low-pass Digital Filter N ( f) = NTF( f) N ( f) y ( π ) = 4sin f / f N ( f) First-Order Noise Shaping s e e f B f N f s / frequency Key Point: Most of quantization noise pushed out of frequency band of interest EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 4

First Order ΣΔ Modulator Simulated Noise Transfer Characteristic Amplitude [ dbwn ] 0 10 0-10 -0-30 Signal Simulated output spectrum Computed NTF ( π ) N ( f ) = 4 sin f / f y s Confirms assumption of quantization noise being white at insertion point -40 0 0.1 0. 0.3 0.4 0.5 Frequency [f /f s ] EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 43 Quantizer Error For quantizers with many bits Δ ( kt ) = 1 Let s use the same expression for the 1-Bit case Use simulation to verify validity e Experience: Often sufficiently accurate to be useful, with enough exceptions to be very careful EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 44

First Order ΣΔ Modulator In-Band Quantization Noise 1 ( ) = 1 z ( ) ( π ) NTF z s B Y = Q B NTF f = 4 sin f / f for M >> 1 fs M fs M ( ) ( ) S S f NTF z df 1 Δ f 1 s z= e ( sinπ ft ) π jft df S Y π 1 Δ 3 3 M 1 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 45 Dynamic Range full-scale signal power SX DR = 10log 10log inband noise power = SY S X Y 1 Δ = sinusoidal input, STF = 1 π 1 Δ SY = 3 3 M 1 SX 9 3 = M S π 9 3 9 DR = 10log M = 10log + 30log M π π M DR 16 33 db 3 4 db 104 87 db DR = 3. 4dB ++ 30logM X increase in M 9dB (1.5-Bit) increase in dynamic range EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 46

Oversampling and Noise Shaping ΣΔ modulators have interesting characteristics Unity gain for input signal V IN Large in-band attenuation of quantization noise injected at quantizer input Performance significantly better than 1-Bit noise performance possible for frequencies << f s Increase in oversampling (M = f s /f N >> 1) improves SQNR considerably 1 st order ΣΔ: DR increases 9dB for each doubling of M To first order, SQNR independent of circuit complexity and accuracy Analysis assumes that the quantizer noise is white Not true in practice, especially for low-order modulators Practical modulators suffer from other noise sources also (e.g. thermal noise) EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 47 DC Input DC input A = 1/11 Amplitude [ dbwn ] 0 0-0 -40 0 0.1 0. 0.3 0.4 0.5 Frequency [ f /f s ] Doesn t look like spectrum of DC at all Tones frequency shaped the same as quantization noise More prominent at higher frequencies Seems like periodic quantization noise EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 48

Limit Cycle Oscillation Output First order sigma-delta, DC input 0.4 0. 0-0. -0.4 0 10 0 30 40 50 Time [t/t] DC input 1/11 Periodic sequence: 1 3 4 5 6 7 8 9 10 11 +1 +1-1 +1-1 +1-1 +1-1 +1-1 EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 49 Noise Shaping Function 1 st Order ΣΔ Limit Cycle Oscillation In-band spurious tone with f ~ DC input level First-Order Noise Shaping f B f N Frequency f s / Problem: quantization noise becomes periodic in response to low level DC inputs & could fall within passband of interest! Solution: Use dithering (inject noise-like signal at the input ): randomizes quantization noise - If circuit thermal noise if large enough acts as dither Second order loop EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 50

1 st Order ΣΔ Modulator Linearized Model Analysis ( ) 1 1 Y( z) = z X( z) + 1 z E( z) LPF HPF EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 51 nd Order ΣΔ Modulator Two integrators in series Single quantizer (typically 1-bit) Feedback from output to both integrators Tones less prominent compared to 1st order EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 5

nd Order ΣΔ Modulator Linearized Model Analysis ( ) Recursive drivation: Y = X + E E + E n n 1 n n 1 n ( ) 1 1 1 Using the delay operator z : Y( z) = z X( z) + 1 z E( z) LPF HPF EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 53 NTF z NTF 4 1 ( ) = ( 1 z ) ( f ) = ( π ) nd Order ΣΔ Modulator In-Band Quantization Noise = sin f / f for M >> 1 B Y = Q( ) ( ) z= e B fs M fs M 1 Δ f 1 s 4 π 1 Δ 5 5 M 1 s S S f NTF z df 4 ( sinπ ft) π jft 4 df EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 54

Quantization Noise nd Order ΣΔ Modulator vs 1 st Order Modulator S Y π 1 Δ M 3 3 1 Noise Shaping Function Ideal Low-pass Digital Filter nd -Order Noise Shaping 1 st Order Noise Shaping S Y 4 π 1 Δ 5 5 M 1 f B Frequency f s / EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 55 nd Order ΣΔ Modulator Dynamic Range full-scale signal power SX DR = 10log 10log inband noise power = SY 1 Δ SX = sinusoidal input, STF = 1 4 π 1 Δ SY = 5 5 M 1 SX 15 5 = M 4 SY π 15 5 15 DR = 10log M = 10log + 50log M 4 4 π π DR = 11.1dB + 50log M M DR ( nd ) DR (1 st ) 16 49 db 33dB 3 64 db 4dB 104 139 db 87dB X increase in M 15dB (.5-bit) increase in DR EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 56

nd Order vs 1 st Order ΣΔ Modulator Dynamic Range M nd Order DR 1 st Order DR Resolution Difference 16 49 db (7.8bit) 33dB (5.bit).6 bit 3 64 db (10.3bit) 4dB (6.7bit) 3.6 bit 56 109 db (17.9bit) 68.8dB (11.1bit) 6.8 bit 104 139 db (.8bit) 87dB (14.bit) 8.6 bit Note: For higher oversampling ratios resolution of nd order modulator significantly higher compared to 1 st order EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 57 nd Order ΣΔ Modulator Example Digital audio application Signal bandwidth 0kHz Desired resolution 16-bit 16 bit 98 db Dynamic Range DR = 11.1dB + 50log M M = 153 min M 56= 8 to allow some margin so that thermal noise dominants & provides dithering & also choice of M power of ease of digital filter implementation Sampling rate (x0khz + 5kHz)M = 1MHz (quite reasonable!) EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 58

Limit Cycle Tones in 1 st Order & nd Order ΣΔ Modulator Higher oversampling ratio lower tones nd order much lower tones compared to 1 st 6dB 1 st Order ΣΔ Modulator Xincrease in M decreases the tones by 6dB for 1 st order loop and 1dB for nd order loop 1dB Inband Quantization noise nd Order ΣΔ Modulator Ref: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 6, pp. 618-67, April 1991. R. Gray, Spectral analysis of quantization noise in a single-loop sigma delta modulator with dc input, IEEE Trans. Commun., vol. 37, pp. 588 599, June 1989. EECS 47 Lecture 5 Pipeline & Oversampled ADCs 007 H.K. Page 59