Texas Instruments 1910-612M Digital Micromirror Device (DMD) MEMS Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
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MEMS Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 3 Package Analysis 3.1 Package Overview 3.2 Multi-Layer Ceramic Substrate 4 Process 4.1 General Device Structure 4.2 Dielectrics 4.3 Metallization 4.4 Vias and Contacts 4.5 Transistors and Poly 4.6 Isolation 4.7 Wells and Epi 5 Architectural Analysis 5.1 Micromirror Array (Plan View) 5.2 Cross-Sectional Analysis (Parallel to Metal 1 Row Select Line) 5.3 Cross-Sectional Analysis (Parallel to Metal 2 Data Line) 6 Critical Dimensions 6.1 Package and Die Dimensions 6.2 Horizontal Dimensions 6.3 Vertical Dimensions 7 References 8 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Top Package View 2.1.2 Package Bottom View 2.1.3 Package Side View 2.1.4 Package Tilt View 2.1.5 Plan-View Package X-Ray 2.1.6 Die Photograph 2.1.7 Damaged Mirror Rows 2.1.8 Die Corner A 2.1.9 Die Corner B 2.1.10 Die Corner C 2.1.11 Die Corner D 2.1.12 Die Markings 2.1.13 Bond Pads 2.1.14 Mirror Array Corner 3 Package Analysis 3.1.1 Opened Package 3.1.2 Opened Package Corner 3.1.3 Underside of Package Lid 3.1.4 Package Cross Section Tilt View 3.1.5 Package Cross Section Edge View 3.1.6 Metal Frame And Lid Flange Left Side 3.1.7 Metal Frame And Lid Flange Right Side 3.1.8 Lid Attach To Frame 3.1.9 Frame Attach To Ceramic Substrate 3.1.10 Package Cavity SEM Tilt View 3.1.11 Die Attach 3.2.1 Ceramic Substrate General Structure 3.2.2 Minimum Package Metal 5 3.2.3 Package Via 4 4 Process 4.1.1 Die Annotated with Analysis Locations 4.1.2 General Structure of 1910-612M 4.1.3 Die Thickness 4.1.4 Die Top Edge 4.1.5 Die Seal 4.2.1 Passivation 4.2.2 IMD 2 4.2.3 IMD 1 and PMD
Overview 1-2 4.3.1 Metal 5 TEM 4.3.2 Metal 5 Mirror Edge TEM 4.3.3 Minimum Width Metal 4 4.3.4 Metal 4 Thickness TEM 4.3.5 Minimum Pitch Metal 3 4.3.6 Edge of Metal 3 TEM 4.3.7 Metal 3 Barrier and Adhesion Layers TEM 4.3.8 Metal 2 and Metal 1 Thicknesses 4.3.9 Metal 2 Barrier and Adhesion Layers TEM 4.3.10 Metal 1 Barrier and Adhesion Layers TEM 4.3.11 Minimum Pitch Metal 2 4.3.12 Minimum Pitch Metal 1 4.4.1 Via 4 4.4.2 Via 3s 4.4.3 Via 3 TEM 4.4.4 Tungsten Filled Vias and Contacts 4.4.5 Minimum Pitch Via 1s 4.4.6 Minimum Pitch Contacts to Diffusion 4.4.7 Bottom of Contact to Diffusion TEM 4.4.8 Contact to Poly TEM 4.5.1 Peripheral Logic NMOS Transistor 4.5.2 Peripheral Logic NMOS Transistor TEM 4.5.3 Peripheral Thick Gate Oxide NMOS Transistor 4.5.4 Gate Edge TEM 4.5.5 Peripheral Transistor Thick Gate Oxide TEM 4.5.6 Peripheral Transistor Thin Gate Oxide TEM 4.6.1 Minimum Width Field Oxide 4.6.2 Poly Over Oxide 4.7.1 P-Epi and Substrate SRP 4.7.2 Peripheral P-Well SRP 4.7.3 Peripheral N-Well SRP 4.7.4 Peripheral N-Well and P-Well SCM 5 Architectural Analysis 5.1.1 5T Mirror Cell 5.1.2 Metal 5 Mirrors 5.1.3 Torsion Hinges and Electrodes 5.1.4 Torsion Hinges and Electrodes Tilt View 5.1.5 Metal 3 Mirror Bias Bus and Drive Electrodes 5.1.6 Metal 2 V SS and Data Lines 5.1.7 Metal 1 Select Line, V SS, and V DD Buses 5.1.8 Array at Poly 5.1.9 Poly and Diffusion
Overview 1-3 5.2.1 Mirror Pixel SRAM Annotated with Cross Sections 5.2.2 T1/T5 NMOS Transistor Width (A) 5.2.3 T2/T4 PMOS Pull-Up Transistor Length (B) 5.3.1 Mirror Support Post and Torsion Hinge 5.3.2 T1/T3 NMOS Pull-Down Transistor Length (C) 5.3.3 T2/T4 PMOS Pull-Up Transistor Width (D) 5.3.4 SRAM Transistor Gate Oxide Thickness
Overview 1-4 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 DMD Package Dimensions 4 Process 4.2.1 Dielectric Thicknesses 4.3.1 Metallization Vertical Dimensions 4.3.2 Metallization Horizontal Dimensions 4.4.1 Via and Contact Dimensions 4.5.1 Peripheral Transistor Horizontal Dimensions 4.5.2 Peripheral Transistor and Polycide Vertical Dimensions 5 Architectural Analysis 5.1.1 SRAM Transistor Sizes 6 Critical Dimensions 6.1.1 DMD Package Dimensions 6.2.1 Metallization Horizontal Dimensions 6.2.2 Via and Contact Dimensions 6.2.3 Peripheral Transistor Horizontal Dimensions 6.2.4 SRAM Transistor Sizes 6.3.1 Dielectric Thicknesses 6.3.2 Metallization Vertical Dimensions 6.3.3 Peripheral Transistor and Polycide Vertical Dimensions