Chapter 9. sequential logic technologies In chapter 4, we looked at diverse implementation technologies for combinational logic circuits: random logic, regular logic, programmable logic. The similar variants can be also applied to the implementation of sequential logic systems. Technology Copyright 24, Gaetano Borriello and Randy H. Katz
Combination logic technologies Revisited Standard gates (random logic) gate packages cell libraries Regular logic multiplexers decoders Two-level programmable logic PALs PLAs ROMs Recall that there are three categories of approaches to implement combinational logic circuits. The random logic is also called fixed logic. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 2
Sequential logic implementation Implementation random logic gates and FFs programmable logic devices (PAL with FFs) Design procedure state diagrams state transition table state assignment and encoding next state functions There are two categories in implementing sequential logic circuits. We already covered the first approach. In chapters 7 and 8, we implemented the combination logic for the next state and output by random logic gates mostly. Before going on to the programmable logic devices such as PAL, we look at some special cases of sequential logic circuit implementations. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 3
Median filter FSM Remove single s between two s (output = NS3) Reset I PS PS2 PS3 NS NS2 NS3 X X X X X X The first example is to try to implement the overall system by using a shift register instead of three independent FFs. Whenever the three recent bits are, the output becomes. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 4
Median filter FSM (cont d) Realized using the standard procedure and individual FFs and gates I PS PS2 PS3 NS NS2 NS3 X X X X X X NS = Reset (I) NS2 = Reset ( PS + PS2 I ) NS3 = Reset PS2 O = PS3 If we implement the combinational logic with K-maps, the next states will be represented by the above expressions. If reset is true, all the stored values will be reset to s. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 5
Median filter FSM (cont d) But it looks like a shift register if you look at it right Reset Reset The state diagram of the median filter is so similar to that of a 3-bit shift register. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 6
Median filter FSM (cont d) An alternate implementation with S/R FFs Reset In R S D Q R S D Q R S D Q Out R = Reset S = PS2 I NS = I NS2 = PS NS3 = PS2 O = PS3 CLK The set input (S) does the median filter function by making the next state whenever the input is and PS2 is ( input to state xx) Consider the function of the median filter, if the input string is, the output (or the next state) will be. In other words, if the current input is and PS2 is, then NS, NS2, NS3 will be set to s. This example can be compared to a regular logic implementation of combinational logic systems, shift registers and counters are similar to MUXes and DEMUXes. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 7
homework Example 9.2 Figure 9.4 and 9.5 No need to hand in solutions Technology Copyright 24, Gaetano Borriello and Randy H. Katz 8
Programmable logic building block for sequential logic ROM, PLA/PAL Inputs Combinational Logic Output Function Next State Function Registers Outputs Block Block Diagram for for Synchronous Mealy Mealy Machine State ROM Registers ROM-based Realization Inputs A An- D Dk- Outputs Inputs & Current State form the address An Dk An+m- Dk+m- ROM data bits form the Outputs & Next State State Technology Copyright 24, Gaetano Borriello and Randy H. Katz 9
Implementation using PALs Programmable logic building block for sequential logic macro-cell: FF + logic D-FF two-level logic capability like PAL (e.g., 8 product terms) D Q Q This slide illustrates an implementation with a PAL. An input comes from the bottom left to the AND array. The current state goes back from the bottom right to the AND array. Be aware that there can be multiple blocks. Technology Copyright 24, Gaetano Borriello and Randy H. Katz
Vending machine example (Moore PLD mapping) D D OPEN = reset'(q'n + QN' + QN + QD) = reset'(q + D + QN) = QQ CLK DQ Q N Seq DQ Q D Seq DQ Open Reset Com This is a PAL implementation of the vending machine based on the Moore model. Seq (sequential) IX - Sequential and Logic Com (combinational) are the selector inputs of the MUXes, depicted by trapezoids. Technology X marks indicate enabled Copyright 24, cross-points. Gaetano Borriello and The Randy trapezoid H. Katz is a MUX.
Vending machine (synch. Mealy PLD mapping) OPEN = reset'(qqn' + QN + QD + Q'ND + QN'D) CLK DQ Q N Seq DQ Q D Seq OPEN DQ Open Reset Seq This synch. Mealy machine is derived from Moore machine model. So here, OPEN is reset DD, actually. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 2
22V PAL Combinational logic elements (SoP) Sequential logic elements (D-FFs) Up to outputs Up to FFs Up to 22 inputs Fig. 9.28 This is a specific type of a PAL, which has blocks (or combinational logic elements). There is a tri-state gate on the rightmost column. OE is output enable. If OE is unasserted, the gate is disconnected. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 3
Tri-state buffer 4 types Depending on s, either X or X2 will be connected to output f Depending on whether OE and output are inverted, there are 4 types of tri-state buffers. Z means Technology high-impedance state, Copyright which 24, means Gaetano Borriello the output and Randy is H. disconnected Katz from the input. 4
Tri-state buffer Tri-state buffers are used when multiple circuits all connect to a common bus. Only one circuit at a time is allowed to drive the bus If there is a shared bus, and multiple inputs have different voltage values, there is a conflict about the data value in the bus. That is why a tri-state buffer is widely used in FPGAs. For details, look at section 4.4 Technology Copyright 24, Gaetano Borriello and Randy H. Katz 5
OE 22V PAL Macro Cell Sequential logic element + output/input selection Asynchronous Reset (AR) sets all registers to zero any time. Synchronous Preset (SP) sets all registers to a logic one on the rising edge of the next clock pulse. AR and SP are common to all the registers. This is the inside of a macro cell. The main function of this macrocell is to select the current output of the combinational logic or the stored value, which will be relayed to the output. Also, it can decide that either the stored value or the final output goes back to the combinational logic part. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 6
Example: traffic light controller A busy highway is intersected by a little used farmroad Detectors C sense the presence of cars waiting on the farmroad with no car on farmroad, light remain green in highway direction if vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green these stay green only as long as a farmroad car is detected but never longer than a set interval when these conditions are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green even if farmroad vehicles are waiting, highway gets at least a set interval as green Assume you have an interval timer that generates: a short time pulse (TS) and a long time pulse (TL), in response to a set (ST) signal. TS is to be used for timing yellow lights and TL for green lights Now we will look at a traffic light controller, which controls traffic signals for two crossing roads. Probably, we should give a green light to highway traffic as much as possible. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 7
Example: traffic light controller (cont ) Highway/farm road intersection farm road car sensors highway There are two sensors on the farmroad. When one of them detects a car waiting, it will send a signal to the traffic controller. The signal is denoted by C Technology Copyright 24, Gaetano Borriello and Randy H. Katz 8
Example: traffic light controller (cont ) Tabulation of inputs and outputs inputs description outputs description reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights TS short time interval expired ST start timing a short or long interval TL long time interval expired Tabulation of unique states some light configurations imply others state HG HY FG FY description highway green (farm road red) highway yellow (farm road red) farm road green (highway red) farm road yellow (highway red) There ar many variables. H is Highway and F means Farmroad. G,Y and R are initials of Green, Yellow, and Red. TS for a yellow signal and TL is for a green signal. ST triggers either TS or TL depending on situations. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 9
Example: traffic light controller (cont ) State diagram (TL C)' Reset TL C / ST HG TS / ST TS' HY FY TS' TS / ST FG TL+C' / ST (TL+C')' Suppose the system starts with HG state. If the long interval expires and C is asserted, then it will move to HY state. With this transition, it will enable ST (for short interval). After the short interval, TS will be set to true, which makes the system go to FG state. In FG state, either of two events will trigger the transition to the next state, FY. Two events are long time expiration and no car on the farmroad. Each transition will set the timer, Technology Copyright 24, Gaetano Borriello and Randy H. Katz 2 either long interval or short interval.
Example: traffic light controller (cont ) Generate state table with symbolic states Consider state assignments output encoding similar problem to state assignment (Green =, Yellow =, Red = ) Inputs Present State Next State Outputs C TL TS PS PS NS NS ST H F HG HG Green Red HG HG Green Red HG HY Green Red HY HY Yellow Red HY FG Yellow Red FG FG Red Green FG FY Red Green FG FY Red Green FY FY Red Yellow FY HG Red Yellow SA: HG = HY = FG = FY = SA2: HG = HY = FG = FY = SA3: HG = HY = FG = FY = (one-hot) We will consider three kinds of state assignments (SA, SA2, SA3). Technology Copyright 24, Gaetano Borriello and Randy H. Katz 2
Logic for different state assignments SA NS = C TL' PS PS + TS PS' PS + TS PS PS' + C' PS PS + TL PS PS NS = C TL PS' PS' + C TL' PS PS + PS' PS ST = C TL PS' PS' + TS PS' PS + TS PS PS' + C' PS PS + TL PS PS H = PS H = PS' PS F = PS' F = PS PS SA2 NS = C TL PS' + TS' PS + C' PS' PS NS = TS PS PS' + PS' PS + TS' PS PS SA3 ST = C TL PS' + C' PS' PS + TS PS H = PS F = PS' NS3 = C' PS2 + TL PS2 + TS' PS3 NS = C TL PS + TS' PS H = PS PS' F = PS PS NS2 = TS PS + C TL' PS2 NS = C' PS + TL' PS + TS PS3 ST = C TL PS + TS PS + C' PS2 + TL PS2 + TS PS3 H = PS3 + PS2 H = PS F = PS + PS F = PS3 These are the boolean expressions for each state assignment. Note that in SA3, the product terms for the next state is originally the number of incoming transitions. Technology Copyright 24, Gaetano Borriello and Randy H. Katz 22
Sequential logic implementation summary Models for representing sequential circuits finite state machines and their state diagrams Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure deriving state diagram deriving state transition table assigning codes to states determining next state and output functions implementing combinational logic Implementation technologies random logic + FFs PAL with FFs (programmable logic devices PLDs) Technology Copyright 24, Gaetano Borriello and Randy H. Katz 23