Design nd experimentl vlidtion of multiphse VRM controller S.K. Mzumder nd S.L. Kmisetty Astrct: By comining the concepts of multiple-sliding-surfce nd integrl-vrile-structure controls, one cn develop roust controller for multiphse 9 V VRM, which comprises four prllel DC DC synchronous uck convertors operting t 00 khz. The dvntges of the control scheme re its simplicity in design, good dynmic response, roustness, ility to nullify the us-voltge error nd the error etween the lod currents of the convertor modules, nd ility to reduce the impct of high-frequency dynmics due to prsitics on the closed-loop control system. Unlike conventionl vrile-structure controller (VSC), which chieves superior trnsient performnce y optimising (nd hence, y vrying) the switching frequency, the novel controller is le to retin the excellent dynmic performnce of conventionl VSC nd yet mintin constnt-frequency opertion of PWM controller under stedy-stte condition. The ltter is chieved y otining duty-rtio signl; however, unlike PWM controller, the new controller clcultes the duty rtio sed on Lypunov s stility crietrion. Thus, the new controller lso permits interleved opertion of the VRM modules. Introduction The power requirement for microprocessors doules pproximtely every 6 months. Future power-delivery systems for microprocessors need to provide high currents t very low noise mrgins []. In ddition, trnsient response specifictions re lso ecoming more stringent. For instnce, the design requirements specified y Intel for VRM 9.0 re shown in Tle []. Designing VRMs to meet this continully incresing power requirement t low voltges nd high currents remins chllenging. To chieve the specified trnsient-lod response single uck convertor would require very high output-filter cpcitnce, which would increse the size of the VRM nd mke it imprcticl. Prlleling numer of DC DC synchronous-uckconvertor (SBC) modules (s shown in Fig. ) using interleving technique solves this prolem [, ], therey incresing the output ripple frequency nd reducing the size of the output-filter cpcitnce. The multiphse VRM, comprising prllel DC DC SBCs, opertes under closedloop feedck control to regulte the us voltge nd to chieve uniform current distriution mong the interleved modules. The interction mong the convertor modules is mjor source of nonlinerity, in ddition to the switching nonlinerity. However, there re few studies on the nonliner control of prllel DC DC convertors where, unlike the stnd-lone convertors, there is strong r IEE, 005 IEE Proceedings online no. 00565 doi:0.09/ip-ep:00565 Pper first received rd Septemer 00 nd in finl revised form 0th Ferury 005 S.K. Mzumder is with Lortory for Energy nd Switching-Electronics Systems, Deprtment of Electricl nd Computer Engineering, University of Illinois, 85 S Morgn St, M/C 5, 00 SEO, Chicgo, IL 60607, USA S.L. Kmisetty is with Servo Tech Inc., 77 W. Roosevelt Rod, Suite 0, Chicgo, IL 60680, USA E-mil: mzumder@ece.uic.edu Tle : VRM 9.0 design guidelines [] Electricl specifictions Intel VRM 9.0 design guidelines Output voltge.08.5 V (our nominl reference:.5 V) Output current 60 A No-lod opertion Outputs must not exceed 0% of the mximum vlue Overshoot t turn-on or turn-off Slew rte Current shring Must e within % of the nominl output voltge set y VID code 50 A/ms Should e ccurte within 0% of the rted output current, except during initil power-up nd trnsient responses interction mong the convertor modules prt from the feed-forwrd nd feedck disturnces. In [5], fuzzy-logic compenstor is proposed for the mster slve control of prllel DC DC convertor. The controller uses proportionl-integrl-derivtive (PID) expert to derive the fuzzy-inference rules; it shows improved roustness compred with liner controllers. However, the control design is purely heuristic nd the stility of the overll system hs not een proven. In [6], VSC hs een developed for uck convertor using interleving. However, the interleving scheme works only for three prllel modules. Besides, tht pper does not give ny detils regrding the existence nd stility of the sliding mnifolds. In this pper, we implement hyrid nonliner controller for prllel SBCs nd demonstrte experimentlly tht the stedy-stte nd trnsient performnces of the closed-loop prllel SBC stisfies Intel s VRM 9.0 design specifictions (s shown in Tle ). The controller uses the concepts of 076 IEE Proc.-Electr. Power Appl., Vol. 5, No. 5, Septemer 005 Authorized licensed use limited to: IEEE Xplore. Downloded on Jnury 5, 009 t 5:07 from IEEE Xplore. Restrictions pply.
u S V i inductor L i 0 i 0 r L L V C R S C lod V C trjectories re inside the oundry lyer we re le, y modifying the control using the concepts of MSSC [8, 9] or the lock-control principle [0, ], to reject mismtched disturnces [, ] nd keep the stedy-stte switching frequency constnt. Nonliner-control scheme S N S N i LN L N i NO r LN C N V CN The control scheme for the convertor hs two modes of opertion: one when the error trjectories re outside the oundry lyer nd the other when they re inside the oundry lyer. The lock digrm of the overll control scheme is shown in Fig. for N prllel SBC modules. The oundry lyer, which is time-vrying, is formed y rmp signl with frequency f s ( ¼ /T s ). The limits of this oundry lyer correspond to the mximum nd minimum vlues of the rmp. At the eginning of ech switching cycle, we determine whether the error trjectories (s shown in Fig. ), which govern the regultion of the multiphse Fig. N-module multiphse VRM comprising N prllel SBCs integrl-vrile-structure- nd multiple-sliding-surfcecontrol (i.e. IVSC nd MSSC) schemes [7]. The IVSC retins ll of the properties of VSC, i.e. simplicity in design, good dynmic response nd roustness. In ddition, the integrl ction of the IVSC elimintes the us-voltge error nd the error etween the lod currents of the convertor modules under stedy-stte conditions, nd it reduces the impct of very high-frequency dynmics due to prsitics on the closed-loop system. Finlly, when the error G k O V rk G ko f vk v Ck N f N ij i Lj j = f ik i Lk G k O Fig. Block digrm showing the determintion of s k k differentil mplifier i L u S S i L L r L C i 0 v C i 0 f v v C outer control V m k driver F differentil mplifier F inner control PWM signl S N SN i LN L N r LN C N i N0 v CN V r F f v v C power stge hyrid controller Fig. Illustrtion of the hyrid nonliner control scheme for the first SBC module of n N-module SBC The control schemes for the other N modules re the sme. The outer nd inner controls re descried in Section. The lock F represents lowpss filter, which elimintes ll hrmonic components including nd ove the switching frequency. The lock differentil mplifier represents differentil mplifier used to sense the inductor current IEE Proc.-Electr. Power Appl., Vol. 5, No. 5, Septemer 005 077 Authorized licensed use limited to: IEEE Xplore. Downloded on Jnury 5, 009 t 5:07 from IEEE Xplore. Restrictions pply.
VRMndregiveny Z s k ¼ G ko ðv r f vk v ck ÞþG ko ðv rk f vk v ck Þdt Z X N þg ko f ij i Lj f ik i Lk!dt f ik i Lk ðþ N j¼ re within the limits of the time-vrying rmp, nd sed on tht, determine wht is the mode of opertion. In (), the constnts G ko, G ko nd G ko re the controller gins (selection process descried in [7]), f vk nd f ik re the feedck-sensor gins for the output voltge nd inductor currents, V r is the reference of the output us voltge, nd P N N j¼ f iji Lj represents the verge of ll inductor currents. The first two terms in () minimise voltge error while the third term ensures equl distriution of lod current mong the vrious modules. The lst term improves the dynmic response of the system. The derivtives in conventionl VSC re replced y integrls in (). This is desirle ecuse the integrtors filter out the impcts of the highfrequency prsitic dynmics of the switching convertors. If s k is ove the oundry, the control signl to the high-side switch of SBC is constnt high while if it is elow the oundry, the switch is turned off till the error trjectory flls within the oundry. The conditions under which control sturtion outside the oundry lyer gurntees tht the error trjectories will rech the oundry lyer re derived in [, 7]. To derive the control lw within the oundry lyer, first, using Fig. nd stte spce-verged model, we define the dynmics of the prllel DC DC SBC s: di Lk ¼ r Lk i Lk þ v Ck d k u dt dv Ck ¼ i Lk i ko ; k ¼ ;...N ðþ dt where, d k is the duty rtio, i Lk nd v Ck re the verged vlues of the inductor currents nd cpcitor voltges, nd i ko re the lod current of individul convertor. Next, we define the following sliding surfces/error trjectories inside the oundry lyer (computtion of s k nd s k illustrted in Fig. ): s k ¼ G ki e k þ G ki e k þ G ki e k ðþ where s k ¼ i Lkd i Lk ðþ e k ¼ V rk f vk v Ck ð5þ Z e k ¼ ðv rk f vk v Ck Þdt ð6þ Z X N e k ¼ f ij i Lj f ik i Lk!dt ð7þ N j¼ G ki, G ki nd G ki re the controller gins (selection process descried in [7]). The sliding surfces () nd () re derived s follows. First, we define s k, which ensures regultion of the output voltge y incorporting the first two terms in (), while the third term in () ensures equl current shring mong the prllel convertor modules. The sliding surfce s k ensures tht the inductor current (i Lk ) of ech module follows desired current reference (i Lkd ). The choice of i Lkd in (), is mde such tht stle convergence on the sliding surfce s k is gurnteed, s proven lter in this Section. Stle convergence on the sliding surfce s k is chieved y pproprite selection of control d k s derived in (7). Thus, k Fig. s k s k V rk f ik i Lk the overll control concept cn e summrised s follows: first, gurntee rpid convergence of error trjectories on the sliding s k using d k (y suitle choice of k ), which ensures tht i Lkd is following i Lk very closely; nd then, using i Lkd s fictitious control, stilise the error trjectories on the sliding surfce s k. We now derive i Lkd nd d k tht ensures existence nd stility of the dynmics on the two sliding surfces s well s the stility of the dynmics on the hyperplne formed y s k nd s k. First, we differentite s k, to otin s k ¼ G ki e k þ G ki e k þ G ki e k ð8þ Sustituting () in (8) yields s k ¼ G kif vk i Lk i ko þ GkI e k þ G ki e k ð9þ f vk v Ck k sign(.) G ki G ki Sustituting for i Lk from () into (9) we otin s k ¼ G kif vk i ko þ s k i Lkd þ GkI e k þ G ki We let i Lkd ¼ k s k þ k signðs k Þþ k e k þ k Fig. 5 N f N ij i Lj j = e k e k β β β β G ki e k e k i Lkd i Lk e k k e k k Block digrm showing the determintion of s k nd s k Top lyer of the experimentl prototype ord ð0þ ðþ 078 IEE Proc.-Electr. Power Appl., Vol. 5, No. 5, Septemer 005 Authorized licensed use limited to: IEEE Xplore. Downloded on Jnury 5, 009 t 5:07 from IEEE Xplore. Restrictions pply.
where k, k, k nd k re constnts, in () nd otin s k ¼ G kif vk s k þ k signðs k Þ i ko s k k G kif vk k G ki e k G kif vk k G ki e k ðþ ð Þ Choosing k ¼ G ki ðf vk G ki Þ nd k ¼ G ki ðf vk G ki Þ reduces () to s k ¼ G kif vk k s k þ k signðs k Þ i ko s k ðþ Eqution () shows tht, when s k ¼ 0, the dynmics on s k ¼ 0 re convergent (for s k 0, or s k o0) provided tht k i komx. We ssume tht s k ¼ 0 nd design the control such tht the rte of convergence of dynmics on s k ¼ 0 re much fster thn on s k ¼ 0. Next, we differentite s k in()ndsetitequlto s k s k (where k re positive constnts) to gurntee convergence of the dynmics on s k ¼ 0 (this is ecuse, for stility, s k s k o0 nd this condition is gurnteed y the choice of s k in ()); the result is s k ¼ i Lkd i Lk ¼ ð Þ i Lkd þ r Lk i Lk þ v Ck d k u ¼ k s k Next, using the Lypunov function V ðs k ; s k Þ ¼ s k þ s k ðþ ð5þ nd () nd (), we cn show tht V ¼ s k s k þ s k s k ¼ s k G kif vk f k s k þ k signðs k Þ i ko s k g k þ s k s k G kif vk s k þ k s k k þ G r kif vk G ki f vk s k s k ¼ s k k r G ki f vk s k k G ki f vk s k ð6þ k k is less thn zero provided tht ð k k Þ G ki f vk From (), y equting i Lkd þ r Lk i Lk þ v Ck d k u ¼ k s k we otin d k ¼ u ks k þ L k i Lkd þ r Lk i Lk þ v Ck ð7þ which ensures tht, for the ove choice of control d k,the stility of the sliding surfce s k is gurnteed. We lso note tht, in (7), the term k s k compenstes for ny prmetric uncertinty in r Lk. (Typiclly, such vritions due to mnufcturing tolernces re within 5%.) For instnce, if r Lk is slightly higher thn its nominl vlue, then slightly higher i Lk is required to regulte the output voltge t the reference vlue. This compenstion is chieved (due to slight djustment in d k ) owing to slight vrition in s k tht depends on i Lkd, which in turn depends on s k ; the ltter ccounts for error in the output voltge. Using the error signl v ek, which is otined from the duty rtio d k using v ek ¼ V m d k, nd the fixed-frequency rmp signls, we cn operte N prllel DC DC SBCs in synchroncity or in interleving. Experimentl results Figures 5 nd 6 show the experimentl prototype of the overll multiphse VRM nd the circuitry for one power module, respectively. The experimentl printed-circuit ord (PCB) hs four lyers to reduce the impct of noise nd enle opertion t high switching frequency. The prmeters for the VRM re tulted in Tle, while the control specifictions re outlined in Tle. The VRM comprises four phses of the power stge (i.e. prllel DC DC SBCs) nd the nonliner controller, outlined in Section, using nlogue circuits. The complete detils of the experimentl VRM implementtion re provided in []. The four modules of the VRM operte t 00 khz nd re interleved. The interleving technique is implemented y phse shifting the drive signls of the prlleled modules y 60/N, wheren is the numer of prllel SBCs. Becuse we hve four modules, we hve phse-shifted the drive signls y qurter of switching cycle. This is rtified in Fig. 7, which shows the gte signls of the high- nd lowside power MOSFETs (FDP605L nd FDP800L, respectively), under stedy-stte conditions. gte gte gte gte gte gte gte gte Rg Rg Rg Rg Rg Rg Rg Rg Q Q Q Q Q Q Q Q L L L L C C i 5 L C C Rs V C Rs Rs Rs Rs Rs Rs Rs Rs Rs 5 5 5 i L C C i Rs L 5 Rs Rs Rs 5 5 C C i Rs L 5 Rs Rsense Rsense Rsense Rsense Fig. 6 Schemtics of the nonliner controller for one phse of the four-phse VRM [] shown in Figs. nd. In (), S represents s, S r nd S r represent s nd s, respectively IEE Proc.-Electr. Power Appl., Vol. 5, No. 5, Septemer 005 079 Authorized licensed use limited to: IEEE Xplore. Downloded on Jnury 5, 009 t 5:07 from IEEE Xplore. Restrictions pply.
Fig. 6 Continued 080 IEE Proc.-Electr. Power Appl., Vol. 5, No. 5, Septemer 005 Authorized licensed use limited to: IEEE Xplore. Downloded on Jnury 5, 009 t 5:07 from IEEE Xplore. Restrictions pply.
Tle : Nominl prmeters for the four-phse VRM Prmeter Nominl vlue r DS (on) of MOSFET 0.0056 O r Lk V r U 0.0 O mh 00 mf.5 V V f ik 0.0 f vk Switching frequency 00 khz DC offset of the rmps.5 V Height of the rmps.0 V G ko 5 G ko.5 0 5 G ko 500 G ki 0 G ki.5 0 5 G ki 500 Figure 8 shows the output voltges nd the inductor currents of the four modules of the VRM, under stedystte conditions. The four inductor currents re interleved, i.e. they differ in phse y 90. The high-side switches in the four modules of the VRM re turned on t time intervls tht re qurter of switching-time period prt from ech other. Therefore, the inductor currents do not rise nd fll t the sme time, ut, re phse shifted y qurter of switching cycle. Figure 9 shows the lod current nd the output voltge of the VRM during step-down lod trnsient of 60 A to 0 A t slew rte of 50 A/ms. During the severe lod trnsient, the output voltge stys within the % limit, s specified y Intel VRM specifictions in Tle. The inductor currents of the four phses lso respond stisfctorily nd mintin n even distriution of the lod current mong the modules during the trnsient conditions. The performnce of the VRM remins excellent even during step-up lod trnsient of 0 A to 60 A (t slew rte of 50 A/ms).ThisisillustrtedinFig.0. Once gin, the output voltge stisfied the Intel VRM specifictions nd the current shring ws mintined Ch Ch 5.0V 5.0V Ch Ch 5.0V M.0µs 5MS/s 8.0ns/pt 5.0V A Ch.8V Ch Ch.0V M.0µs 5MS/s 8.0ns/pt 5.0A Ω Ch 0.0mV A Ch 0.0A Ch Ch 0.0V 0.0V Ch Ch 0.0V M.0µs 5MS/s 8.0ns/pt 0.0V A Ch 8.8V Fig. 7 Gte signls of the four VRM modules Low-side power MOSFETs High-side power MOSFETs Ch Ch.0V M.0µs 5MS/s 8.0ns/pt 5.0A Ω Ch 0.0mV A Ch 0.0A Fig. 8 Interleved inductor currents in the four modules of the VRM nd the output voltge Currently the project hs ccess to only two current mplifiers, so only two current wveforms cn e recorded t once; this pplies lso to Figs. 9 Inductor currents (5 A/division) for modules nd Inductor currents (5 A/division) for modules nd IEE Proc.-Electr. Power Appl., Vol. 5, No. 5, Septemer 005 08 Authorized licensed use limited to: IEEE Xplore. Downloded on Jnury 5, 009 t 5:07 from IEEE Xplore. Restrictions pply.
Ch.0V Ch 0.0mV M.0ms 50kS/s.0µs/pt A Ch 0.6mV Ch.0V Ch 0.0mV M.0ms 50kS/s.0µs/pt A Ch 0.0mV Ch 0.0mV Ch.0V Ch 0.0A Ω M.0ms 50kS/s.0µs/pt A Ch 0.A Ch 0.0mV Ch.0V M.0ms 50kS/s.0µs/pt Ch 0.0A Ω A Ch 0.A Ch 0.0mV Ch.0V Ch 0.0A Ω c M.0ms 50kS/s.0µs/pt A Ch 0.A Fig. 9 Performnce of the VRM during step-up lod trnsient Lod current (0 A/division) nd output voltge of the VRM VRM output voltge nd the inductor currents (0 A/division) of modules nd c VRM output voltge nd the inductor currents (0 A/division) of modules nd Ch 0.0mV Ch.0V M.0ms 50kS/s.0µs/pt Ch 0.0A Ω A Ch 0.A c Fig. 0 Performnce of the VRM during step-down lod trnsient Lod current (0 A/division) nd output voltge of the VRM VRM output voltge nd the inductor currents (0 A/division) of modules nd c VRM output voltge nd the inductor currents (0 A/division) of modules nd during the dynmic condition in spite of rpid chnge in the lod. Finlly, Figs. nd show the error-trjectory wveforms s k nd s k during the lod trnsients. Summry nd conclusions Using the concepts of integrl-vrile-structure nd multiple-sliding-surfce controls (i.e. IVSC nd MSSC), we hve implemented roust nonliner controller for four-phse VRM, operting t 00 khz. The power stge of ech phse comprises synchronous uck convertor, the input to ll of which is V; the output voltge of the VRM is set t.5 V. We demonstrte the excellent performnces of the multiphse VRM under stedy-stte nd severe dynmic conditions. The controller is le to retin the trnsient performnce of conventionl sliding-mode/min mx controller (SMC/MMC) nd yet mintin constntfrequency opertion of PWM controller under stedystte conditions. The ltter re chieved y otining duty-rtio signl; however, unlike conventionl PWM controller, the new controller clcultes the duty rtio sed on Lypunov s stility criterion. The roust controller nullifies the us-voltge nd the lod-current errors, exhiits good current shring under stedy-stte nd dynmic conditions, nd, y using IVSC (which uses integrtors in the control insted of the differentitors in conventionl SMC/MMC), filters out ny impcts of the high-frequency prsitic dynmics in the system. An dded dvntge of 08 IEE Proc.-Electr. Power Appl., Vol. 5, No. 5, Septemer 005 Authorized licensed use limited to: IEEE Xplore. Downloded on Jnury 5, 009 t 5:07 from IEEE Xplore. Restrictions pply.
Ch.0V Ch.0V M.0ms5kS/s 8.0µs/pt Ch.0V Ch.0V Ch.0V Ch 0.0A Ω A Ch 0.0A Ch.0V Ch 0.0AΩ c M.0ms 5kS/s 8.0µs/pt A Ch 0.0A Ch.0V Ch.0mV M.0ms50kS/s 8.0µs/pt Ch.0V Ch.0V Ch.0V Ch 0.0A Ω A Ch 0.0A Ch.0V Ch 0.0AΩ d M.0ms 5kS/s 8.0µs/pt A Ch 0.0A Fig. Inductor current for module nd error signls (s k ) for SBC modules during step-down nd step-up lod trnsients Top trce: inductor current Step-down, experimentl results for SBC modules nd Step-down, experimentl results for SBC modules nd c Step-up, experimentl results for SBC modules nd d Step-up, experimentl results for SBC modules nd Ch.0V Ch.0V M.0ms5kS/s 8.0µs/pt Ch.0V Ch.0V Ch.0V Ch 0.0A Ω A Ch 0.0A Ch.0V Ch 0.0A Ω c M.0ms5kS/s 8.0µs/pt A Ch 0.0A Ch.0V Ch.0V M.0ms5kS/s 8.0µs/pt Ch.0V Ch 0.0A Ω A Ch 0.0A Ch.0V Ch.0V Ch.0V Ch 0.0A Ω d Fig. Inductor current for module nd error signls (s k ) for SBC modules Top trce: inductor current Step-down, experimentl results for SBC modules nd Step-down, experimentl results for SBC modules nd c Step-up, experimentl results for SBC modules nd d Step-up, experimentl results for SBC modules nd M.0ms5kS/s 8.0µs/pt A Ch 0.0A IEE Proc.-Electr. Power Appl., Vol. 5, No. 5, Septemer 005 08 Authorized licensed use limited to: IEEE Xplore. Downloded on Jnury 5, 009 t 5:07 from IEEE Xplore. Restrictions pply.
the control is tht it enles the modules to e interleved which reduces the output-cpcitor size nd mkes the whole system more compct. 5 Acknowledgment This work is supported in prt y the Ntionl Science Foundtion CAREER Awrd received y Prof. Mzumder in 00 under Awrd 09. However, ny opinions, findings, conclusions, or recommendtions expressed herein re those of the uthors nd do not necessrily reflect the views of the NSF. Prof. Mzumder thnks Edwrd Stnford nd Shml Chickmenhlli, oth t Intel, for their discussions during the course of this work. 6 References Emerging directions for pckging technologies, Intel Technol. J., 00, 6, () Kmisetty, S.L.: Nonliner controller for multiphse voltge regultor modules. MS thesis, University of Illinois, Chicgo, USA 00 Au-Qhouq, J.A., Pongrtnnukul, N., Btrseh, I., nd Kspris, T.: Multiphse voltge-mode hysteretic controlled VRM with DSP control nd novel current shring. Proc. IEEE Appl. Power Electron. Conf., 00, pp. 66 669 Shml, A.C., Mhdevn, S., Stnford, E., nd Merley, K.: Effect of trget impednce nd control loop design on VRM stility. Proc. IEEE Appl. Power Electron. Conf., 00, pp. 96 0 5 Tomescu, B., nd VnLndinghm, H.F.: Improved lrge-signl performnce of prlleled dc dc converters current shring using fuzzy logic control, IEEE Trns., 999, PE-, pp. 57 577 6 L!opez, M., de Vicu*n, L.G., Cstill, M., L!opez, O., nd Mj!o, J.: Interleving of prllel dc dc converters using sliding mode control. Proc. IECON 0 98, IEEE Industril Electronics Society, 998, Vol., pp. 055 059 7 Mzumder, S.K.: Nonliner nlysis nd control of stndlone, prllel DC DC, nd prllel multiphse converters. PhD thesis, Virgini Polytechnic Institute nd Stte University, Blcksurg, VA, USA, http://scholr..6.vt.edu/theses/ville/etd-08700-00 8 Green, J.H., nd Hedrick, K.: Nonliner speed control of utomotive engines. Proc. IEEE Am. Contr. Conf., 990, pp. 89 897 9 Swroop, D., Gerdes, J.C., Yip, P.P., nd Hedrick, J.K.: Dynmic surfce control of nonliner system. Proc. IEEE Am. Contr. Conf., 990, pp. 08 0 0 Drkunov, S.V., Izosimov, D.B., Lukjnov, A.G., Utkin, V., nd Utkin, V.I.: Block control principle: Prt I, Automt. Remote Contr., 990, 5, (5), pp. 8 6 Drkunov, S.V., Izosimov, D.B., Lukjnov, A.G., Utkin, V., nd Utkin, V.I.: Block control principle: Prt II, Automt. Remote Contr., 990, 5, (6), pp. 0 Brmish, B.R., nd Leitmnn, G.: On ultimte oundedness control of uncertin systems in the sence of mtching ssumptions, IEEE Trns., 98, AC-7, pp. 5 58 Corless, M., nd Leitmnn, G.: Continuous stte feedck gurntees uniform ultimte oundedness for uncertin dynmicl systems, IEEE Trns., 98, AC-6, pp. 9 08 IEE Proc.-Electr. Power Appl., Vol. 5, No. 5, Septemer 005 Authorized licensed use limited to: IEEE Xplore. Downloded on Jnury 5, 009 t 5:07 from IEEE Xplore. Restrictions pply.