Data sheet acquired from Harris Semiconductor SCHS167A November 1997 - Revised May 2000 CD54/74HC240, CD54/74HCT240, HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 High Speed CMOS Logic Octal Buffer/Line Drivers, Three-State Features Description [ /Title ( HC240, HCT24 0, HC241, HCT24 1, HC244, HC/HCT240 Inverting HC/HCT241 Non-Inverting HC/HCT244 Non-Inverting Typical Propagation Delay = 8ns at = 5V, C L = 15pF, T A = 25 o C for HC240 Three-State Outputs Buffered Inputs High- Bus Driver Outputs Fanout (Over Temperature Range) - Standard Outputs............... 10 LSTTL Loads - Bus Driver Outputs............. 15 LSTTL Loads Wide Operating Temperature Range... -55 o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH The HC240 and HCT240 are inverting three-state buffers having two active-low output enables. The HC241, HCT241, HC244 and HCT244 are non-inverting threestate buffers that differ only in that the 241 has one activehigh and one active-low output enable, and the 244 has two active-low output enables. All three types have identical pinouts. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC240F3A -55 to 125 20 Ld CERDIP HC240E -55 to 125 20 Ld PDIP HC240M -55 to 125 20 Ld SOIC CD54HCT240F3A -55 to 125 20 Ld CERDIP HCT240E -55 to 125 20 Ld PDIP HCT240M -55 to 125 20 Ld SOIC HC241E -55 to 125 20 Ld PDIP CD54HCT241F3A -55 to 125 20 Ld CERDIP HCT241E -55 to 125 20 Ld PDIP HCT241M -55 to 125 20 Ld SOIC CD54HC244F -55 to 125 20 Ld CERDIP CD54HC244F3A -55 to 125 20 Ld CERDIP HC244E -55 to 125 20 Ld PDIP HC244M -55 to 125 20 Ld SOIC CD54HCT244F -55 to 125 20 Ld CERDIP CD54HCT244F3A -55 to 125 20 Ld CERDIP HCT244E -55 to 125 20 Ld PDIP HCT244M -55 to 125 20 Ld SOIC NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2000, Texas Instruments Incorporated 1
Pinout CD54HC240, CD54HCT240, CD54HCT241, CD54HC244, CD54HCT244 (CERDIP) HC240, HCT240, HC241, HCT241, HC244, HCT244 (PDIP, SOIC) TOP VIEW 240 1OE 1A0 2Y3 1A1 2Y2 1A2 2Y1 1A3 2Y0 241 244 1OE 1 1A0 2 2Y3 3 1A1 4 2Y2 5 1A2 6 2Y1 7 1A3 8 2Y0 9 10 241 244 240 20 19 2OE (241) 2OE (240, 244) 18 1Y0 1Y0 17 2A3 2A3 16 1Y1 1Y1 15 2A2 2A2 14 1Y2 1Y2 13 2A1 2A1 12 1Y3 1Y3 11 2A0 2A0 Functional Diagram 241 AND 244 240 1A0 2 18 1Y0 1Y0 1A1 4 16 1Y1 1Y1 1A2 6 14 1Y2 1Y2 1A3 8 12 1Y3 1Y3 11 2A0 9 2Y0 2Y0 13 2A1 7 2Y1 2Y1 15 2A2 5 2Y2 2Y2 240 AND 244 1OE 2OE 17 2A3 241 1OE 2OE 1 19 3 2Y3 2Y3 = 20 = 10 2
Absolute Maximum Ratings DC Supply,........................ -0.5V to 7V DC Input Diode, I IK For V I < -0.5V or V I > + 0.5V......................±20mA DC Output Diode, I OK For V O < -0.5V or V O > + 0.5V....................±20mA DC Drain, per Output, I O For -0.5V < V O < + 0.5V.......................... ±35mA DC Output Source or Sink per Output Pin, I O For V O > -0.5V or V O < + 0.5V....................±25mA DC or Ground, I CC.........................±70mA Thermal Information Thermal Resistance (Typical, Note 3) θ JA ( o C/W) PDIP Package............................. 125 SOIC Package............................. 120 Maximum Junction Temperature....................... 150 o C Maximum Storage Temperature Range..........-65 o C to 150 o C Maximum Lead Temperature (Soldering 10s)............. 300 o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range (T A )..................... -55 o C to 125 o C Supply Range, HC Types.....................................2V to 6V HCT Types.................................4.5V to 5.5V DC Input or Output, V I, V O................. 0V to Input Rise and Fall Time 2V...................................... 1000ns (Max) 4.5V...................................... 500ns (Max) 6V....................................... 400ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER HC TYPES SYMBOL V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input V IH - - 2 1.5 - - 1.5-1.5 - V 4.5 3.15 - - 3.15-3.15 - V 6 4.2 - - 4.2-4.2 - V Low Level Input V IL - - 2 - - 0.5-0.5-0.5 V 4.5 - - 1.35-1.35-1.35 V High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads V OH V OL 6 - - 1.8-1.8-1.8 V V IH or -0.02 2 1.9 - - 1.9-1.9 - V V IL -0.02 4.5 4.4 - - 4.4-4.4 - V -0.02 6 5.9 - - 5.9-5.9 - V -6 4.5 3.98 - - 3.84-3.7 - V -7.8 6 5.48 - - 5.34-5.2 - V V IH or 0.02 2 - - 0.1-0.1-0.1 V V IL 0.02 4.5 - - 0.1-0.1-0.1 V 0.02 6 - - 0.1-0.1-0.1 V 6 4.5 - - 0.26-0.33-0.4 V 7.8 6 - - 0.26-0.33-0.4 V Input Leakage I I or - 6 - - ±0.1 - ±1 - ±1 µa Quiescent Device I CC or 0 6 - - 8-80 - 160 µa 3
DC Electrical Specifications (Continued) PARAMETER Three-State Leakage HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Quiescent Device Additional Quiescent Device Per Input Pin: 1 Unit Load (Note 4) Three-State Leakage SYMBOL I OZ V IL or - 6 - - ±0.5 - ±0.5 - ±10 µa V IH V IH - - 4.5 to 5.5 V IL - - 4.5 to 5.5 V OH V OL I I I CC I CC I OZ 2 - - 2-2 - V - - 0.8-0.8-0.8 V V IH or -0.02 4.5 4.4 - - 4.4-4.4 - V V IL -6 4.5 3.98 - - 3.84-3.7 - V V IH or 0.02 4.5 - - 0.1-0.1-0.1 V V IL to or -2.1 6 4.5 - - 0.26-0.33-0.4 V 0 5.5 - - ±0.1 - ±1 - ±1 µa 0 5.5 - - 8-80 - 160 µa - 4.5 to 5.5-100 360-450 - 490 µa V IL or - 5.5 - - ±0.5 - ±5 - ±10 µa V IH NOTE: 4. For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. HCT Input Loading Table TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HCT240 HCT241 HCT244 INPUT UNIT LOADS na0-a3 1.5 1OE 0.7 2OE 0.7 na0-a3 0.7 1OE 0.7 2OE 1.5 na0-a3 0.7 1OE 0.7 2OE 0.7 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25 o C. 4
Switching Specifications C L = 50pF, Input t r, t f = 6ns PARAMETER SYMBOL TEST CONDI- TIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS HC TYPES Propagation Delay t PLH, t PHL C L = 50pF HC240 2 - - 100 - - 125 - - 150 ns 4.5 - - 20 - - 25 - - 30 ns C L = 15pF 5-8 - - - - - - - ns C L = 50pF 6 - - 17 - - 21 - - 26 ns HC241 t PLH, t PHL C L = 50pF 2 - - 110 - - 140 - - 165 ns 4.5 - - 22 - - 28 - - 33 ns C L = 15pF 5-9 - - - - - - - ns C L = 50pF 6 - - 19 - - 24 - - 28 ns HC244 t PLH, t PHL C L = 50pF 2 - - 110 - - 140 - - 165 ns 4.5 - - 22 - - 28 - - 33 ns C L = 15pF 5-9 - - - - - - - ns C L = 50pF 6 - - 19 - - 24 - - 28 ns Output Enable and Disable Time t THL, t TLH C L = 50pF 2 - - 150 - - 190 - - 225 ns 4.5 - - 30 - - 38 - - 45 ns 5-12 - - - - - - - ns 6 - - 26 - - 33 - - 38 ns Output Transition Time t TLH, t THL C L = 50pF 2 - - 60 - - 75 - - 90 ns 4.5 - - 12 - - 15 - - 18 ns 6 - - 10 - - 13 - - 15 ns Input Capacitance C I C L = 50pF - 10-10 - - 10 - - 10 pf Three-State Output Capacitance C O C L = 50pF - - - 20 - - 20 - - 20 pf Power Dissipation Capacitance (Notes 5, 6) C PD C L = 15pF HC240 5-38 - - - - - - - pf HC241 5-34 - - - - - - - pf HC244 5-46 - - - - - - - pf HCT TYPES Propagation Delay HCT240 HCT241 HCT244 t PHL, t PLH C L = 50pF 4.5 - - 22 - - 28 - - 33 ns C L = 15pF 5-9 - - - - - - - ns t PHL, t PLH C L = 50pF 4.5 - - 25 - - 31 - - 38 ns C L = 15pF 5-10 - - - - - - - ns t PHL, t PLH C L = 50pF 4.5 - - 25 - - 31 - - 38 ns C L = 15pF 5-10 - - - - - - - ns 5
Switching Specifications C L = 50pF, Input t r, t f = 6ns (Continued) PARAMETER SYMBOL TEST CONDI- TIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Output Enable and Disable Times t TLH, t THL C L = 50pF 4.5 - - 30 - - 38 - - 45 ns Output Transition Time t THL, t TLH C L = 50pF 4.5 - - 12 - - 15 - - 18 ns Input Capacitance C I C L = 50pF - 10-10 - - 10 - - 10 pf Power Dissipation Capacitance (Notes 5, 6)) C PD HCT240-5 - 40 - - - - - - - pf HCT241-5 - 38 - - - - - - - pf HCT244-5 - 40 - - - - - - - pf NOTES: 5. C PD is used to determine the dynamic power consumption, per channel. 6. P D = V 2 CC f i (C PD + C L ) where f i = Input Frequency, f O = Output Frequency, C L = Output Load Capacitance, = Supply. Test Circuits and Waveforms t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT INPUT 2.7V 1.3V 0.3V 3V t THL t TLH t THL t TLH INVERTING t PHL t PLH INVERTING t PHL t PLH 1.3V FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns DISABLE 6ns t r DISABLE 6ns t f 2.7 1.3 0.3 6ns 3V tplz t PZL t PLZ t PZL LOW TO OFF LOW TO OFF 1.3V HIGH TO OFF t PHZ t PZH HIGH TO OFF t PHZ t PZH 1.3V S ENABLED S DISABLED S ENABLED S ENABLED S DISABLED S ENABLED FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM 6
Test Circuits and Waveforms (Continued) OTHER INPUTS TIED HIGH OR LOW DISABLE IC WITH THREE- STATE R L = 1kΩ C L 50pF FOR t PLZ AND t PZL FOR t PHZ AND t PZH NOTE: Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left. The test circuit is Output R L =1kΩ to, C L = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 7
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