V High and Low Side Gate Driver Driver Characteristics Parameter Rating Units V OFFSET V I O +/- (Source/Sink) / A V OUT - V t on /t off / ns Delay Matching (Max) ns Features Floating Channel for Bootstrap Operation to +V with Absolute Maximum Rating of +7V Outputs Capable of Sourcing and Sinking A Gate Drive Supply Range From V to V Enhanced Robustness due to SOI Process Tolerant to Negative Voltage Transients: dv/dt Immune.V Logic Compatible Undervoltage Lockout for Both High-side and Low-Side Outputs Matched Propagation Delays Description The is a high voltage integrated circuit that can drive high speed MOSFETs and IGBTs that operate at up to +V. The is configured with independent high-side and low-side referenced output channels, both of which can source and sink A. The floating high-side channel can drive an N-channel power MOSFET or IGBT V from the common reference. Manufactured on IXYS Integrated Circuits Division's proprietary high-voltage BCDMOS on SOI (silicon on insulator) process, the is extremely robust, and is virtually immune to negative transients. The UV circuit prevents the turn-on of the MOSFET or IGBT until there is sufficient V BS or supply voltage. Propagation delays are matched for use in high frequency applications. The is available in a -pin DIP package and in a -pin SOIC package. Ordering Information Part G B BTR Description -Pin DIP (/Tube) -Pin SOIC (/Tube) -Pin SOIC (/Reel) Functional Block Diagram SD V SS Input Control Logic & Cycle-by-Cycle Edge-Triggered Shutdown Level Shift / V SS / COM Level Shift / V SS / COM Pulse Generator High Voltage Level Shift LS Delay Control UV R R Q S UV Buffer Buffer V B V S COM DS--R www.ixysic.com
. Specifications............................................................................................... Package Pinout: -Pin SOIC Package........................................................................ Pin Description: -Pin SOIC Package........................................................................ Package Pinout: -Pin DIP Package......................................................................... Pin Description: -Pin DIP Package......................................................................... Absolute Maximum Ratings................................................................................. Recommended Operating Conditions.........................................................................7 Dynamic Electrical Characteristics............................................................................ Static Electrical Characteristics.............................................................................. Test Waveforms.......................................................................................... Typical Performance Data..................................................................................... 7. Manufacturing Information.................................................................................... Moisture Sensitivity...................................................................................... ESD Sensitivity......................................................................................... Reflow Profile........................................................................................... Board Wash............................................................................................ Mechanical Dimensions.................................................................................. www.ixysic.com R
Specifications. Package Pinout: -Pin SOIC Package. Package Pinout: -Pin DIP Package - COM - - V S - V B - 7 - - V SS - - SD - - - COM - - V S - V B - - V SS - - SD - - - 7. Pin Description: -Pin SOIC Package Pin# Name Description Low-Side Gate Drive Output COM Low-Side Return Low-Side Supply - No Connection - No Connection V S High-Side Floating Supply Return 7 V B High-Side Floating Supply High-Side Gate Drive Output - No Connection - No Connection Logic Supply Logic Input for High-Side Gate Driver Output (), In-Phase SD Logic Input for Shutdown Logic Input for Low-Side Gate Driver Output (), In-Phase. Pin Description: -Pin DIP Package Pin# Name Description Low-Side Gate Drive Output COM Low-Side Return Low-Side Supply - No Connection V S High-Side Floating Supply Return V B High-Side Floating Supply 7 High-Side Gate Drive Output - No Connection Logic Supply Logic Input for High-Side Gate Driver Output (), In-Phase SD Logic Input for Shutdown V SS Logic Ground - No Connection Logic Input for Low-Side Gate Driver Output (), In-Phase V SS Logic Ground - No Connection R www.ixysic.com
. Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board-mounted and still-air conditions. Parameter Symbol Min Max Units High-Side Floating Supply Voltage V B -. 7 V High-Side Floating Supply Offset Voltage V S V B - V B +. V High-Side Floating Output Voltage V V S -. V B +. V Low-Side Fixed Supply Voltage -. V Low-Side Output Voltage V -. +. V Logic Supply Voltage -. V SS + V Logic Supply Offset Voltage V SS - +. V Logic Input Voltage (,, SD) V IN V SS -. +. V Allowable Offset Supply Voltage Transient dv S /dt - V/ns Package Power Dissipation @ T A C -Pin SOIC -. PD -Pin DIP. W Thermal Resistance, Junction to Ambient -Pin SOIC - R JA -Pin DIP 7 C/W Junction Temperature T J - C Storage Temperature T S - C Lead Temperature (Soldering, Seconds) T L - C. Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. The V S and V SS offset ratings are tested with all supplies biased at a V differential. Parameter Symbol Min Max Units High-Side Floating Supply Absolute Voltage V B V S + V S + High-Side Floating Supply Offset Voltage V S - High-Side Floating Output Voltage V V S V B Low-Side Fixed Supply Voltage Low-Side Output Voltage V Logic Supply Voltage V SS + V SS + Logic Supply Offset Voltage V SS - Logic Input Voltage (,, SD) V IN V SS Ambient Temperature T A - + C V www.ixysic.com R
.7 Dynamic Electrical Characteristics V BIAS (, V BS, )=V, CL= pf, T A = C, and V SS =COM unless otherwise specified. Parameter Conditions Symbol Min Typ Max Units Turn-On propagation Delay V S =V t on - Turn-Off propagation Delay t off - V S =V Shutdown propagation Delay t SD - Turn-On Rise Time - t r -. ns Turn-Off Fall Time - t f -.7 Delay Matching, HS & LS Turn-On/Off - MT - -. Static Electrical Characteristics V BIAS (, V BS, )=V, T A = C and V SS =COM unless otherwise specified. The V IN, V TH, and I IN parameters are referenced to V SS and are applicable to all three logic input leads:,, and SD. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: or. Parameter Conditions Symbol Min Typ Max Units Logic Input Voltage V IH. - - =V Logic Input Voltage V IL - - Logic Input Voltage V IH. - - =V Logic Input Voltage V IL - -. V V High-Level Output Voltage, V BIAS -V O I O =A V OH -.. Low-Level Output Voltage, V O I O =ma V OL - -. V Offset Supply Leakage Current V B =V S =V I LK - - Quiescent V BS Supply Current V IN =V or I QBS - 7 Quiescent Supply Current V IN =V or I QCC - A Quiescent Supply Current V IN =V or I QDD - - Logic Input Bias Current V IN = I IN+ - Logic Input Bias Current V IN =V I IN- - - A V BB Supply Undervoltage Positive Going Threshold - V BSUV+ 7...7 V BB Supply Undervoltage Negative Going Threshold - V BSUV- 7 7.. Supply Undervoltage Positive Going Threshold - UV+ 7... V Supply Undervoltage Negative Going Threshold - UV- 7 7.. Output High Short Circuit Pulsed Current V O =V, V IN =, PW s I O+. - Output Low Short Circuit Pulsed Current V O =V, V IN =V, PW s I O-. - A R www.ixysic.com
. Test Waveforms.. Switching Time Test Circuit =V µf.µf SD 7.µF C L µf V B + V - ( to V/V) µf V S C L Note: Pin numbers shown are for the SOIC package... Input/Output Timing Diagram.. Shutdown Waveform Definitions SD SD % t sd %.. Switching Time Waveform Definition.. Delay Matching Waveform Definitions % % % % t on t r t off t f % % % % MT % % MT www.ixysic.com R
Typical Performance Data Turn-On Delay Time Turn-Off Delay Time Turn-On Delay Time vs. V BIAS Supply Voltage Turn-On Delay Time (ns) Turn-Off Delay Time (ns) Turn-On Delay Time (ns) - - 7 - - 7 7 Turn-Off Delay Time (ns) Turn-Off Delay Time vs. V BIAS Supply Voltage 7 Shutdown Delay Time (ns) Shutdown Delay Time - - 7 Shutdown Propagation Delay (ns) Shutdown Delay Time vs. V BIAS Supply Voltage V BIAS Shutdown Delay Time (ns) Shutdown Delay Time vs. Supply Voltage Turn-On Rise Time (ns) Turn-On Rise Time - - 7 Turn-Off Fall Time (ns) Turn-Off Fall Time - - 7 R www.ixysic.com 7
Turn-On Rise Time (ns) Turn-On Rise Time vs. Voltage V BIAS Turn-Off Fall Time (ns) Turn-Off Fall Time vs. Voltage V BIAS Logic Input Threshold (V) Logic Input Threshold vs. (V) Logic Input Threshold (V) Logic Input Threshold vs. (V) Logic "" Input Threshold (V) Logic "" Input Threshold - - 7 Logic "" Input Threshold (V) Logic "" Input Threshold - - 7 Logic "" Input Current (µa)...... Logic "" Input Current. - - 7 Logic "" Input Bias Current (µa) Logic "" Input Bias Current - - 7 Supply Current (µa) Supply Current - - 7 Supply Current V BS Supply Current. Supply Current vs. Voltage Supply Current (µa) V BS Supply Current (µa) Supply Current (µa).... - - 7 - - 7. Logic www.ixysic.com R
Supply Current vs. Voltage V BS Supply Current vs. Voltage Offset Supply Leakage Current Supply Current (µa) V BS Supply Current (µa) Leakage Current (µa) Fixed V BS Floating - - 7 Leakage Current (µa) Offset Supply Leakage Current vs. V B Boost Voltage V B Boost Voltage (V) Undervoltage Lockout+ (V) 7 Undervoltage Lockout (+) - - 7 Undervoltage Lockout- (V) 7 Undervoltage Lockout (-) - - 7 V BS Undervoltage Lockout+ (V) 7 V BS Undervoltage Lockout (+) - - 7 V BS Undervoltage Lockout- (V) 7 V BS Undervoltage Lockout (-) - - 7 High Level Output Voltage (V) High Level Output Voltage (I O =ma) - - 7 Low Level Output Voltage (V)..... Low Level Output Voltage (I O =ma). - - 7 Output Source Current (A) Output Source Current - - 7 Output Sink Current (A) Output Sink Current - - 7 R www.ixysic.com
Output Source Current (A) Output Source Current vs. Voltage V BIAS Output Sink Current (A) Output Sink Current vs. Voltage V BIAS High Level Output Voltage (V) High Level Output Voltage vs. Supply Voltage V BIAS Low Level Output Voltage (mv) Low Level Output Voltage vs. Supply Voltage Figure. Typical Connection Diagram up to V V B SD SD V S AD COM V SS V SS www.ixysic.com R
Manufacturing Information. Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-. Device Moisture Sensitivity Level (MSL) Rating B, G MSL. ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-.. Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD- must be observed. Device B G Maximum Temperature x Time C for seconds C for seconds. Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used. R www.ixysic.com
. Mechanical Dimensions.. B: -Pin SOIC Package PIN. ±. (. ±.) Recommended PCB Land Pattern.7 (.) 7. ±.7 (. ±.). ±. (. ±.). (.7). (.7) PIN.7 TYP (. TYP). ±.7 (. ±.). (.).7 ±. (. ±.) º. ±. (. ±.). ±. (. ±.). ±.7 (. ±.7). / +. / -. (. / +. / -.) NOTES:. Coplanarity =. (.) max.. Leadframe thickness does not include solder plating ( microinch maximum). DIMENSIONS mm (inches).. BTR: Tape & Reel Packaging for -Pin SOIC Package. DIA. (. DIA.) Top Cover Tape Thickness. MAX. (. MAX.) B =.7 (.) W= (.) K =. (.) K =.7 (.) A =. (.) P=. (.7) Embossed Carrier Embossment NOTES:. All dimensions carry tolerances of EIA Standard -. The tape complies with all Notes for constant dimensions listed on page of EIA-- Dimensions mm (inches) www.ixysic.com R
.. G: -Pin DIP Through-Hole Package. /. (.7 /.7) See Note º / º PCB Hole Pattern 7. BSC (. BSC). /. (. /.7) See Note 7. (.). (.) Pin. (.). /.77 (. /.) See Note.7 /. (. /.). /. (. /.). min (. min). typ (. typ). max (. max) H Seating Plane.7 typ (. typ). (.) NOTES:. JEDEC outline: MS- AA.. This dimension does not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.).. Measured at the lead tips with the leads unconstrained.. Pointed or rounded lead tips are preferred to ease insertion.. Distance between leads including dam bar protrusions to be.7 (.).. Datum plane H coincident with the bottom of lead where lead exits body. Hole Size =. (.) DIMENSIONS (min / max) mm (inches) For additional information please visit our website at: www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS--R Copyright, IXYS Integrated Circuits Division All rights reserved. Printed in USA. // R www.ixysic.com