Product Description The PE5 is a HaRP -enhanced, high linearity, 5-bit RF Digital Step Attenuator (DSA). This highly versatile DSA covers a 7.75 db attenuation range in.5 db steps. The Peregrine 5Ω RF DSA provides a serial-addressable CMOS control interface. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with V DD due to on-board regulator. This next generation Peregrine DSA is available in a 5x5 mm -lead QFN footprint. The PE5 is manufactured on Peregrine s UltraCMOS process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure. Package Type -lead 5x5x.85 mm QFN Package Figure. Functional Schematic Diagram PE5 5 Ω RF Digital Attenuator 5-bit, 7.75 db, 9 khz - 6. GHz Features HaRP -enhanced UltraCMOS device Attenuation:.5 db steps to 7.75 db High Linearity: Typical +58 dbm IP Excellent low-frequency performance. V or 5. V Power Supply Voltage Fast switch settling time Programming Modes: Direct Parallel Latched Parallel Serial-Addressable: Program up to eight addresses - High-attenuation state @ power-up (PUP) CMOS Compatible No DC blocking capacitors required Packaged in a -lead 5x5x.85 mm QFN Switched Attenuator Array RF Input RF Output Parallel Control 5 Serial In CLK Control Logic Interface LE A A A Document No. 7-5-5 www.psemi.com 8-9 Peregrine Semiconductor Corp. All rights reserved. Page of
PE5 Step Error (db) Table. Electrical Specifications @ +5 C, V DD =. V or 5. V Parameter Test Conditions Frequency Min Typical Max Units Frequency Range 9 khz 6 GHz Attenuation Range.5 db Step 7.75 db Insertion Loss 9 khz 6 GHz..8 db Attenuation Error..75.5.5. db - 7.75 db Attenuation settings db to.5 db Attenuation Settings.75 db to 7.75 db Attenuation Settings db to 7.75dB Attenuation Settings MHz 9 MHz 8 MHz MHz MHz MHz 5 MHz 6 MHz -.5 5 6 7 8 Attenuation Setting (db) 9 khz < GHz GHz 6 GHz GHz 6 GHz GHz 6 GHz Figure..5dB Attenuation vs. Attenuation State Attenuation Attenuation db 8 7 6 5 9 MHz 8 MHz MHz MHz 5 MHz 58 MHz 5 6 7 8 Attenuation State ±(.5+%) +.+% +.+% -. - % Return Loss 9 khz - 6 GHz 8 db Relative Phase All States 9 khz - 6 GHz 9 deg PdB (note ) Input MHz - 6 GHz dbm IIP Two tones at +8 dbm, MHz spacing MHz - 6 GHz 58 dbm Typical Spurious Value MHz - dbm Video Feed Through mvpp Switching Time 5% CTRL to % / 9% RF 65 ns RF Trise/Tfall % / 9% RF ns Settling Time RF settled to within.5 db of final value RBW = 5 MHz, Averaging ON. µs Note:. Please note Maximum Operating Pin (5Ω) of +dbm as shown in Table. Performance Plots Figure..5 db Step Error vs. Frequency* *Monotonicity is held so long as Step-Error does not cross below -.5 db db db db Figure 5..5 db Major State Bit Error.5dB State.5dB State db State db State db State 7.75dB State.5 Figure 6..5 db Attenuation Error vs. Frequency.5 MHz 9 MHz 8 MHz MHZ MHz MHz 5 MHz 6 MHz.. Bit Error (db).5. -.5 -. Attenuation Error (db).5. -.5 -. -.5 -.5 5 6 5 6 7 8 Frequency (MHz) Attenuation Setting (db) 8-9 Peregrine Semiconductor Corp. All rights reserved. Document No. 7-5-5 UltraCMOS RFIC Solutions Page of
PE5 Insertion Loss (dbm) Figure 7. Insertion Loss vs. Temperature Return Loss (db) -.5 - -.5 - -.5 - -.5 - -.5-5 - - - - -5 -C +5C +85C 5 6 7 8 9 Frequency (GHz) Figure 9. Output Return Loss vs. Attenuation: T = +5C db.5db.5db db db db 7.75dB -6 5 6 7 8 9 Frequency (GHz) Figure. Output Return Loss vs. Temperature: 7.75 db State Return Loss (db) Return Loss (db) Figure 8. Input Return Loss vs. Attenuation: T = +5C -5 - -5 - -5 - -5 - -5-5 5 6 7 8 9 - - - - -5-6 db.5db.5db db db db 7.75dB Frequency (GHz) Figure. Input Return Loss vs. Temperature: 7.75 db State -C 5C 85C 5 6 7 8 9 Frequency (GHz) Figure. Relative Phase vs. Frequency -C 5C 85C 6 db.5db.5db db db db 7.75dB - Return Loss (db) - - - -5-6 -7 5 6 7 8 9 Frequency (GHz) Relative Phase Error (Deg) 8 6 5 6 7 8 Frequency (GHz) Document No. 7-5-5 www.psemi.com 8-9 Peregrine Semiconductor Corp. All rights reserved. Page of
PE5 Phase (Deg) Figure. Relative Phase vs. Temperature: 7.75 db State.5..5..5..5..5 9 MHz 8 MHz MHz Attenuation Error (db) Figure. Attenuation Error vs. Attenuation Setting: 9 MHz.5..5. -.5 -. +5 C -C +85C Attenuation Error (db). - - 6 8 Temperature (Deg. C) Figure 5. Attenuation Error vs. Attenuation Setting: 8 MHz.5..5. -.5 -. +5C -C +85C -.5 5 6 7 8 Attenuation Setting (db) -.5 5 6 7 8 Attenuation Error (db).5..5. -.5 -. Attenuation Setting (db) Figure 6. Attenuation Error vs. Attenuation Setting: MHz +5C -C +85C -.5 5 6 7 8 Attenuation Setting (db) Figure 7. Input IP vs. Frequency 7 db.5db.5db db db db 65 6 Input IP (dbm) 55 5 5 5 5 6 7 Frequency (MHz) 8-9 Peregrine Semiconductor Corp. All rights reserved. Document No. 7-5-5 UltraCMOS RFIC Solutions Page of
PE5 Figure 8. Pin Configuration (Top View) NC V DD A RF 5 6 7 8 C.5 C.5 C C C SI 9 8 7 6 5 9 Exposed Solder pad 5 6 Table. Pin Descriptions 9 8 7 CLK LE A A RF Pin No. Pin Name Description N/C No Connect V DD Power supply pin P /S Serial/Parallel mode select A Address bit A connection 5, 6, 8-7, 9,, 6, Ground 7 7 RF RF port 8 RF RF port A Address bit A connection A Address bit A connection LE Serial interface Latch Enable input CLK Serial interface Clock input 5 SI Serial interface Data input 8 C (D) Parallel control bit, db 9 C (D) Parallel control bit, db C (D) Parallel control bit, db C.5 (D) Parallel control bit,.5 db C.5 (D) Parallel control bit,.5 db Paddle Ground for proper operation Note: Ground C.5, C.5, C C, C, if not in use. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE5 in the -lead 5x5 QFN package is MSL. Switching Frequency The PE5 has a maximum 5 khz switching rate. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Document No. 7-5-5 www.psemi.com 8-9 Peregrine Semiconductor Corp. All rights reserved. Page 5 of
PE5 Table. Operating Ranges Parameter Min Typ Max Units V DD Power Supply Voltage.. V V DD Power Supply Voltage 5. 5.5 V Table. Absolute Maximum Ratings Symbol Parameter/Conditions Min Max Units V DD Power supply voltage -. 6. V V I Voltage on any Digital input -. 5.8 V I DD Power Supply Current 7 5 µa Digital Input High.6 5.5 V P IN Input power (5Ω) 9 khz MHz MHz 6 GHz See fig. 9 + dbm dbm P IN Input power (5Ω): 9 khz MHz MHz 6 GHz T OP Operating temperature range Pin dbm 5 5 5 See fig. 9 + dbm dbm - 5 85 C Digital Input Low V Digital Input Leakage 5 µa Note. Input leakage current per Control pin Figure 9. Maximum Power Handling Capability: Z = 5 Ω T ST Storage temperature range -65 5 C V ESD ESD voltage (HBM) ESD voltage (Machine Model) 5 Note:. Human Body Model (HBM, MIL_STD 88 Method 5.7) Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. V V.E+.E+.E+5.E+6.E+7.E+8.E+9 Hz 8-9 Peregrine Semiconductor Corp. All rights reserved. Document No. 7-5-5 UltraCMOS RFIC Solutions Page 6 of
PE5 Table 5. Control Voltage State Bias Condition Low to +. Vdc at µa (typ) High Table 6. Latch and Clock Specifications Latch Enable X Shift Clock X +.6 to +5 Vdc at µa (typ) Function Shift Register Clocked Contents of shift register transferred to attenuator core Table 8. Address Word Truth Table A7 (MSB) Address Word A6 A5 A A A A A Address Setting X X X X X L L L X X X X X L L H X X X X X L H L X X X X X L H H X X X X X H L L X X X X X H L H X X X X X H H L X X X X X H H H Table 7. Parallel Truth Table Table. Serial-Addressable Register Map MSB (last in) Parallel Control Setting D D D D D Attenuation Setting RF-RF L L L L L Reference I.L. L L L L H.5 db L L L H L.5 db L L H L L db L H L L L db H L L L L db H H H H H 7.75 db Table 9. Serial Attenuation Word Truth Table Attenuation Word D7 D6 D5 D D D D Bits can either be set to logic high or logic low D5, D6 and D7 must be set to logic low D (LSB) Attenuation Setting RF-RF L L L L L L L L Reference I.L. L L L L L L L H.5 db L L L L L L H L.5 db L L L L L H L L db L L L L H L L L db L L L H L L L L db L L L H H H H H 7.75 db LSB (first in) Q5 Q Q Q Q Q A7 A6 A5 A A A Q9 Q8 Q7 Q6 Q5 Q A A D7 D6 D5 D Q Q Q Q D D D D Address Word Attenuation Word Attenuation Word is derived directly from the attenuation value. For example, to program the.75 db state at address : Address Word: XXXXX Attenuation Word: Multiply by and convert to binary *.75 db 5 Serial Input: XXXXX Document No. 7-5-5 www.psemi.com 8-9 Peregrine Semiconductor Corp. All rights reserved. Page 7 of
PE5 Programming Options Parallel/Serial Selection Either a parallel or serial-addressable interface can be used to control the PE5. The P /S bit provides this selection, with P /S=LOW selecting the parallel interface and P /S=HIGH selecting the serialaddressable interface. Parallel Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 7. The parallel interface timing requirements are defined by Fig. (Parallel Interface Timing Diagram), Table (Parallel Interface AC Characteristics), and switching speed (Table ). For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. ) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface The serial-addressable interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. The 6-bits make up two words comprised of 8-bits each. The first word is the Attenuation Word, which controls the state of the DSA. The second word is the Address Word, which is compared to the static (or programmed) logical states of the A, A and A digital inputs. If there is an address match, the DSA changes state; otherwise its current state will remain unchanged. Fig. illustrates an example timing diagram for programming a state. It is required that all parallel control inputs be grounded when the DSA is used in serialaddressable mode. The serial-addressable interface is controlled using three CMOS-compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the 8-9 Peregrine Semiconductor Corp. All rights reserved. Document No. 7-5-5 UltraCMOS RFIC Solutions Page 8 of shift register. Serial data is clocked in LSB first, beginning with the Attenuation Word. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Address word and attenuation word truth tables are listed in Table 8 & Table 9, respectively. A programming example of the serial-addressable register is illustrated in Table. The serial-addressable timing diagram is illustrated in Fig.. Power-up Control Settings The PE5 will always initialize to the maximum attenuation setting (7.75 db) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In directparallel mode, the DSA can be preset to any state within the 7.75 db range by pre-setting the parallel control pins prior to power-up. In this mode, there is a -µs delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (7.75 db) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). Dynamic operation between serial-addressable and parallel programming modes is possible. If the DSA powers up in serial-addressable mode (P/ S = HIGH), all the parallel control inputs DI[:] must be set to logic low. Prior to toggling to parallel mode, the DSA must be programmed serially to ensure D[7] is set to logic low. If the DSA powers up in either latched or directparallel mode, all parallel pins DI[:] must be set to logic low prior to toggling to serial-addressable mode (P /S = HIGH), and held low until the DSA has been programmed serially to ensure bit D[7] is set to logic low. The sequencing is only required once on powerup. Once completed, the DSA may be toggled between serial-addressable and parallel programming modes at will.
PE5 Figure. Serial-Addressable Timing Diagram Bits can either be set to logic high or logic low D[5], D[6] and D[7] must be set to logic low DI[:] T DISU T DIH ADD[:] VALID T ASU T AIH T PSSU T PSIH SI D[] D[] D[] D[] D[] D[5] D[6] D[7] A[] A[] A[] T SISU T SIH CLK T CLKL T CLKH T LESU LE T LEPW T PD DO[6:] VALID Figure. Latched-Parallel/Direct-Parallel Timing Diagram DI[:] LE DO[:] T PSSU T DIPD VALID T DISU T LEPW VALID Table. Serial-Addressable Interface AC Characteristics V DD =. or 5. V, - C < T A < 85 C, unless otherwise specified Symbol Parameter Min Max Unit F CLK Serial clock frequency - MHz T CLKH Serial clock HIGH time - ns T CLKL Serial clock LOW time - ns T LESU Last serial clock rising edge setup time to Latch Enable - ns rising edge T LEPW Latch Enable min. pulse width - ns T SISU Serial data setup time - ns T SIH Serial data hold time - ns T DISU Parallel data setup time - ns T DIH Parallel data hold time - ns T ASU Address setup time - ns T AH Address hold time - ns T PSSU Parallel/Serial setup time - ns T PSH Parallel/Serial hold time - ns T PD Digital register delay (internal) - ns T PD Document No. 7-5-5 www.psemi.com T PSH T DIH Table. Parallel and Direct Interface AC Characteristics V DD =. or 5. V, - C < T A < 85 C, unless otherwise specified Symbol Parameter Min Max Unit T LEPW Latch Enable minimum pulse width - ns T DISU Parallel data setup time - ns T DIH Parallel data hold time - ns T PSSU Parallel/Serial setup time - ns T PSIH Parallel/Serial hold time - ns T PD T DIPD Digital register delay (internal) Digital register delay (internal, direct mode only) - ns - 5 ns 8-9 Peregrine Semiconductor Corp. All rights reserved. Page 9 of
PE5 Evaluation Kit The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE5 Digital Step Attenuator. Figure. Evaluation Board Layout Peregrine Specification - Direct-Parallel Programming Procedure For automated direct-parallel programming, connect the test harness provided with the EVK from the parallel port of the PC to the J & Serial header pin and set the D-D SPT switches to the MIDDLE toggle position. Position the Parallel/Serial (P /S) select switch to the Parallel (or left) position. The evaluation software is written to operate the DSA in either Parallel or Serial-Addressable Mode. Ensure that the software is set to program in Direct-Parallel mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. For manual direct-parallel programming, disconnect the test harness provided with the EVK from the J and Serial header pins. Position the Parallel/Serial (P /S) select switch to the Parallel (or left) position. The LE pin on the Serial header must be tied to logic high. Switches D-D are SPT switches which enable the user to manually program the parallel bits. When any input D-D is toggled UP, logic high is presented to the parallel input. When toggled DOWN, logic low is presented to the parallel input. Setting D-D to the MIDDLE toggle position presents an OPEN, which forces an on-chip logic low. Table 7 depicts the parallel programming truth table and Fig. illustrates the parallel programming timing diagram. Latched-Parallel Programming Procedure For automated latched-parallel programming, the procedure is identical to the direct-parallel method. The user only must ensure that Latched- Parallel is selected in the software. For manual latched-parallel programming, the procedure is identical to direct-parallel except now Note: Reference Fig. for Evaluation Board Schematic the LE pin on the Serial header must be logic low as the parallel bits are applied. The user must then pulse LE from V to V DD and back to V to latch the programming word into the DSA. LE must be logic low prior to programming the next word. Serial-Addressable Programming Procedure Position the Parallel/Serial (P /S) select switch to the Serial (or right) position. Prior to programming, the user must define an address setting using the ADD header pin. Jump the middle pins on the ADD header A-A (or lower) row of pins to set logic high, or jump the middle pins to the upper row of pins to set logic low. If the ADD pins are left open, then become the default address. The evaluation software is written to operate the DSA in either Parallel or Serial-Addressable Mode. Ensure that the software is set to program in Serial-Addressable mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. 8-9 Peregrine Semiconductor Corp. All rights reserved. Document No. 7-5-5 UltraCMOS RFIC Solutions Page of
PE5 5 6 Figure. Evaluation Board Schematic Peregrine Specification -8 VDD D D D D D D5 D6 D D D D D D5 D6 J HEADER 6 6 5 5 8 8 7 7 9 9 D D D D D D5 D6 SERIAL HEADER CLK CLOCK SI SI LE LE VDD C5 C C pf pf pf C6 C C C pf pf pf pf VDD J CON C9 C C8 C C.µF pf pf pf pf De-embeding trace J6 Z=5 Ohm SMA SMA J Z=5 Ohm SMA J7 Figure. Package Drawing VDD _ A D VDD PS A 5 6 7 RF 8 D D D D D5 D6 9 8 7 6 5 CP5 CP5 C C C C8 C6 SI U A PEXOX DSA 5 OHM 5X5 MLPQ VSS RF 9 5 6 CLK LE A 9 8 7 A A A_ A_ A_ Z=5 Ohm ADD A VDD A VDD A VDD HEADERX A_ A_ A_ Note: Capacitors C-C8, C, & C may be omitted. Pin 6 & 7 are ground. On the PE5 pin (shown as V SS) must also be grounded. J5 SMA R OHM R OHM C.uF C pf VSS J CON A QFN 5x5 mm MAX.9 NOM.85 MIN.8 Document No. 7-5-5 www.psemi.com 8-9 Peregrine Semiconductor Corp. All rights reserved. Page of
PE5 Figure. Tape and Reel Drawing Figure 5. Marking Specifications Tape Feed Direction Pin Device Orientation in Tape Top of Device 5 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of Lot Number Table. Ordering Information Order Code Part Marking Description Package Shipping Method PE5MLI 5 PE5 G - QFN 5x5mm-75A Green -lead 5x5mm QFN Bulk or tape cut from reel PE5MLI-Z 5 PE5 G QFN 5x5mm-C Green -lead 5x5mm QFN units / T&R EK5-5 PE5 QFN 5x5mm-EK Evaluation Kit / Box 8-9 Peregrine Semiconductor Corp. All rights reserved. Document No. 7-5-5 UltraCMOS RFIC Solutions Page of
PE5 Sales Offices The Americas Peregrine Semiconductor Corporation 98 Carroll Park Drive San Diego, CA 9 Tel: 858-7-9 Fax: 858-7-999 Europe Peregrine Semiconductor Europe Bâtiment Maine -5 rue des Quatre Vents F-98 Garches, France Tel: +--7-97 Fax : +--7-97 High-Reliability and Defense Products Americas San Diego, CA, USA Phone: 858-7-975 Fax: 88-7-999 Europe/Asia-Pacific Aix-En-Provence Cedex, France Phone: +--9-6 Fax: +--9-77 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Document No. 7-5-5 www.psemi.com Peregrine Semiconductor, Asia Pacific (APAC) Shanghai,, P.R. China Tel: +86--586-876 Fax: +86--586-765 Peregrine Semiconductor, Korea #B-67, Kolon Tripolis, Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 6-9 South Korea Tel: +8--78-99 Fax: +8--78-9 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower B-6 -- Uchisaiwai-cho, Chiyoda-ku Tokyo - Japan Tel: +8--5-5 Fax: +8--5-5 The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. 8-9 Peregrine Semiconductor Corp. All rights reserved. Page of